From fb5465ae10e39a9505634e0aaf8e1cab9710f5d7 Mon Sep 17 00:00:00 2001 From: Mart Lubbers Date: Sat, 21 Jan 2017 12:51:35 +0100 Subject: [PATCH] add ChibiOS support --- int/.gitignore | 2 +- int/Makefile | 268 +- .../src/Makefile => Makefile.linux} | 14 +- int/chconf.h | 522 + int/com/ld/stm32f767xi.ld | 188 - .../Device/ST/STM32F7xx/Include/stm32f767xx.h | 10056 ---------------- .../Device/ST/STM32F7xx/Include/stm32f7xx.h | 216 - .../ST/STM32F7xx/Include/system_stm32f7xx.h | 125 - .../Templates/gcc/startup_stm32f767xx.s | 636 - .../Source/Templates/system_stm32f7xx.c | 280 - int/com/lib/CMSIS-hal/Include/cmsis_gcc.h | 1373 --- int/com/lib/CMSIS-hal/Include/core_cm7.h | 2512 ---- int/com/lib/CMSIS-hal/Include/core_cmFunc.h | 87 - int/com/lib/CMSIS-hal/Include/core_cmInstr.h | 87 - int/com/lib/CMSIS-hal/Include/core_cmSimd.h | 96 - .../Inc/Legacy/stm32_hal_legacy.h | 3123 ----- .../STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h | 253 - .../Inc/stm32f7xx_hal_cortex.h | 467 - .../Inc/stm32f7xx_hal_def.h | 213 - .../Inc/stm32f7xx_hal_dma.h | 768 -- .../Inc/stm32f7xx_hal_dma_ex.h | 197 - .../Inc/stm32f7xx_hal_flash.h | 416 - .../Inc/stm32f7xx_hal_flash_ex.h | 608 - .../Inc/stm32f7xx_hal_gpio.h | 327 - .../Inc/stm32f7xx_hal_gpio_ex.h | 511 - .../Inc/stm32f7xx_hal_i2c.h | 711 -- .../Inc/stm32f7xx_hal_i2c_ex.h | 188 - .../Inc/stm32f7xx_hal_pwr.h | 422 - .../Inc/stm32f7xx_hal_pwr_ex.h | 280 - .../Inc/stm32f7xx_hal_rcc.h | 1306 -- .../Inc/stm32f7xx_hal_rcc_ex.h | 3233 ----- .../Inc/stm32f7xx_hal_uart.h | 1221 -- .../Inc/stm32f7xx_hal_uart_ex.h | 365 - .../STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c | 536 - .../Src/stm32f7xx_hal_adc.c | 1686 --- .../Src/stm32f7xx_hal_adc_ex.c | 1069 -- .../Src/stm32f7xx_hal_can.c | 1410 --- .../Src/stm32f7xx_hal_cec.c | 668 - .../Src/stm32f7xx_hal_cortex.c | 483 - .../Src/stm32f7xx_hal_crc.c | 522 - .../Src/stm32f7xx_hal_crc_ex.c | 242 - .../Src/stm32f7xx_hal_cryp.c | 3823 ------ .../Src/stm32f7xx_hal_cryp_ex.c | 3040 ----- .../Src/stm32f7xx_hal_dac.c | 967 -- .../Src/stm32f7xx_hal_dac_ex.c | 388 - .../Src/stm32f7xx_hal_dcmi.c | 904 -- .../Src/stm32f7xx_hal_dcmi_ex.c | 52 - .../Src/stm32f7xx_hal_dfsdm.c | 3018 ----- .../Src/stm32f7xx_hal_dma.c | 1305 -- .../Src/stm32f7xx_hal_dma2d.c | 1762 --- .../Src/stm32f7xx_hal_dma_ex.c | 328 - .../Src/stm32f7xx_hal_dsi.c | 2266 ---- .../Src/stm32f7xx_hal_eth.c | 2043 ---- .../Src/stm32f7xx_hal_flash.c | 821 -- .../Src/stm32f7xx_hal_flash_ex.c | 1038 -- .../Src/stm32f7xx_hal_gpio.c | 543 - .../Src/stm32f7xx_hal_hash.c | 1878 --- .../Src/stm32f7xx_hal_hash_ex.c | 1636 --- .../Src/stm32f7xx_hal_hcd.c | 1229 -- .../Src/stm32f7xx_hal_i2c.c | 4758 -------- .../Src/stm32f7xx_hal_i2c_ex.c | 255 - .../Src/stm32f7xx_hal_i2s.c | 1556 --- .../Src/stm32f7xx_hal_irda.c | 1571 --- .../Src/stm32f7xx_hal_iwdg.c | 282 - .../Src/stm32f7xx_hal_jpeg.c | 3403 ------ .../Src/stm32f7xx_hal_lptim.c | 1705 --- .../Src/stm32f7xx_hal_ltdc.c | 1915 --- .../Src/stm32f7xx_hal_ltdc_ex.c | 164 - .../Src/stm32f7xx_hal_mdios.c | 629 - .../Src/stm32f7xx_hal_nand.c | 1458 --- .../Src/stm32f7xx_hal_nor.c | 1044 -- .../Src/stm32f7xx_hal_pcd.c | 1311 -- .../Src/stm32f7xx_hal_pcd_ex.c | 203 - .../Src/stm32f7xx_hal_pwr.c | 609 - .../Src/stm32f7xx_hal_pwr_ex.c | 572 - .../Src/stm32f7xx_hal_qspi.c | 2337 ---- .../Src/stm32f7xx_hal_rcc.c | 1101 -- .../Src/stm32f7xx_hal_rcc_ex.c | 1340 -- .../Src/stm32f7xx_hal_rng.c | 522 - .../Src/stm32f7xx_hal_rtc.c | 1567 --- .../Src/stm32f7xx_hal_rtc_ex.c | 1831 --- .../Src/stm32f7xx_hal_sai.c | 2184 ---- .../Src/stm32f7xx_hal_sai_ex.c | 52 - .../Src/stm32f7xx_hal_sd.c | 3405 ------ .../Src/stm32f7xx_hal_sdram.c | 859 -- .../Src/stm32f7xx_hal_smartcard.c | 1359 --- .../Src/stm32f7xx_hal_smartcard_ex.c | 184 - .../Src/stm32f7xx_hal_spdifrx.c | 1257 -- .../Src/stm32f7xx_hal_spi.c | 2963 ----- .../Src/stm32f7xx_hal_sram.c | 690 -- .../Src/stm32f7xx_hal_tim.c | 5521 --------- .../Src/stm32f7xx_hal_tim_ex.c | 2574 ---- .../Src/stm32f7xx_hal_uart.c | 2185 ---- .../Src/stm32f7xx_hal_usart.c | 1997 --- .../Src/stm32f7xx_hal_wwdg.c | 322 - .../Src/stm32f7xx_ll_fmc.c | 1117 -- .../Src/stm32f7xx_ll_sdmmc.c | 509 - .../Src/stm32f7xx_ll_usb.c | 1689 --- int/com/lib/lib.mk | 93 - int/com/lib/libstm32f7xxhal.mk | 39 - int/com/pj/cube-hal-dma.awk | 33 - int/com/pj/cube-hal.mk | 76 - int/com/pj/f767-nucleo-hal.mk | 22 - int/com/pj/oocd-stm32f7xx.mk | 27 - int/com/pj/pj.mk | 243 - int/com/pj/pjhdr.mk | 41 - int/com/src/stm-common.mk | 5 - int/com/src/syscalls.mk | 11 - int/com/src/syscalls/syscalls.c | 180 - int/flash | 10 + int/halconf.h | 388 + int/interface.c | 70 + int/interface.h | 39 + .../src => }/interface_linux.c | 13 +- int/{nucleo-f767-blinky/src => }/interpret.c | 0 int/{nucleo-f767-blinky/src => }/interpret.h | 0 int/{nucleo-f767-blinky/src => }/main.c | 43 +- int/mcuconf.h | 386 + int/nucleo-f767-blinky/.gitignore | 7 - int/nucleo-f767-blinky/Makefile | 48 - .../cube/nucleo-f767-blinky/Inc/cube_dma.h | 10 - .../cube/nucleo-f767-blinky/Inc/dma.h | 72 - .../cube/nucleo-f767-blinky/Inc/gpio.h | 72 - .../cube/nucleo-f767-blinky/Inc/mxconstants.h | 109 - .../Inc/stm32f7xx_hal_conf.h | 449 - .../nucleo-f767-blinky/Inc/stm32f7xx_it.h | 58 - .../cube/nucleo-f767-blinky/Inc/usart.h | 75 - .../cube/nucleo-f767-blinky/Src/cube_main.c | 207 - .../Src/cube_stm32f7xx_it.c | 105 - .../cube/nucleo-f767-blinky/Src/dma.c | 76 - .../cube/nucleo-f767-blinky/Src/gpio.c | 252 - .../cube/nucleo-f767-blinky/Src/main.c | 204 - .../Src/stm32f7xx_hal_msp.c | 86 - .../nucleo-f767-blinky/Src/stm32f7xx_it.c | 103 - .../cube/nucleo-f767-blinky/Src/usart.c | 162 - .../nucleo-f767-blinky/nucleo-f767-blinky.ioc | 318 - int/nucleo-f767-blinky/src/interface.c | 125 - int/nucleo-f767-blinky/src/interface.h | 71 - int/nucleo-f767-blinky/src/mTaskSymbols.h | 36 - int/nucleo-f767-blinky/src/serial.h | 12 - int/{nucleo-f767-blinky/src => }/sds.c | 6 +- int/{nucleo-f767-blinky/src => }/sds.h | 6 +- int/{nucleo-f767-blinky/src => }/task.c | 6 +- int/{nucleo-f767-blinky/src => }/task.h | 6 +- 144 files changed, 1687 insertions(+), 126441 deletions(-) mode change 100755 => 100644 int/Makefile rename int/{nucleo-f767-blinky/src/Makefile => Makefile.linux} (54%) create mode 100644 int/chconf.h delete mode 100644 int/com/ld/stm32f767xi.ld delete mode 100644 int/com/lib/CMSIS-hal/Device/ST/STM32F7xx/Include/stm32f767xx.h delete mode 100644 int/com/lib/CMSIS-hal/Device/ST/STM32F7xx/Include/stm32f7xx.h delete mode 100644 int/com/lib/CMSIS-hal/Device/ST/STM32F7xx/Include/system_stm32f7xx.h delete mode 100644 int/com/lib/CMSIS-hal/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f767xx.s delete mode 100644 int/com/lib/CMSIS-hal/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c delete mode 100644 int/com/lib/CMSIS-hal/Include/cmsis_gcc.h delete mode 100644 int/com/lib/CMSIS-hal/Include/core_cm7.h delete mode 100755 int/com/lib/CMSIS-hal/Include/core_cmFunc.h delete mode 100755 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int/com/pj/pjhdr.mk delete mode 100644 int/com/src/stm-common.mk delete mode 100755 int/com/src/syscalls.mk delete mode 100755 int/com/src/syscalls/syscalls.c create mode 100755 int/flash create mode 100644 int/halconf.h create mode 100644 int/interface.c create mode 100644 int/interface.h rename int/{nucleo-f767-blinky/src => }/interface_linux.c (95%) rename int/{nucleo-f767-blinky/src => }/interpret.c (100%) rename int/{nucleo-f767-blinky/src => }/interpret.h (100%) rename int/{nucleo-f767-blinky/src => }/main.c (72%) create mode 100644 int/mcuconf.h delete mode 100644 int/nucleo-f767-blinky/.gitignore delete mode 100644 int/nucleo-f767-blinky/Makefile delete mode 100644 int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/cube_dma.h delete mode 100644 int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/dma.h delete mode 100644 int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/gpio.h delete mode 100644 int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/mxconstants.h delete mode 100644 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int/nucleo-f767-blinky/src/interface.c delete mode 100644 int/nucleo-f767-blinky/src/interface.h delete mode 100644 int/nucleo-f767-blinky/src/mTaskSymbols.h delete mode 100644 int/nucleo-f767-blinky/src/serial.h rename int/{nucleo-f767-blinky/src => }/sds.c (96%) rename int/{nucleo-f767-blinky/src => }/sds.h (75%) rename int/{nucleo-f767-blinky/src => }/task.c (93%) rename int/{nucleo-f767-blinky/src => }/task.h (78%) diff --git a/int/.gitignore b/int/.gitignore index 11d6560..c63175d 100644 --- a/int/.gitignore +++ b/int/.gitignore @@ -1,3 +1,3 @@ main *.o -build-uno +build diff --git a/int/Makefile b/int/Makefile old mode 100755 new mode 100644 index 23ecaf7..d0ea634 --- a/int/Makefile +++ b/int/Makefile @@ -1,34 +1,234 @@ -export -SHOWPJ = 1 -AUTOJ = 1 -MAKES = $(wildcard */Makefile) -DIRS = $(patsubst %/Makefile,%,$(MAKES)) -CLNS = $(patsubst %,%/cln,$(DIRS)) -BINS = $(foreach a,$(DIRS),$(a)/$(a).bin) - -all: $(BINS) -# -test -d com/tools && make -C com/tools all -# @echo made $(BINS) - -hb: $(filter homebus-%,$(BINS)) - -tools: - -test -d com/tools && make -C com/tools all - -info: - $(info $(BINS)) - $(info $(CLNS)) - $(info $(dir $(BINS))) - -$(BINS): - @${MAKE} -C $(dir $@) - -clean: $(CLNS) - -test -d com/tools && make -C com/tools clean -# -test -d com/homebus-bpi && make -C homebus-bpi clean - find . -name *.d -o -name *.o -o -name *.a -o -name *.bin -o -name *.out -o -name *.list -o -name *.map -o -name *.hex -o -name *.s19 -o -name *.sl |xargs rm -fv - -rm -rfv */o/* */filelist - -$(CLNS): - @${MAKE} -C $(dir $@) clean - @touch $@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = mTask + +# Imported source files and paths +CHIBIOS = /home/mrl/projects/ChibiOS +# Startup files. +include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f7xx.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/platform.mk +include $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F767ZI/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). +include $(CHIBIOS)/test/rt/test.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/STM32F76xxI.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(TESTSRC) \ + $(filter-out interface_linux.c,$(wildcard *.c)) + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = +ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(CHIBIOS)/os/license \ + $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m7 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes -Werror + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -DSTM + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk + +flash: build/$(PROJECT).bin + sudo openocd \ + -f interface/stlink-v2-1.cfg\ + -c "transport select hla_swd"\ + -f target/stm32f7x.cfg \ + -c init\ + -c "reset halt"\ + -c "flash write_image erase "$<" 0x08000000"\ + -c "reset run"\ + -c shutdown diff --git a/int/nucleo-f767-blinky/src/Makefile b/int/Makefile.linux similarity index 54% rename from int/nucleo-f767-blinky/src/Makefile rename to int/Makefile.linux index 65d780d..edf1195 100644 --- a/int/nucleo-f767-blinky/src/Makefile +++ b/int/Makefile.linux @@ -5,14 +5,14 @@ OBJS:=interpret.o sds.o task.o main.o interface.o all: mTaskSymbols.h $(PROG) interface.o: interface_linux.c - gcc $(CFLAGS) -c $< -o $@ + gcc $(CFLAGS) -c $< -o $@ $(PROG): $(OBJS) - gcc $(LDFLAGS) -o $@ $(OBJS) - + gcc $(LDFLAGS) -o $@ $(OBJS) + mTaskSymbols.h: - CLMFLAGS=-nr make -BC ../.. mTaskInterpret - ../../mTaskInterpret > $@ - + CLMFLAGS=-nr make -BC ../.. mTaskInterpret + ../../mTaskInterpret > $@ + clean: - $(RM) $(OBJS) $(PROG) + $(RM) $(OBJS) $(PROG) diff --git a/int/chconf.h b/int/chconf.h new file mode 100644 index 0000000..620a180 --- /dev/null +++ b/int/chconf.h @@ -0,0 +1,522 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM TRUE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#define CORTEX_VTOR_INIT 0x00200000U + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/int/com/ld/stm32f767xi.ld b/int/com/ld/stm32f767xi.ld deleted file mode 100644 index e4bf18c..0000000 --- a/int/com/ld/stm32f767xi.ld +++ /dev/null @@ -1,188 +0,0 @@ -/* -***************************************************************************** -** - -** File : LinkerScript.ld -** -** Abstract : Linker script for STM32F746ZGTx Device with -** 1024KByte FLASH, 320KByte RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : STMicroelectronics STM32 -** -** -** Distribution: The file is distributed as is, without any warranty -** of any kind. -** -***************************************************************************** -** @attention -** -**

© COPYRIGHT(c) 2014 Ac6

-** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** 1. Redistributions of source code must retain the above copyright notice, -** this list of conditions and the following disclaimer. -** 2. Redistributions in binary form must reproduce the above copyright notice, -** this list of conditions and the following disclaimer in the documentation -** and/or other materials provided with the distribution. -** 3. Neither the name of Ac6 nor the names of its contributors -** may be used to endorse or promote products derived from this software -** without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x20050000; /* end of RAM */ -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x400; /* required amount of heap */ -_Min_Stack_Size = 0x200; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ -FLASH (rx) : ORIGIN = 0x00200000, LENGTH = 2048K -RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH - - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} - - diff --git a/int/com/lib/CMSIS-hal/Device/ST/STM32F7xx/Include/stm32f767xx.h b/int/com/lib/CMSIS-hal/Device/ST/STM32F7xx/Include/stm32f767xx.h deleted file mode 100644 index 1044a52..0000000 --- a/int/com/lib/CMSIS-hal/Device/ST/STM32F7xx/Include/stm32f767xx.h +++ /dev/null @@ -1,10056 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f767xx.h - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheralÂ’s registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS_Device - * @{ - */ - -/** @addtogroup stm32f767xx - * @{ - */ - -#ifndef __STM32F767xx_H -#define __STM32F767xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief STM32F7xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum -{ -/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ - DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ - DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ - DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ - DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ - DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ - DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ - ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FMC_IRQn = 48, /*!< FMC global Interrupt */ - SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - RNG_IRQn = 80, /*!< RNG global interrupt */ - FPU_IRQn = 81, /*!< FPU global interrupt */ - UART7_IRQn = 82, /*!< UART7 global interrupt */ - UART8_IRQn = 83, /*!< UART8 global interrupt */ - SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ - SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ - SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ - SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ - LTDC_IRQn = 88, /*!< LTDC global Interrupt */ - LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ - DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ - SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ - QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ - LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ - CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ - I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ - I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ - SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ - DFSDM1_FLT0_IRQn = 99, /*!< DFSDM1 Filter 0 global Interrupt */ - DFSDM1_FLT1_IRQn = 100, /*!< DFSDM1 Filter 1 global Interrupt */ - DFSDM1_FLT2_IRQn = 101, /*!< DFSDM1 Filter 2 global Interrupt */ - DFSDM1_FLT3_IRQn = 102, /*!< DFSDM1 Filter 3 global Interrupt */ - SDMMC2_IRQn = 103, /*!< SDMMC2 global Interrupt */ - CAN3_TX_IRQn = 104, /*!< CAN3 TX Interrupt */ - CAN3_RX0_IRQn = 105, /*!< CAN3 RX0 Interrupt */ - CAN3_RX1_IRQn = 106, /*!< CAN3 RX1 Interrupt */ - CAN3_SCE_IRQn = 107, /*!< CAN3 SCE Interrupt */ - JPEG_IRQn = 108, /*!< JPEG global Interrupt */ - MDIOS_IRQn = 109 /*!< MDIO Slave global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -/** - * @brief Configuration of the Cortex-M7 Processor and Core Peripherals - */ -#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ -#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ -#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ - - -#include "system_stm32f7xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual - AND triple modes, Address offset: ADC1 base address + 0x308 */ -} ADC_Common_TypeDef; - - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - -/** - * @brief HDMI-CEC - */ - -typedef struct -{ - __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ - __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ - __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ - __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ - __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ - __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ -}CEC_TypeDef; - - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ - uint32_t RESERVED2; /*!< Reserved, 0x0C */ - __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ - __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief DFSDM module registers - */ -typedef struct -{ - __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ - __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ - __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ - __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ - __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ - __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ - __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ - __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ - __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ - __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ - __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ - __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ - __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ - __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ - __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ -} DFSDM_Filter_TypeDef; - -/** - * @brief DFSDM channel configuration registers - */ -typedef struct -{ - __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ - __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ - __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and - short circuit detector register, Address offset: 0x08 */ - __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ - __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ -} DFSDM_Channel_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DCMI - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ - __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ - __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ - __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ - __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ - __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ - __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ - __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ - __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ - __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ - __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ -} DCMI_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA stream x configuration register */ - __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ - __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ -} DMA_Stream_TypeDef; - -typedef struct -{ - __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ - __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ - __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ - __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ -} DMA_TypeDef; - - -/** - * @brief DMA2D Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ - __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ - __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ - __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ - __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ - __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ - __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ - __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ - __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ - __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ - __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ - __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ - __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ - __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ - __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ - __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ - __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ - __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ - __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ - __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ - uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ - __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ - __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ -} DMA2D_TypeDef; - - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - __IO uint32_t RESERVED8; - __IO uint32_t PTPTSSR; - uint32_t RESERVED9[565]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - __IO uint32_t DMARSWTR; - uint32_t RESERVED10[8]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ - __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ - __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */ -} FLASH_TypeDef; - - - -/** - * @brief Flexible Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FMC_Bank1_TypeDef; - -/** - * @brief Flexible Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FMC_Bank1E_TypeDef; - -/** - * @brief Flexible Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ - __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ - __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ - __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ - uint32_t RESERVED0; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ -} FMC_Bank3_TypeDef; - -/** - * @brief Flexible Memory Controller Bank5_6 - */ - -typedef struct -{ - __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ - __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ - __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ - __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ - __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ -} FMC_Bank5_6_TypeDef; - - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ -} GPIO_TypeDef; - -/** - * @brief System configuration controller - */ - -typedef struct -{ - __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ - __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ - uint32_t RESERVED; /*!< Reserved, 0x18 */ - __IO uint32_t CBR; /*!< SYSCFG Class B register, Address offset: 0x1C */ - __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ -} SYSCFG_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ - __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ - __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ - __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ - __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ - __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ - __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ - __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ - __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ - __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ -} IWDG_TypeDef; - - -/** - * @brief LCD-TFT Display Controller - */ - -typedef struct -{ - uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ - __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ - __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ - __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ - __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ - __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ - __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ - uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ - __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ - uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ - __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ - __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ - __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ - __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ - __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ - __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ -} LTDC_TypeDef; - -/** - * @brief LCD-TFT Display layer x Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ - __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ - __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ - __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ - __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ - __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ - __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ - __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ - uint32_t RESERVED0[2]; /*!< Reserved */ - __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ - __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ - __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ - uint32_t RESERVED1[3]; /*!< Reserved */ - __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ - -} LTDC_Layer_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ - __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ - __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ -} PWR_TypeDef; - - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ - __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ - __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ - __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ - __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ - __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ - uint32_t RESERVED0; /*!< Reserved, 0x1C */ - __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ - __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ - __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ - __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ - __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ - uint32_t RESERVED2; /*!< Reserved, 0x3C */ - __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ - __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ - uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ - __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ - __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ - __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ - uint32_t RESERVED4; /*!< Reserved, 0x5C */ - __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ - __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ - uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ - __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ - __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ - uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ - __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ - __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ - __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ - __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */ - __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */ - -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - uint32_t reserved; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ - __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ - __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ - __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ - __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ - __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ - __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ - __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ - __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ - __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ - __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ - __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ - __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ - __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ - __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ - __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ - __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ - __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ - __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ - __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ - __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ - __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ - __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ - __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ - __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ - __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ - __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ - __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ - __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ - __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ - __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ - __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ - __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ -} RTC_TypeDef; - - -/** - * @brief Serial Audio Interface - */ - -typedef struct -{ - __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ -} SAI_TypeDef; - -typedef struct -{ - __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ - __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ - __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ - __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ - __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ - __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ - __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ -} SAI_Block_TypeDef; - -/** - * @brief SPDIF-RX Interface - */ - -typedef struct -{ - __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ - __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ - __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ - __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ - __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ - __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ -} SPDIFRX_TypeDef; - - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ - uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ - __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */ - uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ -} SDMMC_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ - __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ - __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ - __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ - __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ - __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ - __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ -} SPI_TypeDef; - -/** - * @brief QUAD Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ - __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ - __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ - __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ - __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ - __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ - __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ - __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ - __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ - __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ - __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ - __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ -} QUADSPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ - __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ - __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ - __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */ - __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */ - __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */ - __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */ - -} TIM_TypeDef; - -/** - * @brief LPTIMIMER - */ -typedef struct -{ - __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ - __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ - __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ - __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ - __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ - __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ - __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ -} LPTIM_TypeDef; - - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ - __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ - __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ - __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ - __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ -} USART_TypeDef; - - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - - -/** - * @brief RNG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - -/** - * @} - */ - -/** - * @brief USB_OTG_Core_Registers - */ -typedef struct -{ - __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ - __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ - __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ - __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ - __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ - __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ - __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ - __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ - __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ - __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ - __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ - __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ - uint32_t Reserved30[2]; /*!< Reserved 030h */ - __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ - __IO uint32_t CID; /*!< User ID Register 03Ch */ - uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ - __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ - uint32_t Reserved6; /*!< Reserved 050h */ - __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ - __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ - __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ - __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ - uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ - __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ - __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ -} USB_OTG_GlobalTypeDef; - - -/** - * @brief USB_OTG_device_Registers - */ -typedef struct -{ - __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ - __IO uint32_t DCTL; /*!< dev Control Register 804h */ - __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ - uint32_t Reserved0C; /*!< Reserved 80Ch */ - __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ - __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ - __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ - __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ - uint32_t Reserved20; /*!< Reserved 820h */ - uint32_t Reserved9; /*!< Reserved 824h */ - __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ - __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ - __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ - __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ - __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ - __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ - uint32_t Reserved40; /*!< dedicated EP mask 840h */ - __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ - uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ - __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ -} USB_OTG_DeviceTypeDef; - - -/** - * @brief USB_OTG_IN_Endpoint-Specific_Register - */ -typedef struct -{ - __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ - uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ - __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ - uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ - __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ - __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ - __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ - uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ -} USB_OTG_INEndpointTypeDef; - - -/** - * @brief USB_OTG_OUT_Endpoint-Specific_Registers - */ -typedef struct -{ - __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ - uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ - __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ - uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ - __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ - __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ - uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ -} USB_OTG_OUTEndpointTypeDef; - - -/** - * @brief USB_OTG_Host_Mode_Register_Structures - */ -typedef struct -{ - __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ - __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ - __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ - uint32_t Reserved40C; /*!< Reserved 40Ch */ - __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ - __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ - __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ -} USB_OTG_HostTypeDef; - -/** - * @brief USB_OTG_Host_Channel_Specific_Registers - */ -typedef struct -{ - __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ - __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ - __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ - __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ - __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ - __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ - uint32_t Reserved[2]; /*!< Reserved */ -} USB_OTG_HostChannelTypeDef; -/** - * @} - */ - -/** - * @brief JPEG Codec - */ -typedef struct -{ - __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ - __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ - __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ - __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ - __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ - __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ - __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ - __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ - uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ - __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ - __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ - __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ - uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ - __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ - __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ - uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ - __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ - __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ - __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ - __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ - __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ - __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ - __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ - __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ - uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ - __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0, Address offset: 500h-65Ch */ - __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1, Address offset: 660h-7BCh */ - __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encoder, DC Huffman table 0, Address offset: 7C0h-7DCh */ - __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encoder, DC Huffman table 1, Address offset: 7E0h-7FCh */ - -} JPEG_TypeDef; - -/** - * @brief MDIOS - */ - -typedef struct -{ - __IO uint32_t CR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 00h */ - __IO uint32_t WRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 04h */ - __IO uint32_t CWRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 08h */ - __IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */ - __IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */ - __IO uint32_t SR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 14h */ - __IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */ - uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */ - __IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */ - __IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */ - __IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */ - __IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */ - __IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */ - __IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */ - __IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */ - __IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */ - __IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */ - __IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */ - __IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */ - __IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */ - __IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */ - __IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */ - __IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */ - __IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */ - __IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */ - __IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */ - __IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */ - __IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */ - __IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */ - __IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */ - __IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */ - __IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */ - __IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */ - __IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */ - __IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */ - __IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */ - __IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */ - __IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */ - __IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */ - __IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */ - __IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */ - __IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */ - __IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */ - __IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */ - __IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */ - __IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */ - __IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */ - __IO uint32_t DOUTR7; /*!< MDIOS Output Data Register (MDIOS_DOUTR7), Address offset: 19Ch */ - __IO uint32_t DOUTR8; /*!< MDIOS Output Data Register (MDIOS_DOUTR8), Address offset: 1A0h */ - __IO uint32_t DOUTR9; /*!< MDIOS Output Data Register (MDIOS_DOUTR9), Address offset: 1A4h */ - __IO uint32_t DOUTR10; /*!< MDIOS Output Data Register (MDIOS_DOUTR10), Address offset: 1A8h */ - __IO uint32_t DOUTR11; /*!< MDIOS Output Data Register (MDIOS_DOUTR11), Address offset: 1ACh */ - __IO uint32_t DOUTR12; /*!< MDIOS Output Data Register (MDIOS_DOUTR12), Address offset: 1B0h */ - __IO uint32_t DOUTR13; /*!< MDIOS Output Data Register (MDIOS_DOUTR13), Address offset: 1B4h */ - __IO uint32_t DOUTR14; /*!< MDIOS Output Data Register (MDIOS_DOUTR14), Address offset: 1B8h */ - __IO uint32_t DOUTR15; /*!< MDIOS Output Data Register (MDIOS_DOUTR15), Address offset: 1BCh */ - __IO uint32_t DOUTR16; /*!< MDIOS Output Data Register (MDIOS_DOUTR16), Address offset: 1C0h */ - __IO uint32_t DOUTR17; /*!< MDIOS Output Data Register (MDIOS_DOUTR17), Address offset: 1C4h */ - __IO uint32_t DOUTR18; /*!< MDIOS Output Data Register (MDIOS_DOUTR18), Address offset: 1C8h */ - __IO uint32_t DOUTR19; /*!< MDIOS Output Data Register (MDIOS_DOUTR19), Address offset: 1CCh */ - __IO uint32_t DOUTR20; /*!< MDIOS Output Data Register (MDIOS_DOUTR20), Address offset: 1D0h */ - __IO uint32_t DOUTR21; /*!< MDIOS Output Data Register (MDIOS_DOUTR21), Address offset: 1D4h */ - __IO uint32_t DOUTR22; /*!< MDIOS Output Data Register (MDIOS_DOUTR22), Address offset: 1D8h */ - __IO uint32_t DOUTR23; /*!< MDIOS Output Data Register (MDIOS_DOUTR23), Address offset: 1DCh */ - __IO uint32_t DOUTR24; /*!< MDIOS Output Data Register (MDIOS_DOUTR24), Address offset: 1E0h */ - __IO uint32_t DOUTR25; /*!< MDIOS Output Data Register (MDIOS_DOUTR25), Address offset: 1E4h */ - __IO uint32_t DOUTR26; /*!< MDIOS Output Data Register (MDIOS_DOUTR26), Address offset: 1E8h */ - __IO uint32_t DOUTR27; /*!< MDIOS Output Data Register (MDIOS_DOUTR27), Address offset: 1ECh */ - __IO uint32_t DOUTR28; /*!< MDIOS Output Data Register (MDIOS_DOUTR28), Address offset: 1F0h */ - __IO uint32_t DOUTR29; /*!< MDIOS Output Data Register (MDIOS_DOUTR29), Address offset: 1F4h */ - __IO uint32_t DOUTR30; /*!< MDIOS Output Data Register (MDIOS_DOUTR30), Address offset: 1F8h */ - __IO uint32_t DOUTR31; /*!< MDIOS Output Data Register (MDIOS_DOUTR31), Address offset: 1FCh */ -} MDIOS_TypeDef; - - -/** @addtogroup Peripheral_memory_map - * @{ - */ -#define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */ -#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */ -#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */ -#define RAMDTCM_BASE 0x20000000U /*!< Base address of : 128KB system data RAM accessible over DTCM */ -#define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */ -#define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */ -#define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */ -#define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */ -#define SRAM1_BASE 0x20020000U /*!< Base address of : 368KB RAM1 accessible over AXI/AHB */ -#define SRAM2_BASE 0x2007C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */ -#define FLASH_END 0x081FFFFFU /*!< FLASH end address */ - -/* Legacy define */ -#define FLASH_BASE FLASHAXI_BASE - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U) - -/*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U) -#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) -#define CAN3_BASE (APB1PERIPH_BASE + 0x3400U) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) -#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000U) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) -#define I2C4_BASE (APB1PERIPH_BASE + 0x6000U) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U) -#define CEC_BASE (APB1PERIPH_BASE + 0x6C00U) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) -#define UART7_BASE (APB1PERIPH_BASE + 0x7800U) -#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U) - -/*!< APB2 peripherals */ -#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U) -#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U) -#define USART1_BASE (APB2PERIPH_BASE + 0x1000U) -#define USART6_BASE (APB2PERIPH_BASE + 0x1400U) -#define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00U) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U) -#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U) -#define ADC_BASE (APB2PERIPH_BASE + 0x2300U) -#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) -#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U) -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U) -#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U) -#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U) -#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U) -#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U) -#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U) -#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U) -#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U) -#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U) -#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U) -#define SAI2_Block_A_BASE (SAI2_BASE + 0x004U) -#define SAI2_Block_B_BASE (SAI2_BASE + 0x024U) -#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U) -#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U) -#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U) -#define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400U) -#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U) -#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U) -#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U) -#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U) -#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80U) -#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0U) -#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0U) -#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0U) -#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U) -#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U) -#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200U) -#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280U) -#define MDIOS_BASE (APB2PERIPH_BASE + 0x7800U) -/*!< AHB1 peripherals */ -#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U) -#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U) -#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U) -#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U) -#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U) -#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U) -#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U) -#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U) -#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U) -#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U) -#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) -#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U) -#define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */ -#define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */ -#define PACKAGESIZE_BASE 0x1FFF7BF0U /*!< Package size register base address */ -#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U) -#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U) -#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U) -#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U) -#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U) -#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U) -#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U) -#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U) -#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U) -#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U) -#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U) -#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U) -#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U) -#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U) -#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U) -#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U) -#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U) -#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100U) -#define ETH_PTP_BASE (ETH_BASE + 0x0700U) -#define ETH_DMA_BASE (ETH_BASE + 0x1000U) -#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U) -/*!< AHB2 peripherals */ -#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U) -#define JPEG_BASE (AHB2PERIPH_BASE + 0x51000U) -#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U) -/*!< FMC Bankx registers base address */ -#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) -#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) -#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) -#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U) - -/* Debug MCU registers base address */ -#define DBGMCU_BASE 0xE0042000U - -/*!< USB registers base address */ -#define USB_OTG_HS_PERIPH_BASE 0x40040000U -#define USB_OTG_FS_PERIPH_BASE 0x50000000U - -#define USB_OTG_GLOBAL_BASE 0x000U -#define USB_OTG_DEVICE_BASE 0x800U -#define USB_OTG_IN_ENDPOINT_BASE 0x900U -#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U -#define USB_OTG_EP_REG_SIZE 0x20U -#define USB_OTG_HOST_BASE 0x400U -#define USB_OTG_HOST_PORT_BASE 0x440U -#define USB_OTG_HOST_CHANNEL_BASE 0x500U -#define USB_OTG_HOST_CHANNEL_SIZE 0x20U -#define USB_OTG_PCGCCTL_BASE 0xE00U -#define USB_OTG_FIFO_BASE 0x1000U -#define USB_OTG_FIFO_SIZE 0x1000U - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define I2C4 ((I2C_TypeDef *) I2C4_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define CEC ((CEC_TypeDef *) CEC_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define UART7 ((USART_TypeDef *) UART7_BASE) -#define UART8 ((USART_TypeDef *) UART8_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define USART6 ((USART_TypeDef *) USART6_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define SPI4 ((SPI_TypeDef *) SPI4_BASE) -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define SPI5 ((SPI_TypeDef *) SPI5_BASE) -#define SPI6 ((SPI_TypeDef *) SPI6_BASE) -#define SAI1 ((SAI_TypeDef *) SAI1_BASE) -#define SAI2 ((SAI_TypeDef *) SAI2_BASE) -#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) -#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) -#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) -#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) -#define LTDC ((LTDC_TypeDef *)LTDC_BASE) -#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) -#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) -#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) -#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) -#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) -#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) -#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) -#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) -#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) -#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) -#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) -#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) -#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) -#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) -#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) -#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) -#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) -#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) -#define DCMI ((DCMI_TypeDef *) DCMI_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) -#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) -#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) -#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) -#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) -#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) -#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) -#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) -#define CAN3 ((CAN_TypeDef *) CAN3_BASE) -#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) -#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) -#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) -#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) -#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) -#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) -#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) -#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) -#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) -#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) -#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) -#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) -#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) -#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) -#define JPEG ((JPEG_TypeDef *) JPEG_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD 0x00000001U /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f7xx - * @{ - */ - -#ifndef __STM32F7xx_H -#define __STM32F7xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32F7) -#define STM32F7 -#endif /* STM32F7 */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ -#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \ - !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) - /* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG, - STM32F756NG Devices */ - /* #define STM32F746xx */ /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG, - STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */ - /* #define STM32F745xx */ /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */ - /* #define STM32F765xx */ /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG, - STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */ - /* #define STM32F767xx */ /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI, - STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI, STM32F768AI Devices */ - /* #define STM32F769xx */ /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II, - STM32F769NG, STM32F769NI Devices */ - /* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI, STM32F778AI Devices */ - /* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI Devices */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_HAL_DRIVER */ -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number V1.1.0 - */ -#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F7_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ -#define __STM32F7_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\ - |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\ - |(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32F7_CMSIS_VERSION)) -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ -#if defined(STM32F756xx) - #include "stm32f756xx.h" -#elif defined(STM32F746xx) - #include "stm32f746xx.h" -#elif defined(STM32F745xx) - #include "stm32f745xx.h" -#elif defined(STM32F765xx) - #include "stm32f765xx.h" -#elif defined(STM32F767xx) - #include "stm32f767xx.h" -#elif defined(STM32F769xx) - #include "stm32f769xx.h" -#elif defined(STM32F777xx) - #include "stm32f777xx.h" -#elif defined(STM32F779xx) - #include "stm32f779xx.h" -#else - #error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - -/** @addtogroup Exported_macro - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - -/** - * @} - */ - -#ifdef USE_HAL_DRIVER - #include "stm32f7xx_hal_conf.h" -#endif /* USE_HAL_DRIVER */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32F7xx_H */ - -/** - * @} - */ - - /** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/CMSIS-hal/Device/ST/STM32F7xx/Include/system_stm32f7xx.h b/int/com/lib/CMSIS-hal/Device/ST/STM32F7xx/Include/system_stm32f7xx.h deleted file mode 100644 index 536bacd..0000000 --- a/int/com/lib/CMSIS-hal/Device/ST/STM32F7xx/Include/system_stm32f7xx.h +++ /dev/null @@ -1,125 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f7xx.h - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f7xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32F7XX_H -#define __SYSTEM_STM32F7XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32F7xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32F7xx_System_Exported_Variables - * @{ - */ - /* The SystemCoreClock variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ - - -/** - * @} - */ - -/** @addtogroup STM32F7xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F7xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F7xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32F7XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/CMSIS-hal/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f767xx.s b/int/com/lib/CMSIS-hal/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f767xx.s deleted file mode 100644 index d6e3d13..0000000 --- a/int/com/lib/CMSIS-hal/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f767xx.s +++ /dev/null @@ -1,636 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f767xx.s - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief STM32F767xx Devices vector table for GCC based toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M7 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m7 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system initialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M7. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FMC_IRQHandler /* FMC */ - .word SDMMC1_IRQHandler /* SDMMC1 */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word ETH_IRQHandler /* Ethernet */ - .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word DCMI_IRQHandler /* DCMI */ - .word 0 /* Reserved */ - .word RNG_IRQHandler /* RNG */ - .word FPU_IRQHandler /* FPU */ - .word UART7_IRQHandler /* UART7 */ - .word UART8_IRQHandler /* UART8 */ - .word SPI4_IRQHandler /* SPI4 */ - .word SPI5_IRQHandler /* SPI5 */ - .word SPI6_IRQHandler /* SPI6 */ - .word SAI1_IRQHandler /* SAI1 */ - .word LTDC_IRQHandler /* LTDC */ - .word LTDC_ER_IRQHandler /* LTDC error */ - .word DMA2D_IRQHandler /* DMA2D */ - .word SAI2_IRQHandler /* SAI2 */ - .word QUADSPI_IRQHandler /* QUADSPI */ - .word LPTIM1_IRQHandler /* LPTIM1 */ - .word CEC_IRQHandler /* HDMI_CEC */ - .word I2C4_EV_IRQHandler /* I2C4 Event */ - .word I2C4_ER_IRQHandler /* I2C4 Error */ - .word SPDIF_RX_IRQHandler /* SPDIF_RX */ - .word 0 /* Reserved */ - .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */ - .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */ - .word DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */ - .word DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */ - .word SDMMC2_IRQHandler /* SDMMC2 */ - .word CAN3_TX_IRQHandler /* CAN3 TX */ - .word CAN3_RX0_IRQHandler /* CAN3 RX0 */ - .word CAN3_RX1_IRQHandler /* CAN3 RX1 */ - .word CAN3_SCE_IRQHandler /* CAN3 SCE */ - .word JPEG_IRQHandler /* JPEG */ - .word MDIOS_IRQHandler /* MDIOS */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FMC_IRQHandler - .thumb_set FMC_IRQHandler,Default_Handler - - .weak SDMMC1_IRQHandler - .thumb_set SDMMC1_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak RNG_IRQHandler - .thumb_set RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak UART7_IRQHandler - .thumb_set UART7_IRQHandler,Default_Handler - - .weak UART8_IRQHandler - .thumb_set UART8_IRQHandler,Default_Handler - - .weak SPI4_IRQHandler - .thumb_set SPI4_IRQHandler,Default_Handler - - .weak SPI5_IRQHandler - .thumb_set SPI5_IRQHandler,Default_Handler - - .weak SPI6_IRQHandler - .thumb_set SPI6_IRQHandler,Default_Handler - - .weak SAI1_IRQHandler - .thumb_set SAI1_IRQHandler,Default_Handler - - .weak LTDC_IRQHandler - .thumb_set LTDC_IRQHandler,Default_Handler - - .weak LTDC_ER_IRQHandler - .thumb_set LTDC_ER_IRQHandler,Default_Handler - - .weak DMA2D_IRQHandler - .thumb_set DMA2D_IRQHandler,Default_Handler - - .weak SAI2_IRQHandler - .thumb_set SAI2_IRQHandler,Default_Handler - - .weak QUADSPI_IRQHandler - .thumb_set QUADSPI_IRQHandler,Default_Handler - - .weak LPTIM1_IRQHandler - .thumb_set LPTIM1_IRQHandler,Default_Handler - - .weak CEC_IRQHandler - .thumb_set CEC_IRQHandler,Default_Handler - - .weak I2C4_EV_IRQHandler - .thumb_set I2C4_EV_IRQHandler,Default_Handler - - .weak I2C4_ER_IRQHandler - .thumb_set I2C4_ER_IRQHandler,Default_Handler - - .weak SPDIF_RX_IRQHandler - .thumb_set SPDIF_RX_IRQHandler,Default_Handler - - .weak DFSDM1_FLT0_IRQHandler - .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler - - .weak DFSDM1_FLT1_IRQHandler - .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler - - .weak DFSDM1_FLT2_IRQHandler - .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler - - .weak DFSDM1_FLT3_IRQHandler - .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler - - .weak SDMMC2_IRQHandler - .thumb_set SDMMC2_IRQHandler,Default_Handler - - .weak CAN3_TX_IRQHandler - .thumb_set CAN3_TX_IRQHandler,Default_Handler - - .weak CAN3_RX0_IRQHandler - .thumb_set CAN3_RX0_IRQHandler,Default_Handler - - .weak CAN3_RX1_IRQHandler - .thumb_set CAN3_RX1_IRQHandler,Default_Handler - - .weak CAN3_SCE_IRQHandler - .thumb_set CAN3_SCE_IRQHandler,Default_Handler - - .weak JPEG_IRQHandler - .thumb_set JPEG_IRQHandler,Default_Handler - - .weak MDIOS_IRQHandler - .thumb_set MDIOS_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/int/com/lib/CMSIS-hal/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c b/int/com/lib/CMSIS-hal/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c deleted file mode 100644 index 69edfc5..0000000 --- a/int/com/lib/CMSIS-hal/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c +++ /dev/null @@ -1,280 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f7xx.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. - * - * This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f7xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f7xx_system - * @{ - */ - -/** @addtogroup STM32F7xx_System_Private_Includes - * @{ - */ - -#include "stm32f7xx.h" - -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @} - */ - -/** @addtogroup STM32F7xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F7xx_System_Private_Defines - * @{ - */ - -/************************* Miscellaneous Configuration ************************/ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/******************************************************************************/ - -/** - * @} - */ - -/** @addtogroup STM32F7xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F7xx_System_Private_Variables - * @{ - */ - - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ - uint32_t SystemCoreClock = 16000000; - const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - -/** - * @} - */ - -/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F7xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemFrequency variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/CMSIS-hal/Include/cmsis_gcc.h b/int/com/lib/CMSIS-hal/Include/cmsis_gcc.h deleted file mode 100644 index d868f2e..0000000 --- a/int/com/lib/CMSIS-hal/Include/cmsis_gcc.h +++ /dev/null @@ -1,1373 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03U) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03U) */ - - -#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); -} - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x04) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* __CMSIS_GCC_H */ diff --git a/int/com/lib/CMSIS-hal/Include/core_cm7.h b/int/com/lib/CMSIS-hal/Include/core_cm7.h deleted file mode 100644 index 20963c1..0000000 --- a/int/com/lib/CMSIS-hal/Include/core_cm7.h +++ /dev/null @@ -1,2512 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M7 - @{ - */ - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ -#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000U - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0U - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1U]; - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1U) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = SCB->MVFR0; - if ((mvfr0 & 0x00000FF0UL) == 0x220UL) - { - return 2UL; /* Double + Single precision FPU */ - } - else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) - { - return 1UL; /* Single precision FPU */ - } - else - { - return 0UL; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## Cache functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_INLINE void SCB_EnableICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_INLINE void SCB_DisableICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_INLINE void SCB_InvalidateICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_INLINE void SCB_EnableDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_INLINE void SCB_DisableDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_INLINE void SCB_InvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_INLINE void SCB_CleanDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_INLINE void SCB_CleanInvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t)addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCIMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCIMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/int/com/lib/CMSIS-hal/Include/core_cmFunc.h b/int/com/lib/CMSIS-hal/Include/core_cmFunc.h deleted file mode 100755 index ca319a5..0000000 --- a/int/com/lib/CMSIS-hal/Include/core_cmFunc.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ diff --git a/int/com/lib/CMSIS-hal/Include/core_cmInstr.h b/int/com/lib/CMSIS-hal/Include/core_cmInstr.h deleted file mode 100755 index a0a5064..0000000 --- a/int/com/lib/CMSIS-hal/Include/core_cmInstr.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/int/com/lib/CMSIS-hal/Include/core_cmSimd.h b/int/com/lib/CMSIS-hal/Include/core_cmSimd.h deleted file mode 100644 index 4d76bf9..0000000 --- a/int/com/lib/CMSIS-hal/Include/core_cmSimd.h +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************//** - * @file core_cmSimd.h - * @brief CMSIS Cortex-M SIMD Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMSIMD_H -#define __CORE_CMSIMD_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CMSIMD_H */ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/int/com/lib/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h deleted file mode 100644 index 5225db9..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ /dev/null @@ -1,3123 +0,0 @@ -/** - ****************************************************************************** - * @file stm32_hal_legacy.h - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief This file contains aliases definition for the STM32Cube HAL constants - * macros and functions maintained for legacy purpose. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32_HAL_LEGACY -#define __STM32_HAL_LEGACY - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose - * @{ - */ -#define AES_FLAG_RDERR CRYP_FLAG_RDERR -#define AES_FLAG_WRERR CRYP_FLAG_WRERR -#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF -#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR -#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR - -/** - * @} - */ - -/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose - * @{ - */ -#define ADC_RESOLUTION12b ADC_RESOLUTION_12B -#define ADC_RESOLUTION10b ADC_RESOLUTION_10B -#define ADC_RESOLUTION8b ADC_RESOLUTION_8B -#define ADC_RESOLUTION6b ADC_RESOLUTION_6B -#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN -#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED -#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV -#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV -#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV -#define REGULAR_GROUP ADC_REGULAR_GROUP -#define INJECTED_GROUP ADC_INJECTED_GROUP -#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP -#define AWD_EVENT ADC_AWD_EVENT -#define AWD1_EVENT ADC_AWD1_EVENT -#define AWD2_EVENT ADC_AWD2_EVENT -#define AWD3_EVENT ADC_AWD3_EVENT -#define OVR_EVENT ADC_OVR_EVENT -#define JQOVF_EVENT ADC_JQOVF_EVENT -#define ALL_CHANNELS ADC_ALL_CHANNELS -#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS -#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS -#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR -#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT -#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 -#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 -#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 -#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 -#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 -#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO -#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 -#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO -#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 -#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO -#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 -#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 -#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE -#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING -#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING -#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING -#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 - -#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY -#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY -#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC -#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC -#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL -#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL -#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 -/** - * @} - */ - -/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG - -/** - * @} - */ - -/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose - * @{ - */ -#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE -#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE -#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 -#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 -#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 -#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 -#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 -#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 -#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 -#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR -#if defined(STM32F373xC) || defined(STM32F378xx) -#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 -#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR -#endif /* STM32F373xC || STM32F378xx */ - -#if defined(STM32L0) || defined(STM32L4) -#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON - -#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 -#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 -#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 - -#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT -#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT -#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT -#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT -#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 -#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 -#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 -#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 -#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 -#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 -#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 - -#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW -#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH - -/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ -/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ -#if defined(COMP_CSR_LOCK) -#define COMP_FLAG_LOCK COMP_CSR_LOCK -#elif defined(COMP_CSR_COMP1LOCK) -#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK -#elif defined(COMP_CSR_COMPxLOCK) -#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK -#endif - -#if defined(STM32L4) -#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 -#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 -#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 -#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 -#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 -#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 -#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE -#endif - -#if defined(STM32L0) -#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED -#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER -#else -#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED -#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED -#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER -#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER -#endif - -#endif -/** - * @} - */ - -/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose - * @{ - */ -#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig -/** - * @} - */ - -/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE -#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define DAC1_CHANNEL_1 DAC_CHANNEL_1 -#define DAC1_CHANNEL_2 DAC_CHANNEL_2 -#define DAC2_CHANNEL_1 DAC_CHANNEL_1 -#define DAC_WAVE_NONE ((uint32_t)0x00000000U) -#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) -#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) -#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE -#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE -#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE - -/** - * @} - */ - -/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 -#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 -#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 -#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 -#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 -#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 -#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 -#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 -#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 -#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 -#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 -#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 -#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 -#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 -#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 - -#define IS_HAL_REMAPDMA IS_DMA_REMAP -#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE -#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE - - - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose - * @{ - */ - -#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE -#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD -#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD -#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD -#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS -#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES -#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES -#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE -#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE -#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE -#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE -#define OBEX_PCROP OPTIONBYTE_PCROP -#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG -#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE -#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE -#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE -#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD -#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD -#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE -#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD -#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD -#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE -#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD -#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD -#define PAGESIZE FLASH_PAGE_SIZE -#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE -#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD -#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD -#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 -#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 -#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 -#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 -#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST -#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST -#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA -#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB -#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA -#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB -#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE -#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN -#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE -#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN -#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE -#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD -#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG -#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS -#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP -#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV -#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR -#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG -#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION -#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA -#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE -#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE -#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS -#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS -#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST -#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR -#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO -#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION -#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS -#define OB_WDG_SW OB_IWDG_SW -#define OB_WDG_HW OB_IWDG_HW -#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET -#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET -#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET -#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET -#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR -#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 -#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 -#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 -/** - * @} - */ - -/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose - * @{ - */ - -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 -#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 -#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 -#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 -/** - * @} - */ - - -/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose - * @{ - */ -#if defined(STM32L4) || defined(STM32F7) -#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE -#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE -#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 -#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 -#else -#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE -#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE -#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 -#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 -#endif -/** - * @} - */ - -/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef -#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef -/** - * @} - */ - -/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose - * @{ - */ -#define GET_GPIO_SOURCE GPIO_GET_INDEX -#define GET_GPIO_INDEX GPIO_GET_INDEX - -#if defined(STM32F4) -#define GPIO_AF12_SDMMC GPIO_AF12_SDIO -#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO -#endif - -#if defined(STM32F7) -#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 -#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 -#endif - -#if defined(STM32L4) -#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 -#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 -#endif - -#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 -#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 -#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 - -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ - -#if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L1 */ - -#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH -#endif /* STM32F0 || STM32F3 || STM32F1 */ - -#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 -/** - * @} - */ - -/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose - * @{ - */ -#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 - -#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER -#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER -#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD -#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD -#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER -#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER -#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE -#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose - * @{ - */ -#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE -#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE -#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE -#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE -#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE -#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE -#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE -#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) -#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX -#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX -#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX -#endif -/** - * @} - */ - -/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose - * @{ - */ -#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE -#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose - * @{ - */ -#define KR_KEY_RELOAD IWDG_KEY_RELOAD -#define KR_KEY_ENABLE IWDG_KEY_ENABLE -#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE -#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE -/** - * @} - */ - -/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose - * @{ - */ - -#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION -#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS -#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS -#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS - -#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING -#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING -#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING - -#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION -#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS - -/* The following 3 definition have also been present in a temporary version of lptim.h */ -/* They need to be renamed also to the right name, just in case */ -#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS - -/** - * @} - */ - -/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b -#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b -#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b -#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b - -#define NAND_AddressTypedef NAND_AddressTypeDef - -#define __ARRAY_ADDRESS ARRAY_ADDRESS -#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE -#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE -#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE -#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE -/** - * @} - */ - -/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose - * @{ - */ -#define NOR_StatusTypedef HAL_NOR_StatusTypeDef -#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS -#define NOR_ONGOING HAL_NOR_STATUS_ONGOING -#define NOR_ERROR HAL_NOR_STATUS_ERROR -#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT - -#define __NOR_WRITE NOR_WRITE -#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT -/** - * @} - */ - -/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose - * @{ - */ - -#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 -#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 -#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 -#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 - -#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 -#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 -#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 -#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 - -#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 -#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 - -#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 -#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 - -#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 -#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO -#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 -#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 - -/** - * @} - */ - -/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose - * @{ - */ -#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS -#if defined(STM32F7) - #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL -#endif -/** - * @} - */ - -/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose - * @{ - */ - -/* Compact Flash-ATA registers description */ -#define CF_DATA ATA_DATA -#define CF_SECTOR_COUNT ATA_SECTOR_COUNT -#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER -#define CF_CYLINDER_LOW ATA_CYLINDER_LOW -#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH -#define CF_CARD_HEAD ATA_CARD_HEAD -#define CF_STATUS_CMD ATA_STATUS_CMD -#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE -#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA - -/* Compact Flash-ATA commands */ -#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD -#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD -#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD -#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD - -#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef -#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS -#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING -#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR -#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT -/** - * @} - */ - -/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define FORMAT_BIN RTC_FORMAT_BIN -#define FORMAT_BCD RTC_FORMAT_BCD - -#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE -#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE -#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE - -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE -#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT -#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT - -#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 - -#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE -#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 -#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 - -#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT -#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 -#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 - -/** - * @} - */ - - -/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose - * @{ - */ -#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE -#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE - -#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE -#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE -#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE -#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE - -#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE -#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE - -#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE -#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE -/** - * @} - */ - - -/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose - * @{ - */ -#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE -#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE -#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE -#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE -#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE -#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE -#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE -#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE -#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE -#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE -#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose - * @{ - */ -#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE -#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE - -#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE -#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE - -#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE -#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose - * @{ - */ -#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK -#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK - -#define TIM_DMABase_CR1 TIM_DMABASE_CR1 -#define TIM_DMABase_CR2 TIM_DMABASE_CR2 -#define TIM_DMABase_SMCR TIM_DMABASE_SMCR -#define TIM_DMABase_DIER TIM_DMABASE_DIER -#define TIM_DMABase_SR TIM_DMABASE_SR -#define TIM_DMABase_EGR TIM_DMABASE_EGR -#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 -#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 -#define TIM_DMABase_CCER TIM_DMABASE_CCER -#define TIM_DMABase_CNT TIM_DMABASE_CNT -#define TIM_DMABase_PSC TIM_DMABASE_PSC -#define TIM_DMABase_ARR TIM_DMABASE_ARR -#define TIM_DMABase_RCR TIM_DMABASE_RCR -#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 -#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 -#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 -#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 -#define TIM_DMABase_BDTR TIM_DMABASE_BDTR -#define TIM_DMABase_DCR TIM_DMABASE_DCR -#define TIM_DMABase_DMAR TIM_DMABASE_DMAR -#define TIM_DMABase_OR1 TIM_DMABASE_OR1 -#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 -#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 -#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 -#define TIM_DMABase_OR2 TIM_DMABASE_OR2 -#define TIM_DMABase_OR3 TIM_DMABASE_OR3 -#define TIM_DMABase_OR TIM_DMABASE_OR - -#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE -#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 -#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 -#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 -#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 -#define TIM_EventSource_COM TIM_EVENTSOURCE_COM -#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER -#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK -#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 - -#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER -#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS -#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS -#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS -#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS -#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS -#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS -#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS -#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS -#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS -#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS -#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS -#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS -#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS -#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS -#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS -#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS -#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS - -/** - * @} - */ - -/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose - * @{ - */ -#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING -#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose - * @{ - */ -#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE -#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE -#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE -#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE - -#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE -#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE - -#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 -#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 -#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 -#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 - -#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 -#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 -#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 -#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 - -#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE -#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK - -/** - * @} - */ - - -/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose - * @{ - */ - -#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE -#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE - -#define USARTNACK_ENABLED USART_NACK_ENABLE -#define USARTNACK_DISABLED USART_NACK_DISABLE -/** - * @} - */ - -/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose - * @{ - */ -#define CFR_BASE WWDG_CFR_BASE - -/** - * @} - */ - -/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose - * @{ - */ -#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 -#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME -#define INAK_TIMEOUT CAN_TIMEOUT_VALUE -#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE -#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) -#define CAN_TXSTATUS_OK ((uint8_t)0x01U) -#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) - -/** - * @} - */ - -/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose - * @{ - */ - -#define VLAN_TAG ETH_VLAN_TAG -#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD -#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD -#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD -#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK -#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK -#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK -#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK - -#define ETH_MMCCR ((uint32_t)0x00000100U) -#define ETH_MMCRIR ((uint32_t)0x00000104U) -#define ETH_MMCTIR ((uint32_t)0x00000108U) -#define ETH_MMCRIMR ((uint32_t)0x0000010CU) -#define ETH_MMCTIMR ((uint32_t)0x00000110U) -#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU) -#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U) -#define ETH_MMCTGFCR ((uint32_t)0x00000168U) -#define ETH_MMCRFCECR ((uint32_t)0x00000194U) -#define ETH_MMCRFAECR ((uint32_t)0x00000198U) -#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U) - -#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */ -#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */ -#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */ -#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */ -#if defined(STM32F1) -#else -#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */ -#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */ -#endif -#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */ -#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */ -#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */ -#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */ -#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */ - -/** - * @} - */ - -/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR -#define DCMI_IT_OVF DCMI_IT_OVR -#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI -#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI - -#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop -#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop -#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop - -/** - * @} - */ - -#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ - defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) -/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose - * @{ - */ -#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 -#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 -#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 -#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 -#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 - -#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 -#define CM_RGB888 DMA2D_INPUT_RGB888 -#define CM_RGB565 DMA2D_INPUT_RGB565 -#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 -#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 -#define CM_L8 DMA2D_INPUT_L8 -#define CM_AL44 DMA2D_INPUT_AL44 -#define CM_AL88 DMA2D_INPUT_AL88 -#define CM_L4 DMA2D_INPUT_L4 -#define CM_A8 DMA2D_INPUT_A8 -#define CM_A4 DMA2D_INPUT_A4 -/** - * @} - */ -#endif /* STM32L4xx || STM32F7*/ - -/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback -/** - * @} - */ - -/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef -#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef -#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish -#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish -#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish -#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish - -/*HASH Algorithm Selection*/ - -#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 -#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 -#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 -#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 - -#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH -#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC - -#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY -#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY -/** - * @} - */ - -/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode -#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode -#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode -#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode -#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode -#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode -#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) -#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect -#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) -#if defined(STM32L0) -#else -#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) -#endif -#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) -#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose - * @{ - */ -#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram -#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown -#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown -#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock -#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock -#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase -#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program - - /** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter -#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter -#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter -#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter - -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) - /** - * @} - */ - -/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose - * @{ - */ -#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD -#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg -#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown -#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor -#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg -#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown -#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor -#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler -#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD -#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler -#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback -#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive -#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive -#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC -#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC -#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM - -#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL -#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING -#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING -#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING -#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING -#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING -#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING - -#define CR_OFFSET_BB PWR_CR_OFFSET_BB -#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB - -#define DBP_BitNumber DBP_BIT_NUMBER -#define PVDE_BitNumber PVDE_BIT_NUMBER -#define PMODE_BitNumber PMODE_BIT_NUMBER -#define EWUP_BitNumber EWUP_BIT_NUMBER -#define FPDS_BitNumber FPDS_BIT_NUMBER -#define ODEN_BitNumber ODEN_BIT_NUMBER -#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER -#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER -#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER -#define BRE_BitNumber BRE_BIT_NUMBER - -#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - - /** - * @} - */ - -/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT -#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback -#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt -#define HAL_TIM_DMAError TIM_DMAError -#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt -#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback -/** - * @} - */ - -/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback -/** - * @} - */ - - -/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -/* Exported macros ------------------------------------------------------------*/ - -/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose - * @{ - */ -#define AES_IT_CC CRYP_IT_CC -#define AES_IT_ERR CRYP_IT_ERR -#define AES_FLAG_CCF CRYP_FLAG_CCF -/** - * @} - */ - -/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE -#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH -#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH -#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM -#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC -#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM -#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC -#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI -#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK -#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG -#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG -#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE -#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE - -#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY -#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 -#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS -#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER -#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER - -/** - * @} - */ - - -/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __ADC_ENABLE __HAL_ADC_ENABLE -#define __ADC_DISABLE __HAL_ADC_DISABLE -#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS -#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS -#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE -#define __ADC_IS_ENABLED ADC_IS_ENABLE -#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR -#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR -#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING -#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE - -#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION -#define __HAL_ADC_JSQR_RK ADC_JSQR_RK -#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT -#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR -#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION -#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE -#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS -#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS -#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM -#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT -#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS -#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN -#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ -#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET -#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET -#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL -#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL -#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET -#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET -#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD - -#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION -#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION -#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION -#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER -#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI -#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE -#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE -#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER -#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER -#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE - -#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT -#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT -#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL -#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM -#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET -#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE -#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE -#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER - -#define __HAL_ADC_SQR1 ADC_SQR1 -#define __HAL_ADC_SMPR1 ADC_SMPR1 -#define __HAL_ADC_SMPR2 ADC_SMPR2 -#define __HAL_ADC_SQR3_RK ADC_SQR3_RK -#define __HAL_ADC_SQR2_RK ADC_SQR2_RK -#define __HAL_ADC_SQR1_RK ADC_SQR1_RK -#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS -#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS -#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV -#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection -#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq -#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION -#define __HAL_ADC_JSQR ADC_JSQR - -#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL -#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS -#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF -#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT -#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS -#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN -#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR -#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ - -/** - * @} - */ - -/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT -#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT -#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT -#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE - -/** - * @} - */ - -/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 -#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 -#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 -#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 -#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 -#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 -#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 -#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 -#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 -#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 -#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 -#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 -#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 -#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 -#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 -#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 - -#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 -#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 -#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 -#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 -#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 -#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 -#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 -#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 -#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 -#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 -#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 -#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 -#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 -#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 - - -#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 -#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 -#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 -#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 -#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 -#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 -#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC -#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC -#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG -#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG -#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG -#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG -#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT -#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT -#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT -#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT -#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT -#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT -#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 -#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 -#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 -#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 -#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 -#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 - -/** - * @} - */ - -/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined(STM32F3) -#define COMP_START __HAL_COMP_ENABLE -#define COMP_STOP __HAL_COMP_DISABLE -#define COMP_LOCK __HAL_COMP_LOCK - -#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP6_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F302xE) || defined(STM32F302xC) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP6_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP7_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F373xC) ||defined(STM32F378xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP2_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -# endif -#else -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP2_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -#endif - -#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE - -#if defined(STM32L0) || defined(STM32L4) -/* Note: On these STM32 families, the only argument of this macro */ -/* is COMP_FLAG_LOCK. */ -/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ -/* argument. */ -#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) -#endif -/** - * @} - */ - -#if defined(STM32L0) || defined(STM32L4) -/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -/** - * @} - */ -#endif - -/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ - ((WAVE) == DAC_WAVE_NOISE)|| \ - ((WAVE) == DAC_WAVE_TRIANGLE)) - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_WRPAREA IS_OB_WRPAREA -#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM -#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM -#define IS_TYPEERASE IS_FLASH_TYPEERASE -#define IS_NBSECTORS IS_FLASH_NBSECTORS -#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE - -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 -#define __HAL_I2C_GENERATE_START I2C_GENERATE_START -#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE -#define __HAL_I2C_RISE_TIME I2C_RISE_TIME -#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD -#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST -#define __HAL_I2C_SPEED I2C_SPEED -#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE -#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ -#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS -#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE -#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ -#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB -#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB -#define __HAL_I2C_FREQRANGE I2C_FREQRANGE -/** - * @} - */ - -/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE -#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT - -/** - * @} - */ - -/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __IRDA_DISABLE __HAL_IRDA_DISABLE -#define __IRDA_ENABLE __HAL_IRDA_ENABLE - -#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE -#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION -#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE -#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION - -#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE - - -/** - * @} - */ - - -/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS -#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS -/** - * @} - */ - - -/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT -#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT -#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE - -/** - * @} - */ - - -/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose - * @{ - */ -#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD -#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX -#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX -#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX -#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX -#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L -#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H -#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM -#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES -#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX -#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT -#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION -#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET - -/** - * @} - */ - - -/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT -#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT -#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE -#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE -#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE -#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE -#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE -#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE -#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE -#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine -#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine -#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig -#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) -#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT -#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT -#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE -#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) -#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) -#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention -#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention -#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 -#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 -#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB -#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB - -#if defined (STM32F4) -#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() -#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() -#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() -#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() -#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() -#else -#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG -#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT -#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT -#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT -#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG -#endif /* STM32F4 */ -/** - * @} - */ - - -/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose - * @{ - */ - -#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI -#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI - -#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) - -#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE -#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE -#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE -#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE -#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET -#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET -#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE -#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE -#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET -#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET -#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE -#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE -#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE -#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE -#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET -#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET -#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE -#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE -#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET -#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET -#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE -#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE -#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE -#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE -#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET -#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET -#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE -#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE -#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE -#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET -#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET -#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE -#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE -#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET -#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET -#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET -#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET -#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET -#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET -#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET -#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET -#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET -#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET -#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET -#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET -#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET -#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET -#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE -#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE -#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET -#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET -#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE -#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE -#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE -#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE -#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET -#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET -#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE -#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE -#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET -#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET -#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE -#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE -#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET -#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET -#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE -#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE -#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE -#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE -#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET -#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET -#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE -#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE -#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET -#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET -#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE -#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE -#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE -#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE -#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET -#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET -#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE -#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE -#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET -#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET -#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE -#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE -#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE -#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE -#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET -#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET -#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE -#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE -#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET -#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET -#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE -#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE -#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE -#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE -#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET -#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET -#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE -#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE -#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE -#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE -#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET -#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET -#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE -#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE -#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE -#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE -#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET -#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET -#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE -#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE -#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET -#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET -#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE -#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE -#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE -#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE -#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE -#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE -#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE -#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE -#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE -#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE -#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET -#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET -#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE -#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE -#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET -#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET -#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE -#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE -#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE -#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE -#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE -#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE -#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET -#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET -#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE -#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE -#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE -#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE -#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE -#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE -#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET -#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET -#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE -#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE -#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE -#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE -#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET -#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET -#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE -#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE -#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE -#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE -#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET -#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET -#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE -#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE -#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE -#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE -#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET -#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET -#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE -#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE -#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE -#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE -#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET -#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET -#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE -#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE -#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE -#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE -#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET -#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET -#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE -#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE -#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE -#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE -#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET -#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET -#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE -#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE -#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE -#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE -#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET -#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET -#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE -#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE -#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE -#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE -#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET -#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET -#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE -#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE -#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE -#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE -#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET -#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET -#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE -#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE -#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE -#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE -#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET -#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET -#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE -#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE -#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE -#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE -#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET -#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET -#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE -#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE -#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE -#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE -#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET -#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET -#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE -#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE -#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE -#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE -#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET -#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET -#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE -#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE -#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE -#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE -#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET -#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET -#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE -#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE -#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE -#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE -#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET -#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET -#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE -#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE -#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE -#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE -#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET -#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET -#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE -#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE -#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE -#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE -#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET -#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET -#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE -#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE -#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE -#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE -#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET -#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET -#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE -#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE -#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE -#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE -#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET -#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET -#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE -#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE -#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE -#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE -#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET -#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET -#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE -#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE -#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE -#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE -#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET -#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET -#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE -#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE -#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE -#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE -#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE -#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE -#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET -#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET -#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE -#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE -#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE -#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE -#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET -#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET -#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE -#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE -#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE -#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE -#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET -#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET -#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE -#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE -#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE -#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE -#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET -#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET -#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE -#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE -#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE -#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE -#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE -#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE -#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE -#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE -#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE -#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE -#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET -#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET -#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE -#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE -#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE -#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE -#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET -#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET -#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE -#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE -#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE -#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE -#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET -#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET -#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE -#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE -#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET -#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET -#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE -#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE -#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET -#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET -#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE -#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE -#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET -#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET -#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE -#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE -#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET -#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET -#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE -#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE -#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET -#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET -#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE -#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE -#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE -#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE -#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET -#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET -#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE -#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE -#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE -#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE -#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET -#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET -#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE -#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE -#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE -#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE -#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET -#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET -#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE -#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE -#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE -#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE -#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET -#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET -#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE -#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE -#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE -#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE -#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET -#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET -#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE -#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE -#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE -#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE -#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET -#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET -#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE -#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE -#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE -#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE -#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET -#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET -#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE -#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE -#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE -#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE -#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET -#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET -#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE -#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE -#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE -#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE -#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET -#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET -#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE -#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE -#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE -#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE -#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET -#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET -#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE -#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE -#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET -#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET -#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE -#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE -#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE -#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE -#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET -#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET -#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE -#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE -#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE -#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET -#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET -#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE -#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE -#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE -#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET -#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET -#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE -#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE -#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE -#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE -#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET -#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET -#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE -#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE -#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE -#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE -#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET -#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET -#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE -#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE -#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE -#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE -#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET -#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET -#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE -#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE -#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE -#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET -#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET -#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE -#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE -#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE -#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET -#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET -#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE -#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE -#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET -#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET -#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE -#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE -#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET -#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET -#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE -#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE -#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET -#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE -#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE -#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE -#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE -#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET -#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE -#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE -#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE -#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE -#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET -#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET -#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE -#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE -#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET -#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET -#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE -#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE -#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE -#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE -#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET -#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET -#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE -#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE -#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE -#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE -#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE -#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE -#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET -#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET -#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE -#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE - -#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET -#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET -#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE -#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE -#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE -#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE -#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE -#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE -#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE -#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE -#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE -#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE -#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE -#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE -#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE -#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE -#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE -#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET -#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET -#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE -#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE -#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE -#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE -#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE -#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET -#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET -#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE -#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE -#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE -#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE -#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET -#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET -#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE -#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE -#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE -#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE -#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET -#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET -#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE -#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE -#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE -#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE -#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE -#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE -#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE -#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE -#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE -#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE -#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE -#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE -#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE -#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE -#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE -#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE -#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE -#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE -#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE -#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET -#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET -#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE -#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE -#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE -#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE -#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET -#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET -#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE -#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE -#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE -#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE -#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET -#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET -#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE -#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE -#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE -#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE -#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET -#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET -#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE -#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE -#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE -#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE -#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET -#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE -#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE -#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE -#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE -#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE -#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE -#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET -#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET -#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE -#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE -#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE -#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE -#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET -#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET -#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE -#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE -#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE -#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE -#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET -#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET -#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE -#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE -#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE -#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE -#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED -#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET -#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE -#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE -#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE -#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE -#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE -#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE -#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE -#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET -#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET -#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE -#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE -#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE -#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE -#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET -#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET -#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE - -/* alias define maintained for legacy */ -#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET -#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET - -#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE -#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE -#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE -#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE -#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE -#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE -#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE -#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE -#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE -#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE -#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE -#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE -#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE -#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE -#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE -#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE -#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE -#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE -#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE -#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE - -#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET -#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET -#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET -#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET -#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET -#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET -#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET -#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET -#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET -#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET -#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET -#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET -#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET -#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET -#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET -#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET -#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET -#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET -#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET -#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET - -#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED -#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED -#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED -#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED -#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED -#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED -#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED -#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED -#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED -#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED -#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED -#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED -#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED -#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED -#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED -#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED -#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED -#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED -#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED -#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED -#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED -#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED -#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED -#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED -#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED -#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED -#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED -#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED -#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED -#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED -#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED -#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED -#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED -#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED -#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED -#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED -#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED -#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED -#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED -#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED -#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED -#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED -#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED -#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED -#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED -#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED -#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED -#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED -#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED -#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED -#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED -#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED -#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED -#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED -#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED -#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED -#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED -#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED -#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED -#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED -#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED -#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED -#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED -#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED -#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED -#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED -#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED -#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED -#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED -#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED -#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED -#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED -#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED -#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED -#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED -#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED -#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED -#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED -#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED -#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED -#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED -#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED -#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED -#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED -#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED -#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED -#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED -#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED -#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED -#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED -#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED -#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED -#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED -#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED -#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED -#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED -#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED -#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED -#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED -#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED -#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED -#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED -#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED -#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED -#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED -#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED -#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED -#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED -#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED -#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED -#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED -#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED -#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED -#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED -#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED -#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED - -#if defined(STM32F4) -#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE -#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE -#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED -#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED -#define Sdmmc1ClockSelection SdioClockSelection -#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO -#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 -#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK -#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG -#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE -#endif - -#if defined(STM32F7) || defined(STM32L4) -#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET -#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET -#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE -#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE -#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE -#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE -#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED -#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED -#define SdioClockSelection Sdmmc1ClockSelection -#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 -#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG -#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE -#endif - -#if defined(STM32F7) -#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 -#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK -#endif - -#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG -#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG - -#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE - -#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE -#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE -#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK -#define IS_RCC_HCLK_DIV IS_RCC_PCLK -#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK - -#define RCC_IT_HSI14 RCC_IT_HSI14RDY - -#if defined(STM32L0) -#define RCC_IT_LSECSS RCC_IT_CSSLSE -#define RCC_IT_CSS RCC_IT_CSSHSE -#endif - -#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE -#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG -#define RCC_MCO_NODIV RCC_MCODIV_1 -#define RCC_MCO_DIV1 RCC_MCODIV_1 -#define RCC_MCO_DIV2 RCC_MCODIV_2 -#define RCC_MCO_DIV4 RCC_MCODIV_4 -#define RCC_MCO_DIV8 RCC_MCODIV_8 -#define RCC_MCO_DIV16 RCC_MCODIV_16 -#define RCC_MCO_DIV32 RCC_MCODIV_32 -#define RCC_MCO_DIV64 RCC_MCODIV_64 -#define RCC_MCO_DIV128 RCC_MCODIV_128 -#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK -#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI -#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE -#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK -#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI -#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 -#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 -#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE -#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK -#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK -#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 - -#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK - -#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 -#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL -#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI -#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL -#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL -#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 -#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 -#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 - -#define HSION_BitNumber RCC_HSION_BIT_NUMBER -#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER -#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER -#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER -#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER -#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER -#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER -#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER -#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER -#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER -#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER -#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER -#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER -#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER -#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER -#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER -#define LSION_BitNumber RCC_LSION_BIT_NUMBER -#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER -#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER -#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER -#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER -#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER -#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER -#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER -#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER -#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER -#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS -#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS -#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS -#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS -#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE -#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE - -#define CR_HSION_BB RCC_CR_HSION_BB -#define CR_CSSON_BB RCC_CR_CSSON_BB -#define CR_PLLON_BB RCC_CR_PLLON_BB -#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB -#define CR_MSION_BB RCC_CR_MSION_BB -#define CSR_LSION_BB RCC_CSR_LSION_BB -#define CSR_LSEON_BB RCC_CSR_LSEON_BB -#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB -#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB -#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB -#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB -#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB -#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB -#define CR_HSEON_BB RCC_CR_HSEON_BB -#define CSR_RMVF_BB RCC_CSR_RMVF_BB -#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB -#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB - -#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE -#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE -#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE -#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE -#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE - -#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT - -#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN -#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF - -#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 -#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ -#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP -#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ -#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE -#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 - -#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE -#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE -#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED -#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED -#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET -#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET -#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE -#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE -#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED -#define DfsdmClockSelection Dfsdm1ClockSelection -#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 -#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK -#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK -#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG -#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE - -/** - * @} - */ - -/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose - * @{ - */ -#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) - -/** - * @} - */ - -/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG -#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT -#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT - -#if defined (STM32F1) -#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() - -#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() - -#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() - -#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() - -#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() -#else -#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) -#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) -#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) -#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) -#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) -#endif /* STM32F1 */ - -#define IS_ALARM IS_RTC_ALARM -#define IS_ALARM_MASK IS_RTC_ALARM_MASK -#define IS_TAMPER IS_RTC_TAMPER -#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE -#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER -#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT -#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE -#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION -#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE -#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ -#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION -#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER -#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK -#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER - -#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE -#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE - -/** - * @} - */ - -/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose - * @{ - */ - -#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE -#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS - -#if defined(STM32F4) -#define SD_SDMMC_DISABLED SD_SDIO_DISABLED -#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY -#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED -#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION -#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND -#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT -#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED -#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE -#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE -#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE -#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL -#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT -#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT -#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG -#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG -#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT -#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT -#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS -#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT -#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND -/* alias CMSIS */ -#define SDMMC1_IRQn SDIO_IRQn -#define SDMMC1_IRQHandler SDIO_IRQHandler -#endif - -#if defined(STM32F7) || defined(STM32L4) -#define SD_SDIO_DISABLED SD_SDMMC_DISABLED -#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY -#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED -#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION -#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND -#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT -#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED -#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE -#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE -#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE -#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE -#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT -#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT -#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG -#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG -#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT -#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT -#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS -#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT -#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND -/* alias CMSIS for compatibilities */ -#define SDIO_IRQn SDMMC1_IRQn -#define SDIO_IRQHandler SDMMC1_IRQHandler -#endif -/** - * @} - */ - -/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT -#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT -#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE -#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE -#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE -#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE - -#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE -#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE - -#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE - -/** - * @} - */ - -/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 -#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 -#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START -#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH -#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR -#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE -#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE -#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_SPI_1LINE_TX SPI_1LINE_TX -#define __HAL_SPI_1LINE_RX SPI_1LINE_RX -#define __HAL_SPI_RESET_CRC SPI_RESET_CRC - -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE -#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION -#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE -#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION - -#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD - -#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE -#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE - -/** - * @} - */ - - -/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT -#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT -#define __USART_ENABLE __HAL_USART_ENABLE -#define __USART_DISABLE __HAL_USART_DISABLE - -#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE -#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE - -/** - * @} - */ - -/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose - * @{ - */ -#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE - -#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE -#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE -#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE -#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE - -#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE -#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE -#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE -#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE - -#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE - -#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE -#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT - -#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE -#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT - -#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup -#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup - -#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo -#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE -#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE - -#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE -#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT - -#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE - -#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN -#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER -#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER -#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER -#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD -#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD -#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION -#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION -#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER -#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER -#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE -#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE - -#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 -/** - * @} - */ - -/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT -#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT -#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG -#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER -#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER -#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER - -#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE -#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE -#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE -/** - * @} - */ - -/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_LTDC_LAYER LTDC_LAYER -/** - * @} - */ - -/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose - * @{ - */ -#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE -#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE -#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE -#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE -#define SAI_STREOMODE SAI_STEREOMODE -#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY -#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL -#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL -#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL -#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL -#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL -#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE -#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 -#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE -/** - * @} - */ - - -/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* ___STM32_HAL_LEGACY */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h b/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h deleted file mode 100644 index 1de6b66..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h +++ /dev/null @@ -1,253 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal.h - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief This file contains all the functions prototypes for the HAL - * module driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_H -#define __STM32F7xx_HAL_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_conf.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup HAL - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants - * @{ - */ - -/** @defgroup SYSCFG_BootMode Boot Mode - * @{ - */ -#define SYSCFG_MEM_BOOT_ADD0 ((uint32_t)0x00000000U) -#define SYSCFG_MEM_BOOT_ADD1 SYSCFG_MEMRMP_MEM_BOOT -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup HAL_Exported_Macros HAL Exported Macros - * @{ - */ - -/** @brief Freeze/Unfreeze Peripherals in Debug mode - */ -#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) -#define __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)) -#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) -#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) -#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) -#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP)) -#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP)) - -#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) -#define __HAL_DBGMCU_UNFREEZE_LPTIM1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)) -#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) -#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) -#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) -#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP)) -#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP)) - - -/** @brief FMC (NOR/RAM) mapped at 0x60000000 and SDRAM mapped at 0xC0000000 - */ -#define __HAL_SYSCFG_REMAPMEMORY_FMC() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC)) - - -/** @brief FMC/SDRAM mapped at 0x60000000 (NOR/RAM) mapped at 0xC0000000 - */ -#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\ - SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\ - }while(0); -/** - * @brief Return the memory boot mapping as configured by user. - * @retval The boot mode as configured by user. The returned value can be one - * of the following values: - * @arg @ref SYSCFG_MEM_BOOT_ADD0 - * @arg @ref SYSCFG_MEM_BOOT_ADD1 - */ -#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT) - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -/** @brief SYSCFG Break Cortex-M7 Lockup lock. - * Enable and lock the connection of Cortex-M7 LOCKUP (Hardfault) output to TIM1/8 Break input. - * @note The selected configuration is locked and can be unlocked only by system reset. - */ -#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL) - -/** @brief SYSCFG Break PVD lock. - * Enable and lock the PVD connection to Timer1/8 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register. - * @note The selected configuration is locked and can be unlocked only by system reset. - */ -#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_PVDL) -#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup HAL_Exported_Functions - * @{ - */ -/** @addtogroup HAL_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions ******************************/ -HAL_StatusTypeDef HAL_Init(void); -HAL_StatusTypeDef HAL_DeInit(void); -void HAL_MspInit(void); -void HAL_MspDeInit(void); -HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); -/** - * @} - */ - -/** @addtogroup HAL_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ************************************************/ -void HAL_IncTick(void); -void HAL_Delay(__IO uint32_t Delay); -uint32_t HAL_GetTick(void); -void HAL_SuspendTick(void); -void HAL_ResumeTick(void); -uint32_t HAL_GetHalVersion(void); -uint32_t HAL_GetREVID(void); -uint32_t HAL_GetDEVID(void); -void HAL_DBGMCU_EnableDBGSleepMode(void); -void HAL_DBGMCU_DisableDBGSleepMode(void); -void HAL_DBGMCU_EnableDBGStopMode(void); -void HAL_DBGMCU_DisableDBGStopMode(void); -void HAL_DBGMCU_EnableDBGStandbyMode(void); -void HAL_DBGMCU_DisableDBGStandbyMode(void); -void HAL_EnableCompensationCell(void); -void HAL_DisableCompensationCell(void); -void HAL_EnableFMCMemorySwapping(void); -void HAL_DisableFMCMemorySwapping(void); -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -void HAL_EnableMemorySwappingBank(void); -void HAL_DisableMemorySwappingBank(void); -#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup HAL_Private_Variables HAL Private Variables - * @{ - */ -/** - * @} - */ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup HAL_Private_Constants HAL Private Constants - * @{ - */ -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h b/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h deleted file mode 100644 index 68ba2ef..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h +++ /dev/null @@ -1,467 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_cortex.h - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Header file of CORTEX HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_CORTEX_H -#define __STM32F7xx_HAL_CORTEX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup CORTEX - * @{ - */ -/* Exported types ------------------------------------------------------------*/ -/** @defgroup CORTEX_Exported_Types Cortex Exported Types - * @{ - */ - -#if (__MPU_PRESENT == 1) -/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition - * @brief MPU Region initialization structure - * @{ - */ -typedef struct -{ - uint8_t Enable; /*!< Specifies the status of the region. - This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ - uint8_t Number; /*!< Specifies the number of the region to protect. - This parameter can be a value of @ref CORTEX_MPU_Region_Number */ - uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ - uint8_t Size; /*!< Specifies the size of the region to protect. - This parameter can be a value of @ref CORTEX_MPU_Region_Size */ - uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint8_t TypeExtField; /*!< Specifies the TEX field level. - This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ - uint8_t AccessPermission; /*!< Specifies the region access permission type. - This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ - uint8_t DisableExec; /*!< Specifies the instruction access status. - This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ - uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. - This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ - uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. - This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ - uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. - This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ -}MPU_Region_InitTypeDef; -/** - * @} - */ -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants - * @{ - */ - -/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group - * @{ - */ -#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ -/** - * @} - */ - -/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source - * @{ - */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) -#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) - -/** - * @} - */ - -#if (__MPU_PRESENT == 1) -/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control - * @{ - */ -#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) -#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U) -#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U) -#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable - * @{ - */ -#define MPU_REGION_ENABLE ((uint8_t)0x01U) -#define MPU_REGION_DISABLE ((uint8_t)0x00U) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access - * @{ - */ -#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U) -#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable - * @{ - */ -#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U) -#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable - * @{ - */ -#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U) -#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable - * @{ - */ -#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U) -#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels - * @{ - */ -#define MPU_TEX_LEVEL0 ((uint8_t)0x00U) -#define MPU_TEX_LEVEL1 ((uint8_t)0x01U) -#define MPU_TEX_LEVEL2 ((uint8_t)0x02U) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size - * @{ - */ -#define MPU_REGION_SIZE_32B ((uint8_t)0x04U) -#define MPU_REGION_SIZE_64B ((uint8_t)0x05U) -#define MPU_REGION_SIZE_128B ((uint8_t)0x06U) -#define MPU_REGION_SIZE_256B ((uint8_t)0x07U) -#define MPU_REGION_SIZE_512B ((uint8_t)0x08U) -#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U) -#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) -#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) -#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) -#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) -#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) -#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) -#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U) -#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U) -#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U) -#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U) -#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U) -#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U) -#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U) -#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U) -#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U) -#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U) -#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) -#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) -#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) -#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) -#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) -#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes - * @{ - */ -#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U) -#define MPU_REGION_PRIV_RW ((uint8_t)0x01U) -#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U) -#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U) -#define MPU_REGION_PRIV_RO ((uint8_t)0x05U) -#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number - * @{ - */ -#define MPU_REGION_NUMBER0 ((uint8_t)0x00U) -#define MPU_REGION_NUMBER1 ((uint8_t)0x01U) -#define MPU_REGION_NUMBER2 ((uint8_t)0x02U) -#define MPU_REGION_NUMBER3 ((uint8_t)0x03U) -#define MPU_REGION_NUMBER4 ((uint8_t)0x04U) -#define MPU_REGION_NUMBER5 ((uint8_t)0x05U) -#define MPU_REGION_NUMBER6 ((uint8_t)0x06U) -#define MPU_REGION_NUMBER7 ((uint8_t)0x07U) -/** - * @} - */ -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - - -/* Exported Macros -----------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup CORTEX_Exported_Functions - * @{ - */ - -/** @addtogroup CORTEX_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); -void HAL_NVIC_SystemReset(void); -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); -/** - * @} - */ - -/** @addtogroup CORTEX_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ***********************************************/ -#if (__MPU_PRESENT == 1) -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); -#endif /* __MPU_PRESENT */ -uint32_t HAL_NVIC_GetPriorityGrouping(void); -void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); -uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); -void HAL_SYSTICK_IRQHandler(void); -void HAL_SYSTICK_Callback(void); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup CORTEX_Private_Macros CORTEX Private Macros - * @{ - */ -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ - ((GROUP) == NVIC_PRIORITYGROUP_1) || \ - ((GROUP) == NVIC_PRIORITYGROUP_2) || \ - ((GROUP) == NVIC_PRIORITYGROUP_3) || \ - ((GROUP) == NVIC_PRIORITYGROUP_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) - -#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) - -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ - ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) - -#if (__MPU_PRESENT == 1) -#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ - ((STATE) == MPU_REGION_DISABLE)) - -#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ - ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) - -#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ - ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) - -#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ - ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) - -#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ - ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) - -#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ - ((TYPE) == MPU_TEX_LEVEL1) || \ - ((TYPE) == MPU_TEX_LEVEL2)) - -#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ - ((TYPE) == MPU_REGION_PRIV_RW) || \ - ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ - ((TYPE) == MPU_REGION_FULL_ACCESS) || \ - ((TYPE) == MPU_REGION_PRIV_RO) || \ - ((TYPE) == MPU_REGION_PRIV_RO_URO)) - -#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ - ((NUMBER) == MPU_REGION_NUMBER1) || \ - ((NUMBER) == MPU_REGION_NUMBER2) || \ - ((NUMBER) == MPU_REGION_NUMBER3) || \ - ((NUMBER) == MPU_REGION_NUMBER4) || \ - ((NUMBER) == MPU_REGION_NUMBER5) || \ - ((NUMBER) == MPU_REGION_NUMBER6) || \ - ((NUMBER) == MPU_REGION_NUMBER7)) - -#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ - ((SIZE) == MPU_REGION_SIZE_64B) || \ - ((SIZE) == MPU_REGION_SIZE_128B) || \ - ((SIZE) == MPU_REGION_SIZE_256B) || \ - ((SIZE) == MPU_REGION_SIZE_512B) || \ - ((SIZE) == MPU_REGION_SIZE_1KB) || \ - ((SIZE) == MPU_REGION_SIZE_2KB) || \ - ((SIZE) == MPU_REGION_SIZE_4KB) || \ - ((SIZE) == MPU_REGION_SIZE_8KB) || \ - ((SIZE) == MPU_REGION_SIZE_16KB) || \ - ((SIZE) == MPU_REGION_SIZE_32KB) || \ - ((SIZE) == MPU_REGION_SIZE_64KB) || \ - ((SIZE) == MPU_REGION_SIZE_128KB) || \ - ((SIZE) == MPU_REGION_SIZE_256KB) || \ - ((SIZE) == MPU_REGION_SIZE_512KB) || \ - ((SIZE) == MPU_REGION_SIZE_1MB) || \ - ((SIZE) == MPU_REGION_SIZE_2MB) || \ - ((SIZE) == MPU_REGION_SIZE_4MB) || \ - ((SIZE) == MPU_REGION_SIZE_8MB) || \ - ((SIZE) == MPU_REGION_SIZE_16MB) || \ - ((SIZE) == MPU_REGION_SIZE_32MB) || \ - ((SIZE) == MPU_REGION_SIZE_64MB) || \ - ((SIZE) == MPU_REGION_SIZE_128MB) || \ - ((SIZE) == MPU_REGION_SIZE_256MB) || \ - ((SIZE) == MPU_REGION_SIZE_512MB) || \ - ((SIZE) == MPU_REGION_SIZE_1GB) || \ - ((SIZE) == MPU_REGION_SIZE_2GB) || \ - ((SIZE) == MPU_REGION_SIZE_4GB)) - -#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup CORTEX_Private_Functions CORTEX Private Functions - * @brief CORTEX private functions - * @{ - */ - -#if (__MPU_PRESENT == 1) -/** - * @brief Disables the MPU - * @retval None - */ -__STATIC_INLINE void HAL_MPU_Disable(void) -{ - /* Disable fault exceptions */ - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; - - /* Disable the MPU */ - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; -} - -/** - * @brief Enables the MPU - * @param MPU_Control: Specifies the control mode of the MPU during hard fault, - * NMI, FAULTMASK and privileged access to the default memory - * This parameter can be one of the following values: - * @arg MPU_HFNMI_PRIVDEF_NONE - * @arg MPU_HARDFAULT_NMI - * @arg MPU_PRIVILEGED_DEFAULT - * @arg MPU_HFNMI_PRIVDEF - * @retval None - */ -__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control) -{ - /* Enable the MPU */ - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; - - /* Enable fault exceptions */ - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -} -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_CORTEX_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h b/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h deleted file mode 100644 index b928c55..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h +++ /dev/null @@ -1,213 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_def.h - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief This file contains HAL common defines, enumeration, macros and - * structures definitions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_DEF -#define __STM32F7xx_HAL_DEF - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" -#include "Legacy/stm32_hal_legacy.h" -#include -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief HAL Status structures definition - */ -typedef enum -{ - HAL_OK = 0x00U, - HAL_ERROR = 0x01U, - HAL_BUSY = 0x02U, - HAL_TIMEOUT = 0x03U -} HAL_StatusTypeDef; - -/** - * @brief HAL Lock structures definition - */ -typedef enum -{ - HAL_UNLOCKED = 0x00, - HAL_LOCKED = 0x01 -} HAL_LockTypeDef; - -/* Exported macro ------------------------------------------------------------*/ -#define HAL_MAX_DELAY 0xFFFFFFFFU - -#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET) -#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) - -#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ - do{ \ - (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ - (__DMA_HANDLE__).Parent = (__HANDLE__); \ - } while(0) - -#define UNUSED(x) ((void)(x)) - -/** @brief Reset the Handle's State field. - * @param __HANDLE__: specifies the Peripheral Handle. - * @note This macro can be used for the following purpose: - * - When the Handle is declared as local variable; before passing it as parameter - * to HAL_PPP_Init() for the first time, it is mandatory to use this macro - * to set to 0 the Handle's "State" field. - * Otherwise, "State" field may have any random value and the first time the function - * HAL_PPP_Init() is called, the low level hardware initialization will be missed - * (i.e. HAL_PPP_MspInit() will not be executed). - * - When there is a need to reconfigure the low level hardware: instead of calling - * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). - * In this later function, when the Handle's "State" field is set to 0, it will execute the function - * HAL_PPP_MspInit() which will reconfigure the low level hardware. - * @retval None - */ -#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) - -#if (USE_RTOS == 1) - /* Reserved for future use */ - #error "USE_RTOS should be 0 in the current HAL release" -#else - #define __HAL_LOCK(__HANDLE__) \ - do{ \ - if((__HANDLE__)->Lock == HAL_LOCKED) \ - { \ - return HAL_BUSY; \ - } \ - else \ - { \ - (__HANDLE__)->Lock = HAL_LOCKED; \ - } \ - }while (0) - - #define __HAL_UNLOCK(__HANDLE__) \ - do{ \ - (__HANDLE__)->Lock = HAL_UNLOCKED; \ - }while (0) -#endif /* USE_RTOS */ - -#if defined ( __GNUC__ ) - #ifndef __weak - #define __weak __attribute__((weak)) - #endif /* __weak */ - #ifndef __packed - #define __packed __attribute__((__packed__)) - #endif /* __packed */ -#endif /* __GNUC__ */ - - -/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined (__GNUC__) /* GNU Compiler */ - #ifndef __ALIGN_END - #define __ALIGN_END __attribute__ ((aligned (4))) - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #define __ALIGN_BEGIN - #endif /* __ALIGN_BEGIN */ -#else - #ifndef __ALIGN_END - #define __ALIGN_END - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) - #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN - #endif /* __CC_ARM */ - #endif /* __ALIGN_BEGIN */ -#endif /* __GNUC__ */ - - -/** - * @brief __RAM_FUNC definition - */ -#if defined ( __CC_ARM ) -/* ARM Compiler - ------------ - RAM functions are defined using the toolchain options. - Functions that are executed in RAM should reside in a separate source module. - Using the 'Options for File' dialog you can simply change the 'Code / Const' - area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the 'Options for Target' - dialog. -*/ -#define __RAM_FUNC HAL_StatusTypeDef - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- - RAM functions are defined using a specific toolchain keyword "__ramfunc". -*/ -#define __RAM_FUNC __ramfunc HAL_StatusTypeDef - -#elif defined ( __GNUC__ ) -/* GNU Compiler - ------------ - RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". -*/ -#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc"))) - -#endif - -/** - * @brief __NOINLINE definition - */ -#if defined ( __CC_ARM ) || defined ( __GNUC__ ) -/* ARM & GNUCompiler - ---------------- -*/ -#define __NOINLINE __attribute__ ( (noinline) ) - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- -*/ -#define __NOINLINE _Pragma("optimize = no_inline") - -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ___STM32F7xx_HAL_DEF */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h b/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h deleted file mode 100644 index 5b498cc..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h +++ /dev/null @@ -1,768 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dma.h - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Header file of DMA HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_DMA_H -#define __STM32F7xx_HAL_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Types DMA Exported Types - * @brief DMA Exported Types - * @{ - */ - -/** - * @brief DMA Configuration Structure definition - */ -typedef struct -{ - uint32_t Channel; /*!< Specifies the channel used for the specified stream. - This parameter can be a value of @ref DMAEx_Channel_selection */ - - uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_Data_transfer_direction */ - - uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. - This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ - - uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. - This parameter can be a value of @ref DMA_Memory_incremented_mode */ - - uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_Peripheral_data_size */ - - uint32_t MemDataAlignment; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_Memory_data_size */ - - uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. - This parameter can be a value of @ref DMA_mode - @note The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Stream */ - - uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. - This parameter can be a value of @ref DMA_Priority_level */ - - uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. - This parameter can be a value of @ref DMA_FIFO_direct_mode - @note The Direct mode (FIFO mode disabled) cannot be used if the - memory-to-memory data transfer is configured on the selected stream */ - - uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. - This parameter can be a value of @ref DMA_FIFO_threshold_level */ - - uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. - It specifies the amount of data to be transferred in a single non interruptible - transaction. - This parameter can be a value of @ref DMA_Memory_burst - @note The burst mode is possible only if the address Increment mode is enabled. */ - - uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. - It specifies the amount of data to be transferred in a single non interruptible - transaction. - This parameter can be a value of @ref DMA_Peripheral_burst - @note The burst mode is possible only if the address Increment mode is enabled. */ -}DMA_InitTypeDef; - -/** - * @brief HAL DMA State structures definition - */ -typedef enum -{ - HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ - HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ - HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ - HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ - HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ - HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ -}HAL_DMA_StateTypeDef; - -/** - * @brief HAL DMA Error Code structure definition - */ -typedef enum -{ - HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ - HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ -}HAL_DMA_LevelCompleteTypeDef; - -/** - * @brief HAL DMA Error Code structure definition - */ -typedef enum -{ - HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ - HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ - HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ - HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ - HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ - HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ - HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ -}HAL_DMA_CallbackIDTypeDef; - -/** - * @brief DMA handle Structure definition - */ -typedef struct __DMA_HandleTypeDef -{ - DMA_Stream_TypeDef *Instance; /*!< Register base address */ - - DMA_InitTypeDef Init; /*!< DMA communication parameters */ - - HAL_LockTypeDef Lock; /*!< DMA locking object */ - - __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ - - void *Parent; /*!< Parent object state */ - - void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ - - void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ - - void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ - - void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ - - void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ - - void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ - - __IO uint32_t ErrorCode; /*!< DMA Error code */ - - uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ - - uint32_t StreamIndex; /*!< DMA Stream Index */ - -}DMA_HandleTypeDef; - -/** - * @} - */ - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants DMA Exported Constants - * @brief DMA Exported constants - * @{ - */ - -/** @defgroup DMA_Error_Code DMA Error Code - * @brief DMA Error Code - * @{ - */ -#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ -#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U) /*!< FIFO error */ -#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U) /*!< Direct Mode error */ -#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ -#define HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U) /*!< Parameter error */ -#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort requested with no Xfer ongoing */ -#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */ -/** - * @} - */ - -/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction - * @brief DMA data transfer direction - * @{ - */ -#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ -#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ -#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ -/** - * @} - */ - -/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode - * @brief DMA peripheral incremented mode - * @{ - */ -#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ -#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */ -/** - * @} - */ - -/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode - * @brief DMA memory incremented mode - * @{ - */ -#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ -#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */ -/** - * @} - */ - -/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size - * @brief DMA peripheral data size - * @{ - */ -#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */ -#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ -#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ -/** - * @} - */ - -/** @defgroup DMA_Memory_data_size DMA Memory data size - * @brief DMA memory data size - * @{ - */ -#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */ -#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ -#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ -/** - * @} - */ - -/** @defgroup DMA_mode DMA mode - * @brief DMA mode - * @{ - */ -#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ -#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ -#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ -/** - * @} - */ - -/** @defgroup DMA_Priority_level DMA Priority level - * @brief DMA priority levels - * @{ - */ -#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */ -#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ -#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ -#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ -/** - * @} - */ - -/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode - * @brief DMA FIFO direct mode - * @{ - */ -#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */ -#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ -/** - * @} - */ - -/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level - * @brief DMA FIFO level - * @{ - */ -#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */ -#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ -#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ -#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ -/** - * @} - */ - -/** @defgroup DMA_Memory_burst DMA Memory burst - * @brief DMA memory burst - * @{ - */ -#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U) -#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) -#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) -#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) -/** - * @} - */ - -/** @defgroup DMA_Peripheral_burst DMA Peripheral burst - * @brief DMA peripheral burst - * @{ - */ -#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U) -#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) -#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) -#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) -/** - * @} - */ - -/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions - * @brief DMA interrupts definition - * @{ - */ -#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) -#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) -#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) -#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) -#define DMA_IT_FE ((uint32_t)0x00000080U) -/** - * @} - */ - -/** @defgroup DMA_flag_definitions DMA flag definitions - * @brief DMA flag definitions - * @{ - */ -#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U) -#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U) -#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U) -#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U) -#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U) -#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U) -#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U) -#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U) -#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U) -#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U) -#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U) -#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U) -#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U) -#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U) -#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U) -#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U) -#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U) -#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U) -#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U) -#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @brief Reset DMA handle state - * @param __HANDLE__: specifies the DMA handle. - * @retval None - */ -#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) - -/** - * @brief Return the current DMA Stream FIFO filled level. - * @param __HANDLE__: DMA handle - * @retval The FIFO filling state. - * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full - * and not empty. - * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. - * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. - * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. - * - DMA_FIFOStatus_Empty: when FIFO is empty - * - DMA_FIFOStatus_Full: when FIFO is full - */ -#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) - -/** - * @brief Enable the specified DMA Stream. - * @param __HANDLE__: DMA handle - * @retval None - */ -#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) - -/** - * @brief Disable the specified DMA Stream. - * @param __HANDLE__: DMA handle - * @retval None - */ -#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) - -/* Interrupt & Flag management */ - -/** - * @brief Return the current DMA Stream transfer complete flag. - * @param __HANDLE__: DMA handle - * @retval The specified transfer complete flag index. - */ -#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ - DMA_FLAG_TCIF3_7) - -/** - * @brief Return the current DMA Stream half transfer complete flag. - * @param __HANDLE__: DMA handle - * @retval The specified half transfer complete flag index. - */ -#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ - DMA_FLAG_HTIF3_7) - -/** - * @brief Return the current DMA Stream transfer error flag. - * @param __HANDLE__: DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ - DMA_FLAG_TEIF3_7) - -/** - * @brief Return the current DMA Stream FIFO error flag. - * @param __HANDLE__: DMA handle - * @retval The specified FIFO error flag index. - */ -#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ - DMA_FLAG_FEIF3_7) - -/** - * @brief Return the current DMA Stream direct mode error flag. - * @param __HANDLE__: DMA handle - * @retval The specified direct mode error flag index. - */ -#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ - DMA_FLAG_DMEIF3_7) - -/** - * @brief Get the DMA Stream pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: Get the specified flag. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCIFx: Transfer complete flag. - * @arg DMA_FLAG_HTIFx: Half transfer complete flag. - * @arg DMA_FLAG_TEIFx: Transfer error flag. - * @arg DMA_FLAG_DMEIFx: Direct mode error flag. - * @arg DMA_FLAG_FEIFx: FIFO error flag. - * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. - * @retval The state of FLAG (SET or RESET). - */ -#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ -(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ - ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ - ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) - -/** - * @brief Clear the DMA Stream pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCIFx: Transfer complete flag. - * @arg DMA_FLAG_HTIFx: Half transfer complete flag. - * @arg DMA_FLAG_TEIFx: Transfer error flag. - * @arg DMA_FLAG_DMEIFx: Direct mode error flag. - * @arg DMA_FLAG_FEIFx: FIFO error flag. - * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. - * @retval None - */ -#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ - ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ - ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) - -/** - * @brief Enable the specified DMA Stream interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask. - * @arg DMA_IT_HT: Half transfer complete interrupt mask. - * @arg DMA_IT_TE: Transfer error interrupt mask. - * @arg DMA_IT_FE: FIFO error interrupt mask. - * @arg DMA_IT_DME: Direct mode error interrupt. - * @retval None - */ -#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ -((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) - -/** - * @brief Disable the specified DMA Stream interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask. - * @arg DMA_IT_HT: Half transfer complete interrupt mask. - * @arg DMA_IT_TE: Transfer error interrupt mask. - * @arg DMA_IT_FE: FIFO error interrupt mask. - * @arg DMA_IT_DME: Direct mode error interrupt. - * @retval None - */ -#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ -((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) - -/** - * @brief Check whether the specified DMA Stream interrupt is enabled or not. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask. - * @arg DMA_IT_HT: Half transfer complete interrupt mask. - * @arg DMA_IT_TE: Transfer error interrupt mask. - * @arg DMA_IT_FE: FIFO error interrupt mask. - * @arg DMA_IT_DME: Direct mode error interrupt. - * @retval The state of DMA_IT. - */ -#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ - ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ - ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) - -/** - * @brief Writes the number of data units to be transferred on the DMA Stream. - * @param __HANDLE__: DMA handle - * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) - * Number of data items depends only on the Peripheral data format. - * - * @note If Peripheral data format is Bytes: number of data units is equal - * to total number of bytes to be transferred. - * - * @note If Peripheral data format is Half-Word: number of data units is - * equal to total number of bytes to be transferred / 2. - * - * @note If Peripheral data format is Word: number of data units is equal - * to total number of bytes to be transferred / 4. - * - * @retval The number of remaining data units in the current DMAy Streamx transfer. - */ -#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) - -/** - * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. - * @param __HANDLE__: DMA handle - * - * @retval The number of remaining data units in the current DMA Stream transfer. - */ -#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) - - -/* Include DMA HAL Extension module */ -#include "stm32f7xx_hal_dma_ex.h" - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Functions DMA Exported Functions - * @brief DMA Exported functions - * @{ - */ - -/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * @{ - */ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions - * @brief I/O operation functions - * @{ - */ -HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); -HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); - -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions - * @{ - */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); -/** - * @} - */ -/** - * @} - */ -/* Private Constants -------------------------------------------------------------*/ -/** @defgroup DMA_Private_Constants DMA Private Constants - * @brief DMA private defines and constants - * @{ - */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup DMA_Private_Macros DMA Private Macros - * @brief DMA private macros - * @{ - */ -#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ - ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ - ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) - -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) - -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ - ((STATE) == DMA_PINC_DISABLE)) - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ - ((STATE) == DMA_MINC_DISABLE)) - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ - ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_PDATAALIGN_WORD)) - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ - ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_MDATAALIGN_WORD )) - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ - ((MODE) == DMA_CIRCULAR) || \ - ((MODE) == DMA_PFCTRL)) - -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ - ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ - ((PRIORITY) == DMA_PRIORITY_HIGH) || \ - ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) - -#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ - ((STATE) == DMA_FIFOMODE_ENABLE)) - -#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ - ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ - ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ - ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) - -#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ - ((BURST) == DMA_MBURST_INC4) || \ - ((BURST) == DMA_MBURST_INC8) || \ - ((BURST) == DMA_MBURST_INC16)) - -#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ - ((BURST) == DMA_PBURST_INC4) || \ - ((BURST) == DMA_PBURST_INC8) || \ - ((BURST) == DMA_PBURST_INC16)) -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup DMA_Private_Functions DMA Private Functions - * @brief DMA private functions - * @{ - */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_DMA_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h b/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h deleted file mode 100644 index 84ab78e..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h +++ /dev/null @@ -1,197 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dma_ex.h - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Header file of DMA HAL extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_DMA_EX_H -#define __STM32F7xx_HAL_DMA_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup DMAEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup DMAEx_Exported_Types DMAEx Exported Types - * @brief DMAEx Exported types - * @{ - */ - -/** - * @brief HAL DMA Memory definition - */ -typedef enum -{ - MEMORY0 = 0x00U, /*!< Memory 0 */ - MEMORY1 = 0x01U, /*!< Memory 1 */ - -}HAL_DMA_MemoryTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants DMA Exported Constants - * @brief DMA Exported constants - * @{ - */ - -/** @defgroup DMAEx_Channel_selection DMA Channel selection - * @brief DMAEx channel selection - * @{ - */ -#define DMA_CHANNEL_0 ((uint32_t)0x00000000U) /*!< DMA Channel 0 */ -#define DMA_CHANNEL_1 ((uint32_t)0x02000000U) /*!< DMA Channel 1 */ -#define DMA_CHANNEL_2 ((uint32_t)0x04000000U) /*!< DMA Channel 2 */ -#define DMA_CHANNEL_3 ((uint32_t)0x06000000U) /*!< DMA Channel 3 */ -#define DMA_CHANNEL_4 ((uint32_t)0x08000000U) /*!< DMA Channel 4 */ -#define DMA_CHANNEL_5 ((uint32_t)0x0A000000U) /*!< DMA Channel 5 */ -#define DMA_CHANNEL_6 ((uint32_t)0x0C000000U) /*!< DMA Channel 6 */ -#define DMA_CHANNEL_7 ((uint32_t)0x0E000000U) /*!< DMA Channel 7 */ -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -#define DMA_CHANNEL_8 ((uint32_t)0x10000000U) /*!< DMA Channel 8 */ -#define DMA_CHANNEL_9 ((uint32_t)0x12000000U) /*!< DMA Channel 9 */ -#define DMA_CHANNEL_10 ((uint32_t)0x14000000U) /*!< DMA Channel 10*/ -#define DMA_CHANNEL_11 ((uint32_t)0x16000000U) /*!< DMA Channel 11*/ -#define DMA_CHANNEL_12 ((uint32_t)0x18000000U) /*!< DMA Channel 12*/ -#define DMA_CHANNEL_13 ((uint32_t)0x1A000000U) /*!< DMA Channel 13*/ -#define DMA_CHANNEL_14 ((uint32_t)0x1C000000U) /*!< DMA Channel 14*/ -#define DMA_CHANNEL_15 ((uint32_t)0x1E000000U) /*!< DMA Channel 15*/ -#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions - * @brief DMAEx Exported functions - * @{ - */ - -/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * @{ - */ - -/* IO operation functions *******************************************************/ -HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory); - -/** - * @} - */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup DMAEx_Private_Macros DMA Private Macros - * @brief DMAEx private macros - * @{ - */ -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ - ((CHANNEL) == DMA_CHANNEL_1) || \ - ((CHANNEL) == DMA_CHANNEL_2) || \ - ((CHANNEL) == DMA_CHANNEL_3) || \ - ((CHANNEL) == DMA_CHANNEL_4) || \ - ((CHANNEL) == DMA_CHANNEL_5) || \ - ((CHANNEL) == DMA_CHANNEL_6) || \ - ((CHANNEL) == DMA_CHANNEL_7) || \ - ((CHANNEL) == DMA_CHANNEL_8) || \ - ((CHANNEL) == DMA_CHANNEL_9) || \ - ((CHANNEL) == DMA_CHANNEL_10) || \ - ((CHANNEL) == DMA_CHANNEL_11) || \ - ((CHANNEL) == DMA_CHANNEL_12) || \ - ((CHANNEL) == DMA_CHANNEL_13) || \ - ((CHANNEL) == DMA_CHANNEL_14) || \ - ((CHANNEL) == DMA_CHANNEL_15)) -#else -#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ - ((CHANNEL) == DMA_CHANNEL_1) || \ - ((CHANNEL) == DMA_CHANNEL_2) || \ - ((CHANNEL) == DMA_CHANNEL_3) || \ - ((CHANNEL) == DMA_CHANNEL_4) || \ - ((CHANNEL) == DMA_CHANNEL_5) || \ - ((CHANNEL) == DMA_CHANNEL_6) || \ - ((CHANNEL) == DMA_CHANNEL_7)) -#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup DMAEx_Private_Functions DMAEx Private Functions - * @brief DMAEx Private functions - * @{ - */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_DMA_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h b/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h deleted file mode 100644 index 715920c..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h +++ /dev/null @@ -1,416 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_flash.h - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Header file of FLASH HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_FLASH_H -#define __STM32F7xx_HAL_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Types FLASH Exported Types - * @{ - */ - -/** - * @brief FLASH Procedure structure definition - */ -typedef enum -{ - FLASH_PROC_NONE = 0U, - FLASH_PROC_SECTERASE, - FLASH_PROC_MASSERASE, - FLASH_PROC_PROGRAM -} FLASH_ProcedureTypeDef; - - -/** - * @brief FLASH handle Structure definition - */ -typedef struct -{ - __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ - - __IO uint32_t NbSectorsToErase; /* Internal variable to save the remaining sectors to erase in IT context */ - - __IO uint8_t VoltageForErase; /* Internal variable to provide voltage range selected by user in IT context */ - - __IO uint32_t Sector; /* Internal variable to define the current sector which is erasing */ - - __IO uint32_t Address; /* Internal variable to save address selected for program */ - - HAL_LockTypeDef Lock; /* FLASH locking object */ - - __IO uint32_t ErrorCode; /* FLASH error code */ - -}FLASH_ProcessTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Constants FLASH Exported Constants - * @{ - */ - -/** @defgroup FLASH_Error_Code FLASH Error Code - * @brief FLASH Error Code - * @{ - */ -#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002U) /*!< Programming Sequence error */ -#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004U) /*!< Programming Parallelism error */ -#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008U) /*!< Programming Alignment error */ -#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010U) /*!< Write protection error */ -#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020U) /*!< Operation Error */ -/** - * @} - */ - -/** @defgroup FLASH_Type_Program FLASH Type Program - * @{ - */ -#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00U) /*!< Program byte (8-bit) at a specified address */ -#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U) /*!< Program a half-word (16-bit) at a specified address */ -#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!< Program a word (32-bit) at a specified address */ -#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03U) /*!< Program a double word (64-bit) at a specified address */ -/** - * @} - */ - -/** @defgroup FLASH_Flag_definition FLASH Flag definition - * @brief Flag definition - * @{ - */ -#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH operation Error flag */ -#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */ -#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */ -#define FLASH_FLAG_ERSERR FLASH_SR_ERSERR /*!< FLASH Erasing Sequence error flag */ -#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ -/** - * @} - */ - -/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition - * @brief FLASH Interrupt definition - * @{ - */ -#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ -#define FLASH_IT_ERR ((uint32_t)0x02000000U) /*!< Error Interrupt source */ -/** - * @} - */ - -/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism - * @{ - */ -#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U) -#define FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0) -#define FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1) -#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE) -#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU) -/** - * @} - */ - -/** @defgroup FLASH_Keys FLASH Keys - * @{ - */ -#define FLASH_KEY1 ((uint32_t)0x45670123U) -#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU) -#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU) -#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU) -/** - * @} - */ - -/** @defgroup FLASH_Sectors FLASH Sectors - * @{ - */ -#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ -#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ -#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ -#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */ -#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */ -#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */ -#define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */ -#define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Macros FLASH Exported Macros - * @{ - */ -/** - * @brief Set the FLASH Latency. - * @param __LATENCY__: FLASH Latency - * The value of this parameter depend on device used within the same series - * @retval none - */ -#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \ - MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__)) - -/** - * @brief Get the FLASH Latency. - * @retval FLASH Latency - * The value of this parameter depend on device used within the same series - */ -#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) - -/** - * @brief Enable the FLASH prefetch buffer. - * @retval none - */ -#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN) - -/** - * @brief Disable the FLASH prefetch buffer. - * @retval none - */ -#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN)) - -/** - * @brief Enable the FLASH Adaptive Real-Time memory accelerator. - * @note The ART accelerator is available only for flash access on ITCM interface. - * @retval none - */ -#define __HAL_FLASH_ART_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN) - -/** - * @brief Disable the FLASH Adaptive Real-Time memory accelerator. - * @retval none - */ -#define __HAL_FLASH_ART_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN) - -/** - * @brief Resets the FLASH Adaptive Real-Time memory accelerator. - * @note This function must be used only when the Adaptive Real-Time memory accelerator - * is disabled. - * @retval None - */ -#define __HAL_FLASH_ART_RESET() (FLASH->ACR |= FLASH_ACR_ARTRST) - -/** - * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__ : FLASH interrupt - * This parameter can be any combination of the following values: - * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_ERR: Error Interrupt - * @retval none - */ -#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) - -/** - * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__ : FLASH interrupt - * This parameter can be any combination of the following values: - * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_ERR: Error Interrupt - * @retval none - */ -#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__)) - -/** - * @brief Get the specified FLASH flag status. - * @param __FLAG__: specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_EOP : FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR : FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag - * @arg FLASH_FLAG_BSY : FLASH Busy flag - * @retval The new state of __FLAG__ (SET or RESET). - */ -#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__))) - -/** - * @brief Clear the specified FLASH flag. - * @param __FLAG__: specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_EOP : FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR : FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag - * @retval none - */ -#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__)) -/** - * @} - */ - -/* Include FLASH HAL Extension module */ -#include "stm32f7xx_hal_flash_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup FLASH_Exported_Functions - * @{ - */ -/** @addtogroup FLASH_Exported_Functions_Group1 - * @{ - */ -/* Program operation functions ***********************************************/ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); -/* FLASH IRQ handler method */ -void HAL_FLASH_IRQHandler(void); -/* Callbacks in non blocking modes */ -void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); -void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); -/** - * @} - */ - -/** @addtogroup FLASH_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions **********************************************/ -HAL_StatusTypeDef HAL_FLASH_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_Lock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); -/* Option bytes control */ -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); -/** - * @} - */ - -/** @addtogroup FLASH_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State functions ************************************************/ -uint32_t HAL_FLASH_GetError(void); -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup FLASH_Private_Variables FLASH Private Variables - * @{ - */ - -/** - * @} - */ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup FLASH_Private_Constants FLASH Private Constants - * @{ - */ - -/** - * @brief OPTCR register byte 1 (Bits[15:8]) base address - */ -#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup FLASH_Private_Macros FLASH Private Macros - * @{ - */ - -/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters - * @{ - */ -#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \ - ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ - ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ - ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup FLASH_Private_Functions FLASH Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_FLASH_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h b/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h deleted file mode 100644 index e52727c..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h +++ /dev/null @@ -1,608 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_flash_ex.h - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Header file of FLASH HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_FLASH_EX_H -#define __STM32F7xx_HAL_FLASH_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASHEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Types FLASH Exported Types - * @{ - */ - -/** - * @brief FLASH Erase structure definition - */ -typedef struct -{ - uint32_t TypeErase; /*!< Mass erase or sector Erase. - This parameter can be a value of @ref FLASHEx_Type_Erase */ - -#if defined (FLASH_OPTCR_nDBANK) - uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. - This parameter must be a value of @ref FLASHEx_Banks */ -#endif /* FLASH_OPTCR_nDBANK */ - - uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled - This parameter must be a value of @ref FLASHEx_Sectors */ - - uint32_t NbSectors; /*!< Number of sectors to be erased. - This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ - - uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism - This parameter must be a value of @ref FLASHEx_Voltage_Range */ - -} FLASH_EraseInitTypeDef; - -/** - * @brief FLASH Option Bytes Program structure definition - */ -typedef struct -{ - uint32_t OptionType; /*!< Option byte to be configured. - This parameter can be a value of @ref FLASHEx_Option_Type */ - - uint32_t WRPState; /*!< Write protection activation or deactivation. - This parameter can be a value of @ref FLASHEx_WRP_State */ - - uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. - The value of this parameter depend on device used within the same series */ - - uint32_t RDPLevel; /*!< Set the read protection level. - This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ - - uint32_t BORLevel; /*!< Set the BOR Level. - This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ - - uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY / - IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / nDBANK / nDBOOT. - nDBANK / nDBOOT are only available for STM32F76xxx/STM32F77xxx devices */ - - uint32_t BootAddr0; /*!< Boot base address when Boot pin = 0. - This parameter can be a value of @ref FLASHEx_Boot_Address */ - - uint32_t BootAddr1; /*!< Boot base address when Boot pin = 1. - This parameter can be a value of @ref FLASHEx_Boot_Address */ - -} FLASH_OBProgramInitTypeDef; - -/** - * @} - */ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants - * @{ - */ - -/** @defgroup FLASHEx_Type_Erase FLASH Type Erase - * @{ - */ -#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) /*!< Sectors erase only */ -#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) /*!< Flash Mass erase activation */ -/** - * @} - */ - -/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range - * @{ - */ -#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) /*!< Device operating range: 1.8V to 2.1V */ -#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U) /*!< Device operating range: 2.1V to 2.7V */ -#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U) /*!< Device operating range: 2.7V to 3.6V */ -#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03U) /*!< Device operating range: 2.7V to 3.6V + External Vpp */ -/** - * @} - */ - -/** @defgroup FLASHEx_WRP_State FLASH WRP State - * @{ - */ -#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired bank 1 sectors */ -#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired bank 1 sectors */ -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Type FLASH Option Type - * @{ - */ -#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */ -#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */ -#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */ -#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */ -#define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10U) /*!< Boot 0 Address configuration */ -#define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20U) /*!< Boot 1 Address configuration */ -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection - * @{ - */ -#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU) -#define OB_RDP_LEVEL_1 ((uint8_t)0x55U) -#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2 - it s no more possible to go back to level 1 or 0 */ -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog - * @{ - */ -#define OB_WWDG_SW ((uint32_t)0x10U) /*!< Software WWDG selected */ -#define OB_WWDG_HW ((uint32_t)0x00U) /*!< Hardware WWDG selected */ -/** - * @} - */ - - -/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog - * @{ - */ -#define OB_IWDG_SW ((uint32_t)0x20U) /*!< Software IWDG selected */ -#define OB_IWDG_HW ((uint32_t)0x00U) /*!< Hardware IWDG selected */ -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP - * @{ - */ -#define OB_STOP_NO_RST ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STOP */ -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY - * @{ - */ -#define OB_STDBY_NO_RST ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY */ -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP - * @{ - */ -#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */ -#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000U) /*!< IWDG counter active in STOP mode */ -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY - * @{ - */ -#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */ -#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000U) /*!< IWDG counter active in STANDBY mode */ -/** - * @} - */ - -/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level - * @{ - */ -#define OB_BOR_LEVEL3 ((uint32_t)0x00U) /*!< Supply voltage ranges from 2.70 to 3.60 V */ -#define OB_BOR_LEVEL2 ((uint32_t)0x04U) /*!< Supply voltage ranges from 2.40 to 2.70 V */ -#define OB_BOR_LEVEL1 ((uint32_t)0x08U) /*!< Supply voltage ranges from 2.10 to 2.40 V */ -#define OB_BOR_OFF ((uint32_t)0x0CU) /*!< Supply voltage ranges from 1.62 to 2.10 V */ -/** - * @} - */ - -#if defined (FLASH_OPTCR_nDBOOT) -/** @defgroup FLASHEx_Option_Bytes_nDBOOT FLASH Option Bytes nDBOOT - * @{ - */ -#define OB_DUAL_BOOT_DISABLE ((uint32_t)0x10000000U) /* !< Dual Boot disable. Boot according to boot address option */ -#define OB_DUAL_BOOT_ENABLE ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash - (Dual bank Boot mode), or RAM if Boot address option in RAM */ -/** - * @} - */ -#endif /* FLASH_OPTCR_nDBOOT */ - -#if defined (FLASH_OPTCR_nDBANK) -/** @defgroup FLASHEx_Option_Bytes_nDBank FLASH Single Bank or Dual Bank - * @{ - */ -#define OB_NDBANK_SINGLE_BANK ((uint32_t)0x20000000U) /*!< NDBANK bit is set : Single Bank mode */ -#define OB_NDBANK_DUAL_BANK ((uint32_t)0x00000000U) /*!< NDBANK bit is reset : Dual Bank mode */ -/** - * @} - */ -#endif /* FLASH_OPTCR_nDBANK */ - -/** @defgroup FLASHEx_Boot_Address FLASH Boot Address - * @{ - */ -#define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000U) /*!< Boot from ITCM RAM (0x00000000) */ -#define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040U) /*!< Boot from System memory bootloader (0x00100000) */ -#define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080U) /*!< Boot from Flash on ITCM interface (0x00200000) */ -#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U) /*!< Boot from Flash on AXIM interface (0x08000000) */ -#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U) /*!< Boot from DTCM RAM (0x20000000) */ -#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U) /*!< Boot from SRAM1 (0x20010000) */ -#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U) /*!< Boot from SRAM2 (0x2004C000) */ -/** - * @} - */ - -/** @defgroup FLASH_Latency FLASH Latency - * @{ - */ -#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */ -#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */ -#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */ -#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */ -#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */ -#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */ -#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */ -#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */ -#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycles */ -#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycles */ -#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */ -#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */ -#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */ -#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */ -#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */ -#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */ -/** - * @} - */ - -#if defined (FLASH_OPTCR_nDBANK) -/** @defgroup FLASHEx_Banks FLASH Banks - * @{ - */ -#define FLASH_BANK_1 ((uint32_t)0x01U) /*!< Bank 1 */ -#define FLASH_BANK_2 ((uint32_t)0x02U) /*!< Bank 2 */ -#define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */ -/** - * @} - */ -#endif /* FLASH_OPTCR_nDBANK */ - -/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit - * @{ - */ -#if defined (FLASH_OPTCR_nDBANK) -#define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits */ -#else -#define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER bit */ -#endif /* FLASH_OPTCR_nDBANK */ -/** - * @} - */ - -/** @defgroup FLASHEx_Sectors FLASH Sectors - * @{ - */ -#if (FLASH_SECTOR_TOTAL == 24) -#define FLASH_SECTOR_8 ((uint32_t)8U) /*!< Sector Number 8 */ -#define FLASH_SECTOR_9 ((uint32_t)9U) /*!< Sector Number 9 */ -#define FLASH_SECTOR_10 ((uint32_t)10U) /*!< Sector Number 10 */ -#define FLASH_SECTOR_11 ((uint32_t)11U) /*!< Sector Number 11 */ -#define FLASH_SECTOR_12 ((uint32_t)12U) /*!< Sector Number 12 */ -#define FLASH_SECTOR_13 ((uint32_t)13U) /*!< Sector Number 13 */ -#define FLASH_SECTOR_14 ((uint32_t)14U) /*!< Sector Number 14 */ -#define FLASH_SECTOR_15 ((uint32_t)15U) /*!< Sector Number 15 */ -#define FLASH_SECTOR_16 ((uint32_t)16U) /*!< Sector Number 16 */ -#define FLASH_SECTOR_17 ((uint32_t)17U) /*!< Sector Number 17 */ -#define FLASH_SECTOR_18 ((uint32_t)18U) /*!< Sector Number 18 */ -#define FLASH_SECTOR_19 ((uint32_t)19U) /*!< Sector Number 19 */ -#define FLASH_SECTOR_20 ((uint32_t)20U) /*!< Sector Number 20 */ -#define FLASH_SECTOR_21 ((uint32_t)21U) /*!< Sector Number 21 */ -#define FLASH_SECTOR_22 ((uint32_t)22U) /*!< Sector Number 22 */ -#define FLASH_SECTOR_23 ((uint32_t)23U) /*!< Sector Number 23 */ -#endif /* FLASH_SECTOR_TOTAL == 24 */ -/** - * @} - */ - -#if (FLASH_SECTOR_TOTAL == 24) -/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection - * @note For Single Bank mode, use OB_WRP_SECTOR_x defines: In fact, in FLASH_OPTCR register, - * nWRP[11:0] bits contain the value of the write-protection option bytes for sectors 0 to 11. - * For Dual Bank mode, use OB_WRP_DB_SECTOR_x defines: In fact, in FLASH_OPTCR register, - * nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and - * a second one dedicated for bank 2 (nWRP[i] activates Write protection on sector 2*i and 2*i+1). - * This behavior is applicable only for STM32F76xxx / STM32F77xxx devices. - * @{ - */ -/* Single Bank Sectors */ -#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Single Bank Sector0 */ -#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Single Bank Sector1 */ -#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Single Bank Sector2 */ -#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Single Bank Sector3 */ -#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Single Bank Sector4 */ -#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Single Bank Sector5 */ -#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Single Bank Sector6 */ -#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Single Bank Sector7 */ -#define OB_WRP_SECTOR_8 ((uint32_t)0x01000000U) /*!< Write protection of Single Bank Sector8 */ -#define OB_WRP_SECTOR_9 ((uint32_t)0x02000000U) /*!< Write protection of Single Bank Sector9 */ -#define OB_WRP_SECTOR_10 ((uint32_t)0x04000000U) /*!< Write protection of Single Bank Sector10 */ -#define OB_WRP_SECTOR_11 ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11 */ -#define OB_WRP_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Single Bank Flash */ - -/* Dual Bank Sectors */ -#define OB_WRP_DB_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector0 */ -#define OB_WRP_DB_SECTOR_1 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector1 */ -#define OB_WRP_DB_SECTOR_2 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector2 */ -#define OB_WRP_DB_SECTOR_3 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector3 */ -#define OB_WRP_DB_SECTOR_4 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector4 */ -#define OB_WRP_DB_SECTOR_5 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector5 */ -#define OB_WRP_DB_SECTOR_6 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector6 */ -#define OB_WRP_DB_SECTOR_7 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector7 */ -#define OB_WRP_DB_SECTOR_8 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector8 */ -#define OB_WRP_DB_SECTOR_9 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector9 */ -#define OB_WRP_DB_SECTOR_10 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector10 */ -#define OB_WRP_DB_SECTOR_11 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11 */ -#define OB_WRP_DB_SECTOR_12 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector12 */ -#define OB_WRP_DB_SECTOR_13 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector13 */ -#define OB_WRP_DB_SECTOR_14 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector14 */ -#define OB_WRP_DB_SECTOR_15 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector15 */ -#define OB_WRP_DB_SECTOR_16 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector16 */ -#define OB_WRP_DB_SECTOR_17 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector17 */ -#define OB_WRP_DB_SECTOR_18 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector18 */ -#define OB_WRP_DB_SECTOR_19 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector19 */ -#define OB_WRP_DB_SECTOR_20 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector20 */ -#define OB_WRP_DB_SECTOR_21 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector21 */ -#define OB_WRP_DB_SECTOR_22 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector22 */ -#define OB_WRP_DB_SECTOR_23 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector23 */ -#define OB_WRP_DB_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Dual Bank Flash */ -/** - * @} - */ -#endif /* FLASH_SECTOR_TOTAL == 24 */ - -#if (FLASH_SECTOR_TOTAL == 8) -/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection - * @{ - */ -#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */ -#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */ -#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */ -#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */ -#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Sector4 */ -#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Sector5 */ -#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Sector6 */ -#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Sector7 */ -#define OB_WRP_SECTOR_All ((uint32_t)0x00FF0000U) /*!< Write protection of all Sectors */ -/** - * @} - */ -#endif /* FLASH_SECTOR_TOTAL == 8 */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Macros FLASH Exported Macros - * @{ - */ -/** - * @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1) - * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14]. - * @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB) - * @retval The FLASH Boot Base Adress - */ -#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14) - /** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup FLASHEx_Exported_Functions - * @{ - */ - -/** @addtogroup FLASHEx_Exported_Functions_Group1 - * @{ - */ -/* Extension Program operation functions *************************************/ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError); -HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); -HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); -void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); - -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup FLASHEx_Private_Macros FLASH Private Macros - * @{ - */ - -/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters - * @{ - */ - -#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \ - ((VALUE) == FLASH_TYPEERASE_MASSERASE)) - -#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \ - ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \ - ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \ - ((RANGE) == FLASH_VOLTAGE_RANGE_4)) - -#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \ - ((VALUE) == OB_WRPSTATE_ENABLE)) - -#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ - OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1))) - -#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013) - -#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ - ((LEVEL) == OB_RDP_LEVEL_1) ||\ - ((LEVEL) == OB_RDP_LEVEL_2)) - -#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW)) - -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) - -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) - -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) - -#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE)) - -#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE)) - -#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ - ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) - -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ - ((LATENCY) == FLASH_LATENCY_1) || \ - ((LATENCY) == FLASH_LATENCY_2) || \ - ((LATENCY) == FLASH_LATENCY_3) || \ - ((LATENCY) == FLASH_LATENCY_4) || \ - ((LATENCY) == FLASH_LATENCY_5) || \ - ((LATENCY) == FLASH_LATENCY_6) || \ - ((LATENCY) == FLASH_LATENCY_7) || \ - ((LATENCY) == FLASH_LATENCY_8) || \ - ((LATENCY) == FLASH_LATENCY_9) || \ - ((LATENCY) == FLASH_LATENCY_10) || \ - ((LATENCY) == FLASH_LATENCY_11) || \ - ((LATENCY) == FLASH_LATENCY_12) || \ - ((LATENCY) == FLASH_LATENCY_13) || \ - ((LATENCY) == FLASH_LATENCY_14) || \ - ((LATENCY) == FLASH_LATENCY_15)) - -#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) - -#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) - -#if (FLASH_SECTOR_TOTAL == 8) -#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ - ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ - ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ - ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7)) - -#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xFF00FFFF) == 0x00000000U) && ((SECTOR) != 0x00000000U)) -#endif /* FLASH_SECTOR_TOTAL == 8 */ - -#if (FLASH_SECTOR_TOTAL == 24) -#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ - ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ - ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ - ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\ - ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\ - ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\ - ((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\ - ((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\ - ((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\ - ((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\ - ((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\ - ((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23)) - -#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) -#endif /* FLASH_SECTOR_TOTAL == 24 */ - -#if defined (FLASH_OPTCR_nDBANK) -#define IS_OB_NDBANK(VALUE) (((VALUE) == OB_NDBANK_SINGLE_BANK) || \ - ((VALUE) == OB_NDBANK_DUAL_BANK)) - -#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ - ((BANK) == FLASH_BANK_2) || \ - ((BANK) == FLASH_BANK_BOTH)) -#endif /* FLASH_OPTCR_nDBANK */ - -#if defined (FLASH_OPTCR_nDBOOT) -#define IS_OB_NDBOOT(VALUE) (((VALUE) == OB_DUAL_BOOT_DISABLE) || \ - ((VALUE) == OB_DUAL_BOOT_ENABLE)) -#endif /* FLASH_OPTCR_nDBOOT */ - -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup FLASHEx_Private_Functions FLASH Private Functions - * @{ - */ -void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_FLASH_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h b/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h deleted file mode 100644 index 3a9779b..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h +++ /dev/null @@ -1,327 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_gpio.h - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Header file of GPIO HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_GPIO_H -#define __STM32F7xx_HAL_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Types GPIO Exported Types - * @{ - */ - -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIO_mode_define */ - - uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. - This parameter can be a value of @ref GPIO_pull_define */ - - uint32_t Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIO_speed_define */ - - uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. - This parameter can be a value of @ref GPIO_Alternate_function_selection */ -}GPIO_InitTypeDef; - -/** - * @brief GPIO Bit SET and Bit RESET enumeration - */ -typedef enum -{ - GPIO_PIN_RESET = 0, - GPIO_PIN_SET -}GPIO_PinState; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Constants GPIO Exported Constants - * @{ - */ - -/** @defgroup GPIO_pins_define GPIO pins define - * @{ - */ -#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */ -#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */ -#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */ -#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */ -#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */ -#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */ -#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */ -#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */ -#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */ -#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */ -#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */ -#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */ -#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */ -#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */ -#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */ -#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */ -#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */ - -#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */ -/** - * @} - */ - -/** @defgroup GPIO_mode_define GPIO mode define - * @brief GPIO Configuration Mode - * Elements values convention: 0xX0yz00YZ - * - X : GPIO mode or EXTI Mode - * - y : External IT or Event trigger detection - * - z : IO configuration on External IT or Event - * - Y : Output type (Push Pull or Open Drain) - * - Z : IO Direction mode (Input, Output, Alternate or Analog) - * @{ - */ -#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) /*!< Alternate Function Open Drain Mode */ - -#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog Mode */ - -#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ - -#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000U) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000U) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */ -/** - * @} - */ - -/** @defgroup GPIO_speed_define GPIO speed define - * @brief GPIO Output Maximum frequency - * @{ - */ -#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Low speed */ -#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< Medium speed */ -#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< Fast speed */ -#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< High speed */ -/** - * @} - */ - - /** @defgroup GPIO_pull_define GPIO pull define - * @brief GPIO Pull-Up or Pull-Down Activation - * @{ - */ -#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */ -#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */ -#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Macros GPIO Exported Macros - * @{ - */ - -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param __EXTI_LINE__: specifies the EXTI line flag to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - -/** - * @brief Clears the EXTI's line pending flags. - * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) - -/** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param __EXTI_LINE__: specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - -/** - * @brief Clears the EXTI's line pending bits. - * @param __EXTI_LINE__: specifies the EXTI lines to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) - -/** - * @brief Generates a Software interrupt on selected EXTI line. - * @param __EXTI_LINE__: specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) -/** - * @} - */ - -/* Include GPIO HAL Extension module */ -#include "stm32f7xx_hal_gpio_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup GPIO_Exported_Functions - * @{ - */ - -/** @addtogroup GPIO_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); -/** - * @} - */ - -/** @addtogroup GPIO_Exported_Functions_Group2 - * @{ - */ -/* IO operation functions *****************************************************/ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); -void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); - -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup GPIO_Private_Constants GPIO Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup GPIO_Private_Macros GPIO Private Macros - * @{ - */ -#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) -#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00) -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ - ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ - ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ - ((MODE) == GPIO_MODE_AF_PP) ||\ - ((MODE) == GPIO_MODE_AF_OD) ||\ - ((MODE) == GPIO_MODE_IT_RISING) ||\ - ((MODE) == GPIO_MODE_IT_FALLING) ||\ - ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ - ((MODE) == GPIO_MODE_EVT_RISING) ||\ - ((MODE) == GPIO_MODE_EVT_FALLING) ||\ - ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ - ((MODE) == GPIO_MODE_ANALOG)) -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \ - ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH)) -#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ - ((PULL) == GPIO_PULLDOWN)) -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup GPIO_Private_Functions GPIO Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_GPIO_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h b/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h deleted file mode 100644 index 401c4dd..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h +++ /dev/null @@ -1,511 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_gpio_ex.h - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Header file of GPIO HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_GPIO_EX_H -#define __STM32F7xx_HAL_GPIO_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup GPIOEx GPIOEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants - * @{ - */ - -/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection - * @{ - */ - -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -#define GPIO_AF1_UART5 ((uint8_t)0x01U) /* UART5 Alternate Function mapping */ -#define GPIO_AF1_I2C4 ((uint8_t)0x01U) /* I2C4 Alternate Function mapping */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */ -#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */ -#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */ -#define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF3_CEC ((uint8_t)0x03U) /* CEC Alternate Function mapping */ -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -#define GPIO_AF3_DFSDM1 ((uint8_t)0x03U) /* DFSDM1 Alternate Function mapping */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */ -#define GPIO_AF4_I2C4 ((uint8_t)0x04U) /* I2C4 Alternate Function mapping */ -#define GPIO_AF4_CEC ((uint8_t)0x04U) /* CEC Alternate Function mapping */ -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */ -#define GPIO_AF5_SPI5 ((uint8_t)0x05U) /* SPI5 Alternate Function mapping */ -#define GPIO_AF5_SPI6 ((uint8_t)0x05U) /* SPI6 Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF6_SAI1 ((uint8_t)0x06U) /* SAI1 Alternate Function mapping */ -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -#define GPIO_AF6_UART4 ((uint8_t)0x06U) /* UART4 Alternate Function mapping */ -#define GPIO_AF6_DFSDM1 ((uint8_t)0x06U) /* DFSDM1 Alternate Function mapping */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ -#define GPIO_AF7_UART5 ((uint8_t)0x07U) /* UART5 Alternate Function mapping */ -#define GPIO_AF7_SPDIFRX ((uint8_t)0x07U) /* SPDIF-RX Alternate Function mapping */ -#define GPIO_AF7_SPI2 ((uint8_t)0x07U) /* SPI2 Alternate Function mapping */ -#define GPIO_AF7_SPI3 ((uint8_t)0x07U) /* SPI3 Alternate Function mapping */ -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -#define GPIO_AF7_SPI6 ((uint8_t)0x07U) /* SPI6 Alternate Function mapping */ -#define GPIO_AF7_DFSDM1 ((uint8_t)0x07U) /* DFSDM1 Alternate Function mapping */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */ -#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */ -#define GPIO_AF8_UART7 ((uint8_t)0x08U) /* UART7 Alternate Function mapping */ -#define GPIO_AF8_UART8 ((uint8_t)0x08U) /* UART8 Alternate Function mapping */ -#define GPIO_AF8_SPDIFRX ((uint8_t)0x08U) /* SPIDIF-RX Alternate Function mapping */ -#define GPIO_AF8_SAI2 ((uint8_t)0x08U) /* SAI2 Alternate Function mapping */ -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -#define GPIO_AF8_SPI6 ((uint8_t)0x08U) /* SPI6 Alternate Function mapping */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_CAN2 ((uint8_t)0x09U) /* CAN2 Alternate Function mapping */ -#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */ -#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */ -#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */ -#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */ -#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -#define GPIO_AF9_LTDC ((uint8_t)0x09U) /* LCD-TFT Alternate Function mapping */ -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -#define GPIO_AF9_FMC ((uint8_t)0x09U) /* FMC Alternate Function mapping */ -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -/** - * @brief AF 10 selection - */ -#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */ -#define GPIO_AF10_QUADSPI ((uint8_t)0xAU) /* QUADSPI Alternate Function mapping */ -#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */ -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -#define GPIO_AF10_DFSDM1 ((uint8_t)0x0AU) /* DFSDM1 Alternate Function mapping */ -#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @brief AF 11 selection - */ -#define GPIO_AF11_ETH ((uint8_t)0x0BU) /* ETHERNET Alternate Function mapping */ -#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define GPIO_AF11_CAN3 ((uint8_t)0x0BU) /* CAN3 Alternate Function mapping */ -#define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping */ -#define GPIO_AF11_I2C4 ((uint8_t)0x0BU) /* I2C4 Alternate Function mapping */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */ -#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */ -#define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */ -#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define GPIO_AF12_MDIOS ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */ -#define GPIO_AF12_UART7 ((uint8_t)0xCU) /* UART7 Alternate Function mapping */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF13_DCMI ((uint8_t)0x0DU) /* DCMI Alternate Function mapping */ -#if defined (STM32F769xx) || defined (STM32F779xx) -#define GPIO_AF13_DSI ((uint8_t)0x0DU) /* DSI Alternate Function mapping */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -#define GPIO_AF13_LTDC ((uint8_t)0x0DU) /* LTDC Alternate Function mapping */ - -/** - * @brief AF 14 selection - */ -#define GPIO_AF14_LTDC ((uint8_t)0x0EU) /* LCD-TFT Alternate Function mapping */ -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ - - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros - * @{ - */ -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions - * @{ - */ -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup GPIOEx_Private_Constants GPIO Private Constants - * @{ - */ - -/** - * @brief GPIO pin available on the platform - */ -/* Defines the available pins per GPIOs */ -#define GPIOA_PIN_AVAILABLE GPIO_PIN_All -#define GPIOB_PIN_AVAILABLE GPIO_PIN_All -#define GPIOC_PIN_AVAILABLE GPIO_PIN_All -#define GPIOD_PIN_AVAILABLE GPIO_PIN_All -#define GPIOE_PIN_AVAILABLE GPIO_PIN_All -#define GPIOF_PIN_AVAILABLE GPIO_PIN_All -#define GPIOG_PIN_AVAILABLE GPIO_PIN_All -#define GPIOI_PIN_AVAILABLE GPIO_PIN_All -#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All -#define GPIOH_PIN_AVAILABLE GPIO_PIN_All -#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \ - GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup GPIOEx_Private_Macros GPIO Private Macros - * @{ - */ -/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index - * @{ - */ -#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOF))? 5U :\ - ((__GPIOx__) == (GPIOG))? 6U :\ - ((__GPIOx__) == (GPIOH))? 7U :\ - ((__GPIOx__) == (GPIOI))? 8U :\ - ((__GPIOx__) == (GPIOJ))? 9U : 10U) -/** - * @} - */ - -#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \ - ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOF) && (((__PIN__) & (GPIOF_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOF_PIN_AVAILABLE)) == (GPIOF_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOG) && (((__PIN__) & (GPIOG_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOG_PIN_AVAILABLE)) == (GPIOG_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOI) && (((__PIN__) & (GPIOI_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOI_PIN_AVAILABLE)) == (GPIOI_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE)))) -/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function - * @{ - */ -#if defined(STM32F756xx) || defined(STM32F746xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ - ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ - ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ - ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ - ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ - ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ - ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ - ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ - ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ - ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ - ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ - ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ - ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ - ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ - ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ - ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ - ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ - ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ - ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ - ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ - ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ - ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ - ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ - ((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \ - ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ - ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ - ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ - ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \ - ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF14_LTDC)) -#elif defined(STM32F745xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ - ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ - ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ - ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ - ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ - ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ - ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ - ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ - ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ - ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ - ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ - ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ - ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ - ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ - ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ - ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ - ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ - ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ - ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ - ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ - ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ - ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ - ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ - ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF10_OTG_FS) || \ - ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ - ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ - ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ - ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT)) -#elif defined(STM32F767xx) || defined(STM32F777xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ - ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ - ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ - ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ - ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ - ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ - ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ - ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ - ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ - ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ - ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ - ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ - ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ - ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ - ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ - ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ - ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ - ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ - ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ - ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ - ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ - ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ - ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ - ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF9_LTDC) || \ - ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ - ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ - ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ - ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ - ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ - ((AF) == GPIO_AF14_LTDC)) -#elif defined(STM32F769xx) || defined(STM32F779xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ - ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ - ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ - ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ - ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ - ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ - ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ - ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ - ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ - ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ - ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ - ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ - ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ - ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ - ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ - ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ - ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ - ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ - ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ - ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ - ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ - ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ - ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ - ((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \ - ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ - ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ - ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ - ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ - ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ - ((AF) == GPIO_AF14_LTDC) || ((AF) == GPIO_AF13_DSI)) -#elif defined(STM32F765xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ - ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ - ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ - ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ - ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ - ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ - ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ - ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ - ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ - ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ - ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ - ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ - ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ - ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ - ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ - ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ - ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ - ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ - ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ - ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ - ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ - ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ - ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ - ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ - ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ - ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ - ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ - ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ - ((AF) == GPIO_AF10_OTG_FS)) -#endif /* STM32F756xx || STM32F746xx */ -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup GPIOEx_Private_Functions GPIO Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_GPIO_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h b/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h deleted file mode 100644 index cb5c0b9..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h +++ /dev/null @@ -1,711 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_i2c.h - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Header file of I2C HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_I2C_H -#define __STM32F7xx_HAL_I2C_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup I2C_Exported_Types I2C Exported Types - * @{ - */ - -/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition - * @brief I2C Configuration Structure definition - * @{ - */ -typedef struct -{ - uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. - This parameter calculated by referring to I2C initialization - section in Reference manual */ - - uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. - This parameter can be a value of @ref I2C_ADDRESSING_MODE */ - - uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ - - uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ - - uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ - - uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ - - uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ - -}I2C_InitTypeDef; - -/** - * @} - */ - -/** @defgroup HAL_state_structure_definition HAL state structure definition - * @brief HAL State structure definition - * @note HAL I2C State value coding follow below described bitmap : - * b7-b6 Error information - * 00 : No Error - * 01 : Abort (Abort user request on going) - * 10 : Timeout - * 11 : Error - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called) - * b4 (not used) - * x : Should be set to 0 - * b3 - * 0 : Ready or Busy (No Listen mode ongoing) - * 1 : Listen (IP in Address Listen Mode) - * b2 Intrinsic process state - * 0 : Ready - * 1 : Busy (IP busy with some configuration or internal operations) - * b1 Rx state - * 0 : Ready (no Rx operation ongoing) - * 1 : Busy (Rx operation ongoing) - * b0 Tx state - * 0 : Ready (no Tx operation ongoing) - * 1 : Busy (Tx operation ongoing) - * @{ - */ - -typedef enum -{ - HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ - HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ - HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ - HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ - HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ - HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ - HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission - process is ongoing */ - HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception - process is ongoing */ - HAL_I2C_STATE_ABORT = 0x60, /*!< Abort user request ongoing */ - HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ - -}HAL_I2C_StateTypeDef; - -/** - * @} - */ - -/** @defgroup HAL_mode_structure_definition HAL mode structure definition - * @brief HAL Mode structure definition - * @note HAL I2C Mode value coding follow below described bitmap : - * b7 (not used) - * x : Should be set to 0 - * b6 - * 0 : None - * 1 : Memory (HAL I2C communication is in Memory Mode) - * b5 - * 0 : None - * 1 : Slave (HAL I2C communication is in Slave Mode) - * b4 - * 0 : None - * 1 : Master (HAL I2C communication is in Master Mode) - * b3-b2-b1-b0 (not used) - * xxxx : Should be set to 0000 - * @{ - */ -typedef enum -{ - HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ - HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ - HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ - HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ - -}HAL_I2C_ModeTypeDef; - -/** - * @} - */ - -/** @defgroup I2C_Error_Code_definition I2C Error Code definition - * @brief I2C Error Code definition - * @{ - */ -#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001U) /*!< BERR error */ -#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002U) /*!< ARLO error */ -#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004U) /*!< ACKF error */ -#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008U) /*!< OVR error */ -#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ -#define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040U) /*!< Size Management error */ -#define HAL_I2C_ERROR_ABORT ((uint32_t)0x00000080U) /*!< Abort user request */ -/** - * @} - */ - -/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition - * @brief I2C handle Structure definition - * @{ - */ -typedef struct __I2C_HandleTypeDef -{ - I2C_TypeDef *Instance; /*!< I2C registers base address */ - - I2C_InitTypeDef Init; /*!< I2C communication parameters */ - - uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ - - uint16_t XferSize; /*!< I2C transfer size */ - - __IO uint16_t XferCount; /*!< I2C transfer counter */ - - __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can - be a value of @ref I2C_XFEROPTIONS */ - - __IO uint32_t PreviousState; /*!< I2C communication Previous state */ - - HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ - - DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ - - HAL_LockTypeDef Lock; /*!< I2C locking object */ - - __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ - - __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ - - __IO uint32_t ErrorCode; /*!< I2C Error code */ - - __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ -}I2C_HandleTypeDef; -/** - * @} - */ - -/** - * @} - */ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Constants I2C Exported Constants - * @{ - */ - -/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options - * @{ - */ -#define I2C_NO_OPTION_FRAME ((uint32_t)0xFFFF0000U) -#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) -#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) -#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) -#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) -/** - * @} - */ - -/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode - * @{ - */ -#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001U) -#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002U) -/** - * @} - */ - -/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode - * @{ - */ -#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U) -#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN -/** - * @} - */ - -/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks - * @{ - */ -#define I2C_OA2_NOMASK ((uint8_t)0x00U) -#define I2C_OA2_MASK01 ((uint8_t)0x01U) -#define I2C_OA2_MASK02 ((uint8_t)0x02U) -#define I2C_OA2_MASK03 ((uint8_t)0x03U) -#define I2C_OA2_MASK04 ((uint8_t)0x04U) -#define I2C_OA2_MASK05 ((uint8_t)0x05U) -#define I2C_OA2_MASK06 ((uint8_t)0x06U) -#define I2C_OA2_MASK07 ((uint8_t)0x07U) -/** - * @} - */ - -/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode - * @{ - */ -#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U) -#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN -/** - * @} - */ - -/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode - * @{ - */ -#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U) -#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH -/** - * @} - */ - -/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size - * @{ - */ -#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U) -#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002U) -/** - * @} - */ - -/** @defgroup I2C_XferDirection I2C Transfer Direction - * @{ - */ -#define I2C_DIRECTION_TRANSMIT ((uint32_t)0x00000000U) -#define I2C_DIRECTION_RECEIVE ((uint32_t)0x00000001U) -/** - * @} - */ - -/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode - * @{ - */ -#define I2C_RELOAD_MODE I2C_CR2_RELOAD -#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND -#define I2C_SOFTEND_MODE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode - * @{ - */ -#define I2C_NO_STARTSTOP ((uint32_t)0x00000000U) -#define I2C_GENERATE_STOP I2C_CR2_STOP -#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) -#define I2C_GENERATE_START_WRITE I2C_CR2_START -/** - * @} - */ - -/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition - * @brief I2C Interrupt definition - * Elements values convention: 0xXXXXXXXX - * - XXXXXXXX : Interrupt control mask - * @{ - */ -#define I2C_IT_ERRI I2C_CR1_ERRIE -#define I2C_IT_TCI I2C_CR1_TCIE -#define I2C_IT_STOPI I2C_CR1_STOPIE -#define I2C_IT_NACKI I2C_CR1_NACKIE -#define I2C_IT_ADDRI I2C_CR1_ADDRIE -#define I2C_IT_RXI I2C_CR1_RXIE -#define I2C_IT_TXI I2C_CR1_TXIE -/** - * @} - */ - -/** @defgroup I2C_Flag_definition I2C Flag definition - * @{ - */ -#define I2C_FLAG_TXE I2C_ISR_TXE -#define I2C_FLAG_TXIS I2C_ISR_TXIS -#define I2C_FLAG_RXNE I2C_ISR_RXNE -#define I2C_FLAG_ADDR I2C_ISR_ADDR -#define I2C_FLAG_AF I2C_ISR_NACKF -#define I2C_FLAG_STOPF I2C_ISR_STOPF -#define I2C_FLAG_TC I2C_ISR_TC -#define I2C_FLAG_TCR I2C_ISR_TCR -#define I2C_FLAG_BERR I2C_ISR_BERR -#define I2C_FLAG_ARLO I2C_ISR_ARLO -#define I2C_FLAG_OVR I2C_ISR_OVR -#define I2C_FLAG_PECERR I2C_ISR_PECERR -#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT -#define I2C_FLAG_ALERT I2C_ISR_ALERT -#define I2C_FLAG_BUSY I2C_ISR_BUSY -#define I2C_FLAG_DIR I2C_ISR_DIR -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Macros I2C Exported Macros - * @{ - */ - -/** @brief Reset I2C handle state. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) - -/** @brief Enable the specified I2C interrupt. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__ specifies the interrupt source to enable. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval None - */ -#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) - -/** @brief Disable the specified I2C interrupt. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__ specifies the interrupt source to disable. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval None - */ -#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) - -/** @brief Check whether the specified I2C interrupt source is enabled or not. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__ specifies the I2C interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Check whether the specified I2C flag is set or not. - * @param __HANDLE__ specifies the I2C Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref I2C_FLAG_TXE Transmit data register empty - * @arg @ref I2C_FLAG_TXIS Transmit interrupt status - * @arg @ref I2C_FLAG_RXNE Receive data register not empty - * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) - * @arg @ref I2C_FLAG_AF Acknowledge failure received flag - * @arg @ref I2C_FLAG_STOPF STOP detection flag - * @arg @ref I2C_FLAG_TC Transfer complete (master mode) - * @arg @ref I2C_FLAG_TCR Transfer complete reload - * @arg @ref I2C_FLAG_BERR Bus error - * @arg @ref I2C_FLAG_ARLO Arbitration lost - * @arg @ref I2C_FLAG_OVR Overrun/Underrun - * @arg @ref I2C_FLAG_PECERR PEC error in reception - * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag - * @arg @ref I2C_FLAG_ALERT SMBus alert - * @arg @ref I2C_FLAG_BUSY Bus busy - * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) - * - * @retval The new state of __FLAG__ (SET or RESET). - */ -#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) - -/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. - * @param __HANDLE__ specifies the I2C Handle. - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg @ref I2C_FLAG_TXE Transmit data register empty - * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) - * @arg @ref I2C_FLAG_AF Acknowledge failure received flag - * @arg @ref I2C_FLAG_STOPF STOP detection flag - * @arg @ref I2C_FLAG_BERR Bus error - * @arg @ref I2C_FLAG_ARLO Arbitration lost - * @arg @ref I2C_FLAG_OVR Overrun/Underrun - * @arg @ref I2C_FLAG_PECERR PEC error in reception - * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag - * @arg @ref I2C_FLAG_ALERT SMBus alert - * - * @retval None - */ -#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ - : ((__HANDLE__)->Instance->ICR = (__FLAG__))) - -/** @brief Enable the specified I2C peripheral. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) - -/** @brief Disable the specified I2C peripheral. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) - -/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. - * @param __HANDLE__: specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) -/** - * @} - */ - -/* Include I2C HAL Extended module */ -#include "stm32f7xx_hal_i2c_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup I2C_Exported_Functions - * @{ - */ - -/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -/* Initialization and de-initialization functions******************************/ -HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); -void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); -/** - * @} - */ - -/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ -/* IO operation functions ****************************************************/ - /******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); - - /******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); - -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); - - /******* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -/** - * @} - */ - -/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ -/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); -void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); -void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); -/** - * @} - */ - -/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions - * @{ - */ -/* Peripheral State, Mode and Error functions *********************************/ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); - -/** - * @} - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2C_Private_Constants I2C Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2C_Private_Macro I2C Private Macros - * @{ - */ - -#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ - ((MODE) == I2C_ADDRESSINGMODE_10BIT)) - -#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) - -#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ - ((MASK) == I2C_OA2_MASK01) || \ - ((MASK) == I2C_OA2_MASK02) || \ - ((MASK) == I2C_OA2_MASK03) || \ - ((MASK) == I2C_OA2_MASK04) || \ - ((MASK) == I2C_OA2_MASK05) || \ - ((MASK) == I2C_OA2_MASK06) || \ - ((MASK) == I2C_OA2_MASK07)) - -#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ - ((CALL) == I2C_GENERALCALL_ENABLE)) - -#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ - ((STRETCH) == I2C_NOSTRETCH_ENABLE)) - -#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ - ((SIZE) == I2C_MEMADD_SIZE_16BIT)) - -#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ - ((MODE) == I2C_AUTOEND_MODE) || \ - ((MODE) == I2C_SOFTEND_MODE)) - -#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ - ((REQUEST) == I2C_GENERATE_START_READ) || \ - ((REQUEST) == I2C_GENERATE_START_WRITE) || \ - ((REQUEST) == I2C_NO_STARTSTOP)) - -#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ - ((REQUEST) == I2C_NEXT_FRAME) || \ - ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ - ((REQUEST) == I2C_LAST_FRAME)) - -#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) - -#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16) -#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16) -#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) -#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1) -#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2) - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) - -#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8))) -#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) - -#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) -/** - * @} - */ - -/* Private Functions ---------------------------------------------------------*/ -/** @defgroup I2C_Private_Functions I2C Private Functions - * @{ - */ -/* Private functions are defined in stm32f7xx_hal_i2c.c file */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32F7xx_HAL_I2C_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h b/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h deleted file mode 100644 index 2cfa26e..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h +++ /dev/null @@ -1,188 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_i2c_ex.h - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Header file of I2C HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_I2C_EX_H -#define __STM32F7xx_HAL_I2C_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup I2CEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup I2CEx_Exported_Constants I2CEx Exported Constants - * @{ - */ - -/** @defgroup I2CEx_Analog_Filter I2CEx Analog Filter - * @{ - */ -#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U) -#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF -/** - * @} - */ - -/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus - * @{ - */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - -#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP -#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP -#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP -#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP - -#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP -#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP -#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP -#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP - -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Peripheral Control methods ************************************************/ -HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); -HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); -void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2C_Private_Constants I2C Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2C_Private_Macro I2C Private Macros - * @{ - */ -#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ - ((FILTER) == I2C_ANALOGFILTER_DISABLE)) - -#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) - -#if defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) && defined(SYSCFG_PMC_I2C4_FMP) -#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4)) -#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) -#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3)) -#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) -#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2)) -#elif defined(SYSCFG_PMC_I2C1_FMP) -#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1)) -#endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */ -/** - * @} - */ -/** - * @} - */ - -/* Private Functions ---------------------------------------------------------*/ -/** @defgroup I2C_Private_Functions I2C Private Functions - * @{ - */ -/* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_I2C_EX_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h b/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h deleted file mode 100644 index 8a6c5f3..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h +++ /dev/null @@ -1,422 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_pwr.h - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Header file of PWR HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_PWR_H -#define __STM32F7xx_HAL_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Types PWR Exported Types - * @{ - */ - -/** - * @brief PWR PVD configuration structure definition - */ -typedef struct -{ - uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. - This parameter can be a value of @ref PWR_PVD_detection_level */ - - uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. - This parameter can be a value of @ref PWR_PVD_Mode */ -}PWR_PVDTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup PWR_Exported_Constants PWR Exported Constants - * @{ - */ - -/** @defgroup PWR_PVD_detection_level PWR PVD detection level - * @{ - */ -#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 -#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 -#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 -#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 -#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 -#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 -#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 -#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7/* External input analog voltage - (Compare internally to VREFINT) */ - -/** - * @} - */ - -/** @defgroup PWR_PVD_Mode PWR PVD Mode - * @{ - */ -#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< basic mode is used */ -#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ -/** - * @} - */ - -/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode - * @{ - */ -#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U) -#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS -/** - * @} - */ - -/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry - * @{ - */ -#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) -#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) -/** - * @} - */ - -/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry - * @{ - */ -#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) -#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) -/** - * @} - */ - -/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale - * @{ - */ -#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS -#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 -#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR1_VOS_0 -/** - * @} - */ - -/** @defgroup PWR_Flag PWR Flag - * @{ - */ -#define PWR_FLAG_WU PWR_CSR1_WUIF -#define PWR_FLAG_SB PWR_CSR1_SBF -#define PWR_FLAG_PVDO PWR_CSR1_PVDO -#define PWR_FLAG_BRR PWR_CSR1_BRR -#define PWR_FLAG_VOSRDY PWR_CSR1_VOSRDY -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup PWR_Exported_Macro PWR Exported Macro - * @{ - */ - -/** @brief macros configure the main internal regulator output voltage. - * @param __REGULATOR__: specifies the regulator output voltage to achieve - * a tradeoff between performance and power consumption when the device does - * not operate at the maximum frequency (refer to the datasheets for more details). - * This parameter can be one of the following values: - * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode - * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode - * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode - * @retval None - */ -#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ - __IO uint32_t tmpreg; \ - MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ - UNUSED(tmpreg); \ - } while(0) - -/** @brief Check PWR flag is set or not. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event - * was received on the internal wakeup line in standby mode (RTC alarm (Alarm A or Alarm B), - * RTC Tamper event, RTC TimeStamp event or RTC Wakeup)). - * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was - * resumed from StandBy mode. - * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled - * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode - * For this reason, this bit is equal to 0 after Standby or reset - * until the PVDE bit is set. - * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset - * when the device wakes up from Standby mode or by a system reset - * or power reset. - * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage - * scaling output selection is ready. - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__)) - -/** @brief Clear the PWR's pending flags. - * @param __FLAG__: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_SB: StandBy flag - */ -#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR1 |= (__FLAG__) << 2) - -/** - * @brief Enable the PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) - -/** - * @brief Disable the PVD EXTI Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) - -/** - * @brief Enable event on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) - -/** - * @brief Disable event on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) - -/** - * @brief Enable the PVD Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) - -/** - * @brief Disable the PVD Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) - -/** - * @brief Enable the PVD Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) - - -/** - * @brief Disable the PVD Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) - - -/** - * @brief PVD EXTI line configuration: set rising & falling edge trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); - -/** - * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); - -/** - * @brief checks whether the specified PVD Exti interrupt flag is set or not. - * @retval EXTI PVD Line Status. - */ -#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) - -/** - * @brief Clear the PVD Exti flag. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) - -/** - * @brief Generates a Software interrupt on PVD EXTI line. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) - -/** - * @} - */ - -/* Include PWR HAL Extension module */ -#include "stm32f7xx_hal_pwr_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -void HAL_PWR_DeInit(void); -void HAL_PWR_EnableBkUpAccess(void); -void HAL_PWR_DisableBkUpAccess(void); -/** - * @} - */ - -/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @{ - */ -/* Peripheral Control functions **********************************************/ -/* PVD configuration */ -void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); -void HAL_PWR_EnablePVD(void); -void HAL_PWR_DisablePVD(void); - -/* WakeUp pins configuration */ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); - -/* Low Power modes entry */ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); -void HAL_PWR_EnterSTANDBYMode(void); - -/* Power PVD IRQ Handler */ -void HAL_PWR_PVD_IRQHandler(void); -void HAL_PWR_PVDCallback(void); - -/* Cortex System Control functions *******************************************/ -void HAL_PWR_EnableSleepOnExit(void); -void HAL_PWR_DisableSleepOnExit(void); -void HAL_PWR_EnableSEVOnPend(void); -void HAL_PWR_DisableSEVOnPend(void); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup PWR_Private_Constants PWR Private Constants - * @{ - */ - -/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line - * @{ - */ -#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_IM16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ -/** - * @} - */ - -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup PWR_Private_Macros PWR Private Macros - * @{ - */ - -/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters - * @{ - */ -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ - ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ - ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ - ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) -#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ - ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ - ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ - ((MODE) == PWR_PVD_MODE_NORMAL)) -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ - ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) -#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) -#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ - ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ - ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32F7xx_HAL_PWR_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h b/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h deleted file mode 100644 index 7246003..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h +++ /dev/null @@ -1,280 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_pwr_ex.h - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Header file of PWR HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_PWR_EX_H -#define __STM32F7xx_HAL_PWR_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup PWREx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup PWREx_Exported_Constants PWREx Exported Constants - * @{ - */ -/** @defgroup PWREx_WakeUp_Pins PWREx Wake Up Pins - * @{ - */ -#define PWR_WAKEUP_PIN1 PWR_CSR2_EWUP1 -#define PWR_WAKEUP_PIN2 PWR_CSR2_EWUP2 -#define PWR_WAKEUP_PIN3 PWR_CSR2_EWUP3 -#define PWR_WAKEUP_PIN4 PWR_CSR2_EWUP4 -#define PWR_WAKEUP_PIN5 PWR_CSR2_EWUP5 -#define PWR_WAKEUP_PIN6 PWR_CSR2_EWUP6 -#define PWR_WAKEUP_PIN1_HIGH PWR_CSR2_EWUP1 -#define PWR_WAKEUP_PIN2_HIGH PWR_CSR2_EWUP2 -#define PWR_WAKEUP_PIN3_HIGH PWR_CSR2_EWUP3 -#define PWR_WAKEUP_PIN4_HIGH PWR_CSR2_EWUP4 -#define PWR_WAKEUP_PIN5_HIGH PWR_CSR2_EWUP5 -#define PWR_WAKEUP_PIN6_HIGH PWR_CSR2_EWUP6 -#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR2_WUPP1<<6) | PWR_CSR2_EWUP1) -#define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR2_WUPP2<<6) | PWR_CSR2_EWUP2) -#define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR2_WUPP3<<6) | PWR_CSR2_EWUP3) -#define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR2_WUPP4<<6) | PWR_CSR2_EWUP4) -#define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR2_WUPP5<<6) | PWR_CSR2_EWUP5) -#define PWR_WAKEUP_PIN6_LOW (uint32_t)((PWR_CR2_WUPP6<<6) | PWR_CSR2_EWUP6) - -/** - * @} - */ - -/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode - * @{ - */ -#define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR1_MRUDS -#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR1_LPDS | PWR_CR1_LPUDS)) -/** - * @} - */ - -/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag - * @{ - */ -#define PWR_FLAG_ODRDY PWR_CSR1_ODRDY -#define PWR_FLAG_ODSWRDY PWR_CSR1_ODSWRDY -#define PWR_FLAG_UDRDY PWR_CSR1_UDRDY -/** - * @} - */ - -/** @defgroup PWREx_Wakeup_Pins_Flag PWREx Wake Up Pin Flags - * @{ - */ -#define PWR_WAKEUP_PIN_FLAG1 PWR_CSR2_WUPF1 -#define PWR_WAKEUP_PIN_FLAG2 PWR_CSR2_WUPF2 -#define PWR_WAKEUP_PIN_FLAG3 PWR_CSR2_WUPF3 -#define PWR_WAKEUP_PIN_FLAG4 PWR_CSR2_WUPF4 -#define PWR_WAKEUP_PIN_FLAG5 PWR_CSR2_WUPF5 -#define PWR_WAKEUP_PIN_FLAG6 PWR_CSR2_WUPF6 -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup PWREx_Exported_Macro PWREx Exported Macro - * @{ - */ -/** @brief Macros to enable or disable the Over drive mode. - */ -#define __HAL_PWR_OVERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN) -#define __HAL_PWR_OVERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN)) - -/** @brief Macros to enable or disable the Over drive switching. - */ -#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN) -#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN)) - -/** @brief Macros to enable or disable the Under drive mode. - * @note This mode is enabled only with STOP low power mode. - * In this mode, the 1.2V domain is preserved in reduced leakage mode. This - * mode is only available when the main regulator or the low power regulator - * is in low voltage mode. - * @note If the Under-drive mode was enabled, it is automatically disabled after - * exiting Stop mode. - * When the voltage regulator operates in Under-drive mode, an additional - * startup delay is induced when waking up from Stop mode. - */ -#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_UDEN) -#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN)) - -/** @brief Check PWR flag is set or not. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode - * is ready - * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode - * switching is ready - * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode - * is enabled in Stop mode - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__)) - -/** @brief Clear the Under-Drive Ready flag. - */ -#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= PWR_FLAG_UDRDY) - -/** @brief Check Wake Up flag is set or not. - * @param __WUFLAG__: specifies the Wake Up flag to check. - * This parameter can be one of the following values: - * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0 - * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2 - * @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1 - * @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13 - * @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8 - * @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11 - */ -#define __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__)) - -/** @brief Clear the WakeUp pins flags. - * @param __WUFLAG__: specifies the Wake Up pin flag to clear. - * This parameter can be one of the following values: - * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0 - * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2 - * @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1 - * @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13 - * @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8 - * @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11 - */ -#define __HAL_PWR_CLEAR_WAKEUP_FLAG(__WUFLAG__) (PWR->CR2 |= (__WUFLAG__)) -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions - * @{ - */ - -/** @addtogroup PWREx_Exported_Functions_Group1 - * @{ - */ -uint32_t HAL_PWREx_GetVoltageRange(void); -HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); - -void HAL_PWREx_EnableFlashPowerDown(void); -void HAL_PWREx_DisableFlashPowerDown(void); -HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void); -HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); - -void HAL_PWREx_EnableMainRegulatorLowVoltage(void); -void HAL_PWREx_DisableMainRegulatorLowVoltage(void); -void HAL_PWREx_EnableLowRegulatorLowVoltage(void); -void HAL_PWREx_DisableLowRegulatorLowVoltage(void); - -HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void); -HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void); -HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry); - -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup PWREx_Private_Macros PWREx Private Macros - * @{ - */ - -/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters - * @{ - */ -#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \ - ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON)) -#define IS_PWR_WAKEUP_PIN(__PIN__) (((__PIN__) == PWR_WAKEUP_PIN1) || \ - ((__PIN__) == PWR_WAKEUP_PIN2) || \ - ((__PIN__) == PWR_WAKEUP_PIN3) || \ - ((__PIN__) == PWR_WAKEUP_PIN4) || \ - ((__PIN__) == PWR_WAKEUP_PIN5) || \ - ((__PIN__) == PWR_WAKEUP_PIN6) || \ - ((__PIN__) == PWR_WAKEUP_PIN1_HIGH) || \ - ((__PIN__) == PWR_WAKEUP_PIN2_HIGH) || \ - ((__PIN__) == PWR_WAKEUP_PIN3_HIGH) || \ - ((__PIN__) == PWR_WAKEUP_PIN4_HIGH) || \ - ((__PIN__) == PWR_WAKEUP_PIN5_HIGH) || \ - ((__PIN__) == PWR_WAKEUP_PIN6_HIGH) || \ - ((__PIN__) == PWR_WAKEUP_PIN1_LOW) || \ - ((__PIN__) == PWR_WAKEUP_PIN2_LOW) || \ - ((__PIN__) == PWR_WAKEUP_PIN3_LOW) || \ - ((__PIN__) == PWR_WAKEUP_PIN4_LOW) || \ - ((__PIN__) == PWR_WAKEUP_PIN5_LOW) || \ - ((__PIN__) == PWR_WAKEUP_PIN6_LOW)) -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32F7xx_HAL_PWR_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h b/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h deleted file mode 100644 index dd2a68c..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h +++ /dev/null @@ -1,1306 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_rcc.h - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Header file of RCC HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_RCC_H -#define __STM32F7xx_HAL_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/* Include RCC HAL Extended module */ -/* (include on top of file since RCC structures are defined in extended file) */ -#include "stm32f7xx_hal_rcc_ex.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Types RCC Exported Types - * @{ - */ - -/** - * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition - */ -typedef struct -{ - uint32_t OscillatorType; /*!< The oscillators to be configured. - This parameter can be a value of @ref RCC_Oscillator_Type */ - - uint32_t HSEState; /*!< The new state of the HSE. - This parameter can be a value of @ref RCC_HSE_Config */ - - uint32_t LSEState; /*!< The new state of the LSE. - This parameter can be a value of @ref RCC_LSE_Config */ - - uint32_t HSIState; /*!< The new state of the HSI. - This parameter can be a value of @ref RCC_HSI_Config */ - - uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ - - uint32_t LSIState; /*!< The new state of the LSI. - This parameter can be a value of @ref RCC_LSI_Config */ - - RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ - -}RCC_OscInitTypeDef; - -/** - * @brief RCC System, AHB and APB busses clock configuration structure definition - */ -typedef struct -{ - uint32_t ClockType; /*!< The clock to be configured. - This parameter can be a value of @ref RCC_System_Clock_Type */ - - uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. - This parameter can be a value of @ref RCC_System_Clock_Source */ - - uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). - This parameter can be a value of @ref RCC_AHB_Clock_Source */ - - uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ - - uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ - -}RCC_ClkInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCC_Exported_Constants RCC Exported Constants - * @{ - */ - -/** @defgroup RCC_Oscillator_Type Oscillator Type - * @{ - */ -#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) -#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) -#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) -#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) -#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) -/** - * @} - */ - -/** @defgroup RCC_HSE_Config RCC HSE Config - * @{ - */ -#define RCC_HSE_OFF ((uint32_t)0x00000000U) -#define RCC_HSE_ON RCC_CR_HSEON -#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) -/** - * @} - */ - -/** @defgroup RCC_LSE_Config RCC LSE Config - * @{ - */ -#define RCC_LSE_OFF ((uint32_t)0x00000000U) -#define RCC_LSE_ON RCC_BDCR_LSEON -#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) -/** - * @} - */ - -/** @defgroup RCC_HSI_Config RCC HSI Config - * @{ - */ -#define RCC_HSI_OFF ((uint32_t)0x00000000U) -#define RCC_HSI_ON RCC_CR_HSION - -#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */ -/** - * @} - */ - -/** @defgroup RCC_LSI_Config RCC LSI Config - * @{ - */ -#define RCC_LSI_OFF ((uint32_t)0x00000000U) -#define RCC_LSI_ON RCC_CSR_LSION -/** - * @} - */ - -/** @defgroup RCC_PLL_Config RCC PLL Config - * @{ - */ -#define RCC_PLL_NONE ((uint32_t)0x00000000U) -#define RCC_PLL_OFF ((uint32_t)0x00000001U) -#define RCC_PLL_ON ((uint32_t)0x00000002U) -/** - * @} - */ - -/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider - * @{ - */ -#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) -#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) -#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) -#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) -/** - * @} - */ - -/** @defgroup RCC_PLL_Clock_Source PLL Clock Source - * @{ - */ -#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI -#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Type RCC System Clock Type - * @{ - */ -#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) -#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) -#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) -#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source RCC System Clock Source - * @{ - */ -#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI -#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE -#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL -/** - * @} - */ - - -/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status - * @{ - */ -#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source - * @{ - */ -#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 -#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 -#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 -#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 -#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 -#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 -#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 -#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 -#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 -/** - * @} - */ - -/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source - * @{ - */ -#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 -#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 -#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 -#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 -#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source - * @{ - */ -#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U) -#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U) -#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U) -#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U) -#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U) -#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U) -#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U) -#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U) -#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U) -#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U) -#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U) -#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U) -#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U) -#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U) -#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U) -#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U) -#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U) -#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U) -#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U) -#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U) -#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U) -/** - * @} - */ - - - -/** @defgroup RCC_MCO_Index RCC MCO Index - * @{ - */ -#define RCC_MCO1 ((uint32_t)0x00000000U) -#define RCC_MCO2 ((uint32_t)0x00000001U) -/** - * @} - */ - -/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source - * @{ - */ -#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U) -#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 -#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 -#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1 -/** - * @} - */ - -/** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source - * @{ - */ -#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U) -#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 -#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 -#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 -/** - * @} - */ - -/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler - * @{ - */ -#define RCC_MCODIV_1 ((uint32_t)0x00000000U) -#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2 -#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) -#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) -#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE -/** - * @} - */ - -/** @defgroup RCC_Interrupt RCC Interrupt - * @{ - */ -#define RCC_IT_LSIRDY ((uint8_t)0x01U) -#define RCC_IT_LSERDY ((uint8_t)0x02U) -#define RCC_IT_HSIRDY ((uint8_t)0x04U) -#define RCC_IT_HSERDY ((uint8_t)0x08U) -#define RCC_IT_PLLRDY ((uint8_t)0x10U) -#define RCC_IT_PLLI2SRDY ((uint8_t)0x20U) -#define RCC_IT_PLLSAIRDY ((uint8_t)0x40U) -#define RCC_IT_CSS ((uint8_t)0x80U) -/** - * @} - */ - -/** @defgroup RCC_Flag RCC Flags - * Elements values convention: 0XXYYYYYb - * - YYYYY : Flag position in the register - * - 0XX : Register index - * - 01: CR register - * - 10: BDCR register - * - 11: CSR register - * @{ - */ -/* Flags in the CR register */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x21U) -#define RCC_FLAG_HSERDY ((uint8_t)0x31U) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39U) -#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU) -#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3CU) - -/* Flags in the BDCR register */ -#define RCC_FLAG_LSERDY ((uint8_t)0x41U) - -/* Flags in the CSR register */ -#define RCC_FLAG_LSIRDY ((uint8_t)0x61U) -#define RCC_FLAG_BORRST ((uint8_t)0x79U) -#define RCC_FLAG_PINRST ((uint8_t)0x7AU) -#define RCC_FLAG_PORRST ((uint8_t)0x7BU) -#define RCC_FLAG_SFTRST ((uint8_t)0x7CU) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7DU) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7EU) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7FU) -/** - * @} - */ - -/** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations - * @{ - */ -#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) -#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 -#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 -#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RCC_Exported_Macros RCC Exported Macros - * @{ - */ - -/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable - * @brief Enable or disable the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_CRC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) -#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN)) - -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable - * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_PWR_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) -#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) -/** - * @} - */ - -/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable - * @brief Enable or disable the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) - -/** - * @} - */ - -/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) -#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET) - -#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) -#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET) -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) -#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) - -#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) -#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) -/** - * @} - */ - -/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status - * @brief EGet the enable or disable status of the APB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) -#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release - * @brief Force or release AHB peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) -#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) - -#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) -#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) -#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) -/** - * @} - */ - -/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset - * @brief Force or release APB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) -#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) - -#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) -#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) -#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) -/** - * @} - */ - -/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset - * @brief Force or release APB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) - -#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) -#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) - -/** - * @} - */ - -/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) -#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) - -#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) -#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN)) - -/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) -#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) - -#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) -#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) - -/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) -#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) - -/** - * @} - */ - -/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status - * @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET) -#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET) - -#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET) -#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status - * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET) -#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET) - -#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET) -#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status - * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET) -#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCC_HSI_Configuration HSI Configuration - * @{ - */ - -/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). - * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * It is used (enabled by hardware) as system clock source after startup - * from Reset, wakeup from STOP and STANDBY mode, or in case of failure - * of the HSE used directly or indirectly as system clock (if the Clock - * Security System CSS is enabled). - * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. - * @note After enabling the HSI, the application software should wait on HSIRDY - * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - */ -#define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION)) -#define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION)) - -/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value. - * (default is RCC_HSICALIBRATION_DEFAULT). - */ -#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\ - RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM))) -/** - * @} - */ - -/** @defgroup RCC_LSI_Configuration LSI Configuration - * @{ - */ - -/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - * @note LSI can not be disabled if the IWDG is running. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - */ -#define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION)) -#define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION)) -/** - * @} - */ - -/** @defgroup RCC_HSE_Configuration HSE Configuration - * @{ - */ -/** - * @brief Macro to configure the External High Speed oscillator (HSE). - * @note Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this macro. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. - * @note HSE state can not be changed if it is used directly or through the - * PLL as system clock. In this case, you have to select another source - * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @note This function reset the CSSON bit, so if the clock security system(CSS) - * was previously enabled you have to enable it again after calling this - * function. - * @param __STATE__: specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg RCC_HSE_ON: turn ON the HSE oscillator. - * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. - */ -#define __HAL_RCC_HSE_CONFIG(__STATE__) \ - do { \ - if ((__STATE__) == RCC_HSE_ON) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else if ((__STATE__) == RCC_HSE_OFF) \ - { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ - } \ - else if ((__STATE__) == RCC_HSE_BYPASS) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ - } \ - } while(0) -/** - * @} - */ - -/** @defgroup RCC_LSE_Configuration LSE Configuration - * @{ - */ - -/** - * @brief Macro to configure the External Low Speed oscillator (LSE). - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. - * User should request a transition to LSE Off first and then LSE On or LSE Bypass. - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * HAL_PWR_EnableBkUpAccess() function before to configure the LSE - * (to be done once after reset). - * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application - * software should wait on LSERDY flag to be set indicating that LSE clock - * is stable and can be used to clock the RTC. - * @param __STATE__: specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after - * 6 LSE oscillator clock cycles. - * @arg RCC_LSE_ON: turn ON the LSE oscillator. - * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. - */ -#define __HAL_RCC_LSE_CONFIG(__STATE__) \ - do { \ - if((__STATE__) == RCC_LSE_ON) \ - { \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - } \ - else if((__STATE__) == RCC_LSE_OFF) \ - { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - } \ - else if((__STATE__) == RCC_LSE_BYPASS) \ - { \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - } \ - } while(0) -/** - * @} - */ - -/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration - * @{ - */ - -/** @brief Macros to enable or disable the RTC clock. - * @note These macros must be used only after the RTC clock source was selected. - */ -#define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN)) -#define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN)) - -/** @brief Macros to configure the RTC clock (RTCCLK). - * @note As the RTC clock configuration bits are in the Backup domain and write - * access is denied to this domain after reset, you have to enable write - * access using the Power Backup Access macro before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the - * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by - * a Power On Reset (POR). - * @param __RTCCLKSource__: specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. - * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. - * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected - * as RTC clock, where x:[2,31] - * @note If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wakeup source. - * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. - * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as - * RTC clock source). - */ -#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) - -#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ - RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \ - } while (0) - -/** @brief Macros to force or release the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_CSR register. - * @note The BKPSRAM is not affected by this reset. - */ -#define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST)) -#define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST)) -/** - * @} - */ - -/** @defgroup RCC_PLL_Configuration PLL Configuration - * @{ - */ - -/** @brief Macros to enable or disable the main PLL. - * @note After enabling the main PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The main PLL can not be disabled if it is used as system clock source - * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) -#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) - -/** @brief Macro to configure the PLL clock source. - * @note This function must be used only when the main PLL is disabled. - * @param __PLLSOURCE__: specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - * - */ -#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) - -/** @brief Macro to configure the PLL multiplication factor. - * @note This function must be used only when the main PLL is disabled. - * @param __PLLM__: specifies the division factor for PLL VCO input clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 63. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLL jitter. - * - */ -#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) -/** - * @} - */ - -/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration - * @{ - */ - -/** @brief Macro to configure the I2S clock source (I2SCLK). - * @note This function must be called before enabling the I2S APB clock. - * @param __SOURCE__: specifies the I2S clock source. - * This parameter can be one of the following values: - * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. - * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin - * used as I2S clock source. - */ -#define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \ - RCC->CFGR |= (__SOURCE__); \ - }while(0) - -/** @brief Macros to enable or disable the PLLI2S. - * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON)) -#define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON)) -/** - * @} - */ - -/** @defgroup RCC_Get_Clock_source Get Clock source - * @{ - */ -/** - * @brief Macro to configure the system clock source. - * @param __RCC_SYSCLKSOURCE__: specifies the system clock source. - * This parameter can be one of the following values: - * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. - * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. - * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. - */ -#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) - -/** @brief Macro to get the clock source used as system clock. - * @retval The clock source used as system clock. The returned value can be one - * of the following: - * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. - * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. - * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. - */ -#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) - -/** - * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability. - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * HAL_PWR_EnableBkUpAccess() function before to configure the LSE - * (to be done once after reset). - * @param __RCC_LSEDRIVE__: specifies the new state of the LSE drive capability. - * This parameter can be one of the following values: - * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability. - * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability. - * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability. - * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability. - * @retval None - */ -#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \ - (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) - -/** @brief Macro to get the oscillator used as PLL clock source. - * @retval The oscillator used as PLL clock source. The returned value can be one - * of the following: - * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. - * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. - */ -#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) -/** - * @} - */ - -/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config - * @{ - */ - -/** @brief Macro to configure the MCO1 clock. - * @param __MCOCLKSOURCE__ specifies the MCO clock source. - * This parameter can be one of the following values: - * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source - * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source - * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source - * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source - * @param __MCODIV__ specifies the MCO clock prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCODIV_1: no division applied to MCOx clock - * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock - * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock - * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock - * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock - */ - -#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) - -/** @brief Macro to configure the MCO2 clock. - * @param __MCOCLKSOURCE__ specifies the MCO clock source. - * This parameter can be one of the following values: - * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source - * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source - * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source - * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source - * @param __MCODIV__ specifies the MCO clock prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCODIV_1: no division applied to MCOx clock - * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock - * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock - * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock - * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock - */ - -#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3))); -/** - * @} - */ - -/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management - * @brief macros to manage the specified RCC Flags and interrupts. - * @{ - */ - -/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable - * the selected interrupts). - * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt. - * @arg RCC_IT_LSERDY: LSE ready interrupt. - * @arg RCC_IT_HSIRDY: HSI ready interrupt. - * @arg RCC_IT_HSERDY: HSE ready interrupt. - * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. - */ -#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) - -/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable - * the selected interrupts). - * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt. - * @arg RCC_IT_LSERDY: LSE ready interrupt. - * @arg RCC_IT_HSIRDY: HSI ready interrupt. - * @arg RCC_IT_HSERDY: HSE ready interrupt. - * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. - */ -#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) - -/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] - * bits to clear the selected interrupt pending bits. - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt. - * @arg RCC_IT_LSERDY: LSE ready interrupt. - * @arg RCC_IT_HSIRDY: HSI ready interrupt. - * @arg RCC_IT_HSERDY: HSE ready interrupt. - * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. - * @arg RCC_IT_CSS: Clock Security System interrupt - */ -#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) - -/** @brief Check the RCC's interrupt has occurred or not. - * @param __INTERRUPT__: specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt. - * @arg RCC_IT_LSERDY: LSE ready interrupt. - * @arg RCC_IT_HSIRDY: HSI ready interrupt. - * @arg RCC_IT_HSERDY: HSE ready interrupt. - * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval The new state of __INTERRUPT__ (TRUE or FALSE). - */ -#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) - -/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, - * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. - */ -#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) - -/** @brief Check RCC flag is set or not. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. - * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. - * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready. - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. - * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset. - * @arg RCC_FLAG_PINRST: Pin reset. - * @arg RCC_FLAG_PORRST: POR/PDR reset. - * @arg RCC_FLAG_SFTRST: Software reset. - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. - * @arg RCC_FLAG_LPWRRST: Low Power reset. - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define RCC_FLAG_MASK ((uint8_t)0x1F) -#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0) - -/** - * @} - */ - -/** - * @} - */ - -/* Include RCC HAL Extension module */ -#include "stm32f7xx_hal_rcc_ex.h" - -/* Exported functions --------------------------------------------------------*/ - /** @addtogroup RCC_Exported_Functions - * @{ - */ - -/** @addtogroup RCC_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions ******************************/ -void HAL_RCC_DeInit(void); -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); -/** - * @} - */ - -/** @addtogroup RCC_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ************************************************/ -void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); -void HAL_RCC_EnableCSS(void); -void HAL_RCC_DisableCSS(void); -uint32_t HAL_RCC_GetSysClockFreq(void); -uint32_t HAL_RCC_GetHCLKFreq(void); -uint32_t HAL_RCC_GetPCLK1Freq(void); -uint32_t HAL_RCC_GetPCLK2Freq(void); -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); - -/* CSS NMI IRQ handler */ -void HAL_RCC_NMI_IRQHandler(void); - -/* User Callbacks in non blocking mode (IT mode) */ -void HAL_RCC_CSSCallback(void); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup RCC_Private_Constants RCC Private Constants - * @{ - */ -#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ -#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ -#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ -#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ - -/** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias - * @brief RCC registers bit address alias - * @{ - */ -/* CIR register byte 2 (Bits[15:8]) base address */ -#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) - -/* CIR register byte 3 (Bits[23:16]) base address */ -#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) - -#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) -#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT -/** - * @} - */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup RCC_Private_Macros RCC Private Macros - * @{ - */ - -/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters - * @{ - */ -#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15) - -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_BYPASS)) - -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_BYPASS)) - -#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) - -#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) - -#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) - -#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ - ((SOURCE) == RCC_PLLSOURCE_HSE)) - -#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) -#define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63)) - -#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) - -#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \ - ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8)) -#define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) - -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \ - ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \ - ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \ - ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \ - ((HCLK) == RCC_SYSCLK_DIV512)) - -#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15)) - -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \ - ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \ - ((PCLK) == RCC_HCLK_DIV16)) - -#define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2)) - - -#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK)) - -#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ - ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) - -#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ - ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ - ((DIV) == RCC_MCODIV_5)) -#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) - -#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31)) - - -#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \ - ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \ - ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \ - ((DRIVE) == RCC_LSEDRIVE_HIGH)) -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_RCC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h b/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h deleted file mode 100644 index 13221c6..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h +++ /dev/null @@ -1,3233 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_rcc_ex.h - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Header file of RCC HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_RCC_EX_H -#define __STM32F7xx_HAL_RCC_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCCEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Types RCCEx Exported Types - * @{ - */ - -/** - * @brief RCC PLL configuration structure definition - */ -typedef struct -{ - uint32_t PLLState; /*!< The new state of the PLL. - This parameter can be a value of @ref RCC_PLL_Config */ - - uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ - - uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ - - uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. - This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ - - uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). - This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ - - uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks. - This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - uint32_t PLLR; /*!< PLLR: Division factor for DSI clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -}RCC_PLLInitTypeDef; - -/** - * @brief PLLI2S Clock structure definition - */ -typedef struct -{ - uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. - This parameter must be a number between Min_Data = 50 and Max_Data = 432. - This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ - - uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 7. - This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ - - uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 15. - This parameter will be used only when PLLI2S is selected as Clock Source SAI */ - - uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock. - This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider. - This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */ -}RCC_PLLI2SInitTypeDef; - -/** - * @brief PLLSAI Clock structure definition - */ -typedef struct -{ - uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. - This parameter must be a number between Min_Data = 50 and Max_Data = 432. - This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ - - uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 15. - This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ - - uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock - This parameter must be a number between Min_Data = 2 and Max_Data = 7. - This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ - - uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock. - This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider - This parameter will be used only when PLLSAI is disabled */ -}RCC_PLLSAIInitTypeDef; - -/** - * @brief RCC extended clocks structure definition - */ -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. - This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ - - RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. - This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ - - uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 32 - This parameter will be used only when PLLI2S is selected as Clock Source SAI */ - - uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 32 - This parameter will be used only when PLLSAI is selected as Clock Source SAI */ - - uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. - This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ - - uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection. - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection. - This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ - - uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. - This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ - - uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection - This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ - - uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection - This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ - - uint32_t Usart1ClockSelection; /*!< USART1 clock source - This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ - - uint32_t Usart2ClockSelection; /*!< USART2 clock source - This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ - - uint32_t Usart3ClockSelection; /*!< USART3 clock source - This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ - - uint32_t Uart4ClockSelection; /*!< UART4 clock source - This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ - - uint32_t Uart5ClockSelection; /*!< UART5 clock source - This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ - - uint32_t Usart6ClockSelection; /*!< USART6 clock source - This parameter can be a value of @ref RCCEx_USART6_Clock_Source */ - - uint32_t Uart7ClockSelection; /*!< UART7 clock source - This parameter can be a value of @ref RCCEx_UART7_Clock_Source */ - - uint32_t Uart8ClockSelection; /*!< UART8 clock source - This parameter can be a value of @ref RCCEx_UART8_Clock_Source */ - - uint32_t I2c1ClockSelection; /*!< I2C1 clock source - This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ - - uint32_t I2c2ClockSelection; /*!< I2C2 clock source - This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ - - uint32_t I2c3ClockSelection; /*!< I2C3 clock source - This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ - - uint32_t I2c4ClockSelection; /*!< I2C4 clock source - This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ - - uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source - This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ - - uint32_t CecClockSelection; /*!< CEC clock source - This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ - - uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC - This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ - - uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source - This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source - This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */ - - uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source - This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ - - uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source - This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -}RCC_PeriphCLKInitTypeDef; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants - * @{ - */ - -/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection - * @{ - */ -#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U) -#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U) -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U) -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U) -#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080U) -#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100U) -#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200U) -#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400U) -#define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800U) -#define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000U) -#define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000U) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000U) -#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000U) -#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000U) -#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000U) -#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000U) -#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000U) -#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000U) -#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000U) -#define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000U) -#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U) -#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U) -#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U) -#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U) -#define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @} - */ - -/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider - * @{ - */ -#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000U) -#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001U) -#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002U) -#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003U) -/** - * @} - */ - -/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider - * @{ - */ -#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000U) -#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001U) -#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002U) -#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003U) -/** - * @} - */ - -/** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR - * @{ - */ -#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U) -#define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0 -#define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1 -#define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR -/** - * @} - */ - -/** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source - * @{ - */ -#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U) -#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC - -/** - * @} - */ - - -/** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source - * @{ - */ -#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) -#define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0 -#define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1 -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL -#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -/** - * @} - */ - -/** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source - * @{ - */ -#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) -#define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0 -#define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1 -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL -#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -/** - * @} - */ - -/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source - * @{ - */ -#define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U) -#define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/ -/** - * @} - */ - -/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source - * @{ - */ -#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) -#define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0 -#define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1 -#define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL -/** - * @} - */ - -/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source - * @{ - */ -#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0 -#define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1 -#define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL -/** - * @} - */ - -/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source - * @{ - */ -#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0 -#define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1 -#define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL -/** - * @} - */ - -/** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source - * @{ - */ -#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0 -#define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1 -#define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL -/** - * @} - */ - -/** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source - * @{ - */ -#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0 -#define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1 -#define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL -/** - * @} - */ - -/** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source - * @{ - */ -#define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) -#define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0 -#define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1 -#define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL -/** - * @} - */ - -/** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source - * @{ - */ -#define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0 -#define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1 -#define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL -/** - * @} - */ - -/** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source - * @{ - */ -#define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0 -#define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1 -#define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL -/** - * @} - */ - -/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source - * @{ - */ -#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0 -#define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1 -/** - * @} - */ - -/** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source - * @{ - */ -#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0 -#define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1 - -/** - * @} - */ - -/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source - * @{ - */ -#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0 -#define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1 -/** - * @} - */ - -/** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source - * @{ - */ -#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0 -#define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1 -/** - * @} - */ - -/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source - * @{ - */ -#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U) -#define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 -#define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 -#define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL - -/** - * @} - */ - -/** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source - * @{ - */ -#define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000U) -#define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL -/** - * @} - */ - -/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection - * @{ - */ -#define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U) -#define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE -/** - * @} - */ - -/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source - * @{ - */ -#define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000U) -#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL -/** - * @} - */ - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -/** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source - * @{ - */ -#define RCC_SDMMC2CLKSOURCE_CLK48 ((uint32_t)0x00000000U) -#define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL -/** - * @} - */ - -/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source - * @{ - */ -#define RCC_DFSDM1CLKSOURCE_PCLK ((uint32_t)0x00000000U) -#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL -/** - * @} - */ - -/** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source - * @{ - */ -#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U) -#define RCC_DFSDM1AUDIOCLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL -/** - * @} - */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#if defined (STM32F769xx) || defined (STM32F779xx) -/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source - * @{ - */ -#define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U) -#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL) -/** - * @} - */ -#endif /* STM32F769xx || STM32F779xx */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros - * @{ - */ -/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable - * @brief Enables or disables the AHB/APB peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -/** @brief Enables or disables the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) -#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN)) -#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN)) -#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) -#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) -#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN)) -#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN)) -#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN)) -#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) -#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) -#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) -#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) -#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) -#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) -#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) -#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) -/** - * @brief Enable ETHERNET clock. - */ -#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_ETH_CLK_ENABLE() do { \ - __HAL_RCC_ETHMAC_CLK_ENABLE(); \ - __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ - __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ - } while(0) -/** - * @brief Disable ETHERNET clock. - */ -#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) -#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) -#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) -#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) -#define __HAL_RCC_ETH_CLK_DISABLE() do { \ - __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ - __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ - __HAL_RCC_ETHMAC_CLK_DISABLE(); \ - } while(0) - -/** @brief Enable or disable the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ - UNUSED(tmpreg); \ - } while(0) - -#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_JPEG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ - UNUSED(tmpreg); \ - } while(0) -#define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#define __HAL_RCC_RNG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ - UNUSED(tmpreg); \ - __HAL_RCC_SYSCFG_CLK_ENABLE();\ - } while(0) - -#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) -#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) - -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) -#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_CRYP_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_HASH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) -#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) -#endif /* STM32F756x || STM32F777xx || STM32F779xx */ - -/** @brief Enables or disables the AHB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#define __HAL_RCC_FMC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) -#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) - -/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_RTC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_CAN3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ - UNUSED(tmpreg); \ - } while(0) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_USART2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_USART3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_UART4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_UART5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_CEC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_DAC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_UART7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_UART8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) -#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) -#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) -#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) -#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) -#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) -#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) -#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) -#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) -#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN)) -#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) -#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) -#define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) -#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) -#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) -#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) -#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) -#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) -#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) -#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) -#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN)) -#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) -#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) -#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) -#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) -#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) -#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) - -/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_USART1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_USART6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ - UNUSED(tmpreg); \ - } while(0) - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ - UNUSED(tmpreg); \ - } while(0) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM9_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM11_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SPI6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ - UNUSED(tmpreg); \ - } while(0) - -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ - UNUSED(tmpreg); \ - } while(0) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#if defined (STM32F769xx) || defined (STM32F779xx) -#define __HAL_RCC_DSI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ - UNUSED(tmpreg); \ - } while(0) -#endif /* STM32F769xx || STM32F779xx */ - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_MDIO_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ - UNUSED(tmpreg); \ - } while(0) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) -#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) -#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) -#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) -#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) -#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) -#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN)) -#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) -#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) -#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) -#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) -#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) -#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) -#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) -#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) -#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) -#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) -#endif /* STM32F769xx || STM32F779xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) -#define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @} - */ - - -/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB/APB peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -/** @brief Get the enable or disable status of the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) -#define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET) -#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET) -#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) -#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) -#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) -#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET) -#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET) -#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET) -#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) -#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) -#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) -#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) -#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET) -#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) -#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) -#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) - -#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) -#define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET) -#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET) -#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) -#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) -#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) -#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET) -#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET) -#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET) -#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) -#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) -#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) -#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) -#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET) -#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) -#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) -#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) -/** - * @brief Enable ETHERNET clock. - */ -#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) -#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) -#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) -#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) -#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ - __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ - __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) - -/** - * @brief Disable ETHERNET clock. - */ -#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) -#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) -#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) -#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) -#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ - __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ - __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) - -/** @brief Get the enable or disable status of the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) -#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) - -#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) -#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) -#define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) - -#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) -#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) -#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) -#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ - -#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET) -#define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** @brief Get the enable or disable status of the AHB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) -#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) - -#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) -#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) - -/** @brief Get the enable or disable status of the APB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) -#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) -#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) -#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) -#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) -#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) -#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) -#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) -#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) -#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET) -#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) -#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) -#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) -#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) -#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) -#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) -#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) -#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) -#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) -#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) -#define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET) -#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) -#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) -#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) -#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) -#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) -#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) - -#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) -#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) -#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) -#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) -#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) -#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) -#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) -#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) -#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) -#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET) -#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) -#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) -#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) -#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) -#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) -#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) -#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) -#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) -#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) -#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) -#define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET) -#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) -#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) -#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) -#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) -#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) -#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) - -/** @brief Get the enable or disable status of the APB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) -#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) -#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) -#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) -#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) -#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) -#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) -#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET) -#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) -#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) -#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) -#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) -#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) -#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) -#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) -#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) -#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) -#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) -#endif /* STM32F769xx || STM32F779xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET) -#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) -#define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) -#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) -#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) -#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) -#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) -#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) -#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) -#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET) -#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) -#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) -#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) -#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) -#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) -#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) -#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) -#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) -#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) -#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) -#endif /* STM32F769xx || STM32F779xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET) -#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) -#define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -/** - * @} - */ - -/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset - * @brief Forces or releases AHB/APB peripheral reset. - * @{ - */ - -/** @brief Force or release AHB1 peripheral reset. - */ -#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) -#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) -#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) -#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) -#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) -#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) -#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) -#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) -#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) -#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) -#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) -#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)) -#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) -#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) -#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) - -#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)) -#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) -#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) -#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) -#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)) -#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)) -#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST)) -#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) -#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) -#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) -#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) -#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)) -#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) -#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) -#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) - -/** @brief Force or release AHB2 peripheral reset. - */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) -#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) -#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) - -#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) -#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) -#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) -#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) - -#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST)) -#define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) -#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) -#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) -#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ - -/** @brief Force or release AHB3 peripheral reset - */ -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) -#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) - -#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) -#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) -#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) - -/** @brief Force or release APB1 peripheral reset. - */ -#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) -#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) -#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) -#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) -#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) -#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) -#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) -#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) -#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) -#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) -#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) -#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) -#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) -#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) -#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST)) -#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) -#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) -#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) -#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) -#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) -#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) - -#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) -#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) -#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) -#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) -#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) -#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) -#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) -#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) -#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) -#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) -#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) -#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) -#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) -#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) -#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST)) -#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) -#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) -#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) -#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) -#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) -#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) - -/** @brief Force or release APB2 peripheral reset. - */ -#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) -#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) -#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) -#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) -#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST)) -#define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST)) -#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) -#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) -#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) -#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) -#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) -#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) -#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) -#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) -#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) -#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) -#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) -#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) -#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST)) -#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST)) -#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) -#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) -#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) -#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) -#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) -#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) -#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) -#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) -#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#if defined (STM32F769xx) || defined (STM32F779xx) -#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) -#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) -#endif /* STM32F769xx || STM32F779xx */ - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST)) -#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) -#define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST)) - -#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST)) -#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) -#define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -/** - * @} - */ - -/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable - * @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. - */ -#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) -#define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN)) -#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) -#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) -#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) -#define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN)) -#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) -#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) -#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) -#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) -#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) -#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) -#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)) -#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN)) -#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN)) -#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) -#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) -#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) -#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) -#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)) -#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) -#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) -#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) - -#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) -#define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN)) -#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) -#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) -#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) -#define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN)) -#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)) -#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) -#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) -#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) -#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) -#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) -#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)) -#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN)) -#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN)) -#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) -#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) -#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) -#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) -#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)) -#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) -#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) -#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) - -/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) -#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) - -#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN)) -#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) -#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) - -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) - -#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) -#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) - -#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) -#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ - -/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) -#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) - -#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) -#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) - -/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) -#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) -#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) -#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) -#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) -#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) -#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) -#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) -#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) -#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN)) -#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) -#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) -#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) -#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) -#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) -#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) -#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) -#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) -#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) -#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) -#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN)) -#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) -#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) -#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) -#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) -#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) -#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) - -#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) -#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) -#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) -#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) -#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) -#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) -#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) -#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) -#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) -#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN)) -#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) -#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) -#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) -#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) -#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) -#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) -#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) -#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) -#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) -#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) -#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN)) -#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) -#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) -#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) -#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) -#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) -#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) - -/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)) -#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) -#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) -#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN)) -#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) -#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) -#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) -#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN)) -#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) -#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) -#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) -#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) -#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) -#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) -#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) -#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) -#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) -#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) -#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) -#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN)) -#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) -#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) -#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) -#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN)) -#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) -#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) -#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) -#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) -#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) -#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) -#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) -#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) -#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) -#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) -#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) -#endif /* STM32F769xx || STM32F779xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN)) -#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) -#define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN)) - -#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN)) -#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) -#define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -/** - * @} - */ - -/** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status - * @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -/** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET) -#define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET) -#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET) -#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET) -#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET) -#define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET) -#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET) -#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET) -#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET) -#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET) -#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET) -#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET) -#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET) -#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET) -#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET) -#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET) -#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET) -#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET) -#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET) -#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET) -#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET) -#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET) -#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET) -#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET) -#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET) - -#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET) -#define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET) -#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET) -#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET) -#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET) -#define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET) -#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET) -#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET) -#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET) -#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET) -#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET) -#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET) -#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET) -#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET) -#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET) -#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET) -#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET) -#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET) -#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET) -#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET) -#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET) -#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET) -#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET) -#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET) -#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET) - -/** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET) -#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET) - -#if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET) -#define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET) -#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET) - -#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET) - -#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET) -#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET) - -#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET) -#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET) -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ - -/** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET) -#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET) - -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET) -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET) - -/** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET) -#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET) -#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET) -#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET) -#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET) -#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET) -#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET) -#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET) -#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET) -#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET) -#define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET) -#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET) -#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET) -#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET) -#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET) -#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET) -#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET) -#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET) -#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET) -#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET) -#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET) -#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET) -#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET) -#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET) -#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET) -#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET) -#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET) - -#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET) -#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET) -#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET) -#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET) -#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET) -#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET) -#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET) -#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET) -#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET) -#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET) -#define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET) -#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET) -#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET) -#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET) -#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET) -#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET) -#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET) -#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET) -#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET) -#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET) -#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET) -#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET) -#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET) -#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET) -#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET) -#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET) -#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET) - -/** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET) -#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET) -#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET) -#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET) -#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET) -#define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET) -#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET) -#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET) -#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET) -#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET) -#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET) -#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET) -#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET) -#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET) -#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET) -#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET) -#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) -#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET) -#endif /* STM32F769xx || STM32F779xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET) -#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET) -#define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET) -#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET) -#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET) -#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET) -#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET) -#define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET) -#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET) -#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET) -#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET) -#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET) -#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET) -#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET) -#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET) -#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET) -#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) -#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET) -#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) -#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET) -#endif /* STM32F769xx || STM32F779xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET) -#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET) -#define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -/** - * @} - */ - -/*------------------------------- PLL Configuration --------------------------*/ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -/** @brief Macro to configure the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * @param __RCC_PLLSource__: specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * @param __PLLM__: specifies the division factor for PLL VCO input clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 63. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLL jitter. - * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock - * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLN parameter correctly to ensure that the VCO - * output frequency is between 100 and 432 MHz. - * @param __PLLP__: specifies the division factor for main system clock (SYSCLK) - * This parameter must be a number in the range {2, 4, 6, or 8}. - * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on - * the System clock frequency. - * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * @note If the USB OTG FS is used in your application, you have to set the - * PLLQ parameter correctly to have 48 MHz clock for the USB. However, - * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work - * correctly. - * @param __PLLR__: specifies the division factor for DSI clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 7. - */ -#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ - (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ - ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ - ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \ - ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) | \ - ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR)))) -#else -/** @brief Macro to configure the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * @param __RCC_PLLSource__: specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * @param __PLLM__: specifies the division factor for PLL VCO input clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 63. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLL jitter. - * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock - * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLN parameter correctly to ensure that the VCO - * output frequency is between 100 and 432 MHz. - * @param __PLLP__: specifies the division factor for main system clock (SYSCLK) - * This parameter must be a number in the range {2, 4, 6, or 8}. - * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on - * the System clock frequency. - * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * @note If the USB OTG FS is used in your application, you have to set the - * PLLQ parameter correctly to have 48 MHz clock for the USB. However, - * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work - * correctly. - */ -#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ - (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \ - ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ - ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \ - ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)))) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -/*---------------------------------------------------------------------------------------------*/ - -/** @brief Macro to configure the Timers clocks prescalers - * @param __PRESC__ : specifies the Timers clocks prescalers selection - * This parameter can be one of the following values: - * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is - * equal to HPRE if PPREx is corresponding to division by 1 or 2, - * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to - * division by 4 or more. - * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is - * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, - * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding - * to division by 8 or more. - */ -#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\ - RCC->DCKCFGR1 |= (__PRESC__); \ - }while(0) - -/** @brief Macros to Enable or Disable the PLLISAI. - * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION)) -#define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION)) - -/** @brief Macro to configure the PLLSAI clock multiplication and division factors. - * @note This function must be used only when the PLLSAI is disabled. - * @note PLLSAI clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock. - * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO - * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. - * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks - * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. - * @param __PLLSAIQ__: specifies the division factor for SAI clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * @param __PLLSAIR__: specifies the division factor for LTDC clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 7. - */ -#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ - (RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\ - ((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\ - ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) |\ - ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))) - -/** @brief Macro to configure the PLLI2S clock multiplication and division factors. - * @note This macro must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * HAL_RCC_ClockConfig() API) - * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock. - * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. - * @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock. - * This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider. - * @param __PLLI2SQ__: specifies the division factor for SAI clock. - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * @param __PLLI2SR__: specifies the division factor for I2S clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 7. - * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. - */ -#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ - (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\ - ((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\ - ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\ - ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))) - -/** @brief Macro to configure the SAI clock Divider coming from PLLI2S. - * @note This function must be called before enabling the PLLI2S. - * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock . - * This parameter must be a number between 1 and 32. - * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ - */ -#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1)) - -/** @brief Macro to configure the SAI clock Divider coming from PLLSAI. - * @note This function must be called before enabling the PLLSAI. - * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock . - * This parameter must be a number between Min_Data = 1 and Max_Data = 32. - * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ - */ -#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8)) - -/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. - * - * @note This function must be called before enabling the PLLSAI. - * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock . - * This parameter can be a value of @ref RCCEx_PLLSAI_DIVR. - * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ - */ -#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\ - MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__)) - -/** @brief Macro to configure SAI1 clock source selection. - * @note This function must be called before enabling PLLSAI, PLLI2S and - * the SAI clock. - * @param __SOURCE__: specifies the SAI1 clock source. - * This parameter can be one of the following values: - * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used - * as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin - * used as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock - * used as SAI1 clock. - * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices - */ -#define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\ - MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__)) - -/** @brief Macro to get the SAI1 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used - * as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin - * used as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock - * used as SAI1 clock. - * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices - */ -#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL))) - - -/** @brief Macro to configure SAI2 clock source selection. - * @note This function must be called before enabling PLLSAI, PLLI2S and - * the SAI clock. - * @param __SOURCE__: specifies the SAI2 clock source. - * This parameter can be one of the following values: - * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used - * as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin - * used as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock - * used as SAI2 clock. - * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices - */ -#define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\ - MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__)) - - -/** @brief Macro to get the SAI2 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used - * as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin - * used as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock - * used as SAI2 clock. - * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices - */ -#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL))) - - -/** @brief Enable PLLSAI_RDY interrupt. - */ -#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) - -/** @brief Disable PLLSAI_RDY interrupt. - */ -#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) - -/** @brief Clear the PLLSAI RDY interrupt pending bits. - */ -#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) - -/** @brief Check the PLLSAI RDY interrupt has occurred or not. - * @retval The new state (TRUE or FALSE). - */ -#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) - -/** @brief Check PLLSAI RDY flag is set or not. - * @retval The new state (TRUE or FALSE). - */ -#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) - -/** @brief Macro to Get I2S clock source selection. - * @retval The clock source can be one of the following values: - * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. - * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source - */ -#define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)) - -/** @brief Macro to configure the I2C1 clock (I2C1CLK). - * - * @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock - * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock - * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock - */ -#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) - -/** @brief Macro to get the I2C1 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock - * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock - * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock - */ -#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL))) - -/** @brief Macro to configure the I2C2 clock (I2C2CLK). - * - * @param __I2C2_CLKSOURCE__: specifies the I2C2 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock - * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock - * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock - */ -#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) - -/** @brief Macro to get the I2C2 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock - * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock - * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock - */ -#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL))) - -/** @brief Macro to configure the I2C3 clock (I2C3CLK). - * - * @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock - * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock - * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock - */ -#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) - -/** @brief macro to get the I2C3 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock - * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock - * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock - */ -#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL))) - -/** @brief Macro to configure the I2C4 clock (I2C4CLK). - * - * @param __I2C4_CLKSOURCE__: specifies the I2C4 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock - * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock - * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock - */ -#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) - -/** @brief macro to get the I2C4 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock - * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock - * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock - */ -#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL))) - -/** @brief Macro to configure the USART1 clock (USART1CLK). - * - * @param __USART1_CLKSOURCE__: specifies the USART1 clock source. - * This parameter can be one of the following values: - * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock - * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock - * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock - * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock - */ -#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) - -/** @brief macro to get the USART1 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock - * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock - * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock - * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock - */ -#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL))) - -/** @brief Macro to configure the USART2 clock (USART2CLK). - * - * @param __USART2_CLKSOURCE__: specifies the USART2 clock source. - * This parameter can be one of the following values: - * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock - * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock - * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock - * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock - */ -#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) - -/** @brief macro to get the USART2 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock - * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock - * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock - * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock - */ -#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL))) - -/** @brief Macro to configure the USART3 clock (USART3CLK). - * - * @param __USART3_CLKSOURCE__: specifies the USART3 clock source. - * This parameter can be one of the following values: - * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock - * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock - * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock - * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock - */ -#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) - -/** @brief macro to get the USART3 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock - * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock - * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock - * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock - */ -#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL))) - - /** @brief Macro to configure the UART4 clock (UART4CLK). - * - * @param __UART4_CLKSOURCE__: specifies the UART4 clock source. - * This parameter can be one of the following values: - * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock - * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock - * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock - * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock - */ -#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) - -/** @brief macro to get the UART4 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock - * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock - * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock - * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock - */ -#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL))) - - /** @brief Macro to configure the UART5 clock (UART5CLK). - * - * @param __UART5_CLKSOURCE__: specifies the UART5 clock source. - * This parameter can be one of the following values: - * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock - * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock - * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock - * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock - */ -#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) - -/** @brief macro to get the UART5 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock - * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock - * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock - * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock - */ -#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL))) - - /** @brief Macro to configure the USART6 clock (USART6CLK). - * - * @param __USART6_CLKSOURCE__: specifies the USART6 clock source. - * This parameter can be one of the following values: - * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock - * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock - * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock - * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock - */ -#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) - -/** @brief macro to get the USART6 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock - * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock - * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock - * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock - */ -#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL))) - - /** @brief Macro to configure the UART7 clock (UART7CLK). - * - * @param __UART7_CLKSOURCE__: specifies the UART7 clock source. - * This parameter can be one of the following values: - * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock - * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock - * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock - * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock - */ -#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__)) - -/** @brief macro to get the UART7 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock - * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock - * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock - * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock - */ -#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL))) - -/** @brief Macro to configure the UART8 clock (UART8CLK). - * - * @param __UART8_CLKSOURCE__: specifies the UART8 clock source. - * This parameter can be one of the following values: - * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock - * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock - * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock - * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock - */ -#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__)) - -/** @brief macro to get the UART8 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock - * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock - * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock - * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock - */ -#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL))) - -/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). - * - * @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source. - * This parameter can be one of the following values: - * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock - */ -#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) - -/** @brief macro to get the LPTIM1 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock - */ -#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))) - -/** @brief Macro to configure the CEC clock (CECCLK). - * - * @param __CEC_CLKSOURCE__: specifies the CEC clock source. - * This parameter can be one of the following values: - * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock - * @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock - */ -#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__)) - -/** @brief macro to get the CEC clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock - * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock - */ -#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))) - -/** @brief Macro to configure the CLK48 source (CLK48CLK). - * - * @param __CLK48_SOURCE__: specifies the CLK48 clock source. - * This parameter can be one of the following values: - * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source - * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source - */ -#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__)) - -/** @brief macro to get the CLK48 source. - * @retval The clock source can be one of the following values: - * @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source - * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source - */ -#define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))) - -/** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK). - * - * @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source. - * This parameter can be one of the following values: - * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock - * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock - */ -#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) - -/** @brief macro to get the SDMMC1 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock - * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock - */ -#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL))) - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -/** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK). - * @param __SDMMC2_CLKSOURCE__: specifies the SDMMC2 clock source. - * This parameter can be one of the following values: - * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock - * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock - */ -#define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__)) - -/** @brief macro to get the SDMMC2 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock - * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock - */ -#define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL))) - -/** @brief Macro to configure the DFSDM1 clock - * @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source. - * This parameter can be one of the following values: - * @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM clock - * @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock - */ -#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) - -/** @brief Macro to get the DFSDM1 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM1 clock - * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System Clock selected as DFSDM1 clock - */ -#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL))) - -/** @brief Macro to configure the DFSDM1 Audio clock - * @param __DFSDM1AUDIO_CLKSOURCE__: specifies the DFSDM1 Audio clock source. - * This parameter can be one of the following values: - * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock - * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock - */ -#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__)) - -/** @brief Macro to get the DFSDM1 Audio clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock - * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock - */ -#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL))) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#if defined (STM32F769xx) || defined (STM32F779xx) -/** @brief Macro to configure the DSI clock. - * @param __DSI_CLKSOURCE__: specifies the DSI clock source. - * This parameter can be one of the following values: - * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. - * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. - */ -#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__))) - -/** @brief Macro to Get the DSI clock. - * @retval The clock source can be one of the following values: - * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. - * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. - */ -#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL)) -#endif /* STM32F769xx || STM32F779xx */ -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCCEx_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); - -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros - * @{ - */ -/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters - * @{ - */ -#if defined(STM32F756xx) || defined(STM32F746xx) -#define IS_RCC_PERIPHCLOCK(SELECTION) \ - ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ - (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ - (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ - (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ - (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ - (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ - (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ - (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ - (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ - (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ - (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) -#elif defined(STM32F745xx) -#define IS_RCC_PERIPHCLOCK(SELECTION) \ - ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ - (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ - (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ - (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ - (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ - (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ - (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ - (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ - (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ - (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) -#elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define IS_RCC_PERIPHCLOCK(SELECTION) \ - ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ - (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ - (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ - (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ - (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ - (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ - (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ - (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ - (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ - (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ - (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ - (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ - (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ - (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) -#elif defined (STM32F765xx) -#define IS_RCC_PERIPHCLOCK(SELECTION) \ - ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ - (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ - (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ - (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ - (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ - (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ - (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ - (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ - (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ - (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ - (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ - (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ - (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) -#endif /* STM32F746xx || STM32F756xx */ -#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ - ((VALUE) == RCC_PLLI2SP_DIV4) ||\ - ((VALUE) == RCC_PLLI2SP_DIV6) ||\ - ((VALUE) == RCC_PLLI2SP_DIV8)) -#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) -#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) - -#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ - ((VALUE) == RCC_PLLSAIP_DIV4) ||\ - ((VALUE) == RCC_PLLSAIP_DIV6) ||\ - ((VALUE) == RCC_PLLSAIP_DIV8)) -#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) -#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) - -#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) - -#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) - -#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ - ((VALUE) == RCC_PLLSAIDIVR_4) ||\ - ((VALUE) == RCC_PLLSAIDIVR_8) ||\ - ((VALUE) == RCC_PLLSAIDIVR_16)) -#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \ - ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) - -#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48)) - -#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ - ((SOURCE) == RCC_CECCLKSOURCE_LSE)) -#define IS_RCC_USART1CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ - ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) - -#define IS_RCC_USART2CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) -#define IS_RCC_USART3CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) - -#define IS_RCC_UART4CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) - -#define IS_RCC_UART5CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) - -#define IS_RCC_USART6CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \ - ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_USART6CLKSOURCE_HSI)) - -#define IS_RCC_UART7CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_UART7CLKSOURCE_HSI)) - -#define IS_RCC_UART8CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_UART8CLKSOURCE_HSI)) -#define IS_RCC_I2C1CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ - ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)) -#define IS_RCC_I2C2CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ - ((SOURCE) == RCC_I2C2CLKSOURCE_HSI)) - -#define IS_RCC_I2C3CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ - ((SOURCE) == RCC_I2C3CLKSOURCE_HSI)) -#define IS_RCC_I2C4CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ - ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)) -#define IS_RCC_LPTIM1CLK(SOURCE) \ - (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || \ - ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \ - ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \ - ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) -#define IS_RCC_CLK48SOURCE(SOURCE) \ - (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \ - ((SOURCE) == RCC_CLK48SOURCE_PLL)) -#define IS_RCC_TIMPRES(VALUE) \ - (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \ - ((VALUE) == RCC_TIMPRES_ACTIVATED)) - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) -#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ - ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ - ((SOURCE) == RCC_SAI1CLKSOURCE_PIN)) -#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ - ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ - ((SOURCE) == RCC_SAI2CLKSOURCE_PIN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx */ - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) - -#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ - ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ - ((SOURCE) == RCC_SAI1CLKSOURCE_PIN) || \ - ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC)) - -#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ - ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ - ((SOURCE) == RCC_SAI2CLKSOURCE_PIN) || \ - ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) - -#define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48)) - -#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK) || \ - ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK)) - -#define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ - ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ - ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_RCC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h b/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h deleted file mode 100644 index fbab466..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h +++ /dev/null @@ -1,1221 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_uart.h - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Header file of UART HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_UART_H -#define __STM32F7xx_HAL_UART_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup UART - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup UART_Exported_Types UART Exported Types - * @{ - */ - -/** - * @brief UART Init Structure definition - */ -typedef struct -{ - uint32_t BaudRate; /*!< This member configures the UART communication baud rate. - The baud rate register is computed using the following formula: - - If oversampling is 16 or in LIN mode, - Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))) - - If oversampling is 8, - Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4] - Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */ - - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref UARTEx_Word_Length */ - - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref UART_Stop_Bits */ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref UART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref UART_Mode */ - - uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref UART_Hardware_Flow_Control */ - - uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8). - This parameter can be a value of @ref UART_Over_Sampling */ - - uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. - Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref UART_OneBit_Sampling */ -}UART_InitTypeDef; - -/** - * @brief UART Advanced Features initialization structure definition - */ -typedef struct -{ - uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several - Advanced Features may be initialized at the same time . - This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type */ - - uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. - This parameter can be a value of @ref UART_Tx_Inv */ - - uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. - This parameter can be a value of @ref UART_Rx_Inv */ - - uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic - vs negative/inverted logic). - This parameter can be a value of @ref UART_Data_Inv */ - - uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. - This parameter can be a value of @ref UART_Rx_Tx_Swap */ - - uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. - This parameter can be a value of @ref UART_Overrun_Disable */ - - uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. - This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error */ - - uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. - This parameter can be a value of @ref UART_AutoBaudRate_Enable */ - - uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate - detection is carried out. - This parameter can be a value of @ref UART_AutoBaud_Rate_Mode */ - - uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. - This parameter can be a value of @ref UART_MSB_First */ -} UART_AdvFeatureInitTypeDef; - - - -/** - * @brief HAL UART State structures definition - * @note HAL UART State value is a combination of 2 different substates: gState and RxState. - * - gState contains UART state information related to global Handle management - * and also information related to Tx operations. - * gState value coding follow below described bitmap : - * b7-b6 Error information - * 00 : No Error - * 01 : (Not Used) - * 10 : Timeout - * 11 : Error - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP not initialized. HAL UART Init function already called) - * b4-b3 (not used) - * xx : Should be set to 00 - * b2 Intrinsic process state - * 0 : Ready - * 1 : Busy (IP busy with some configuration or internal operations) - * b1 (not used) - * x : Should be set to 0 - * b0 Tx state - * 0 : Ready (no Tx operation ongoing) - * 1 : Busy (Tx operation ongoing) - * - RxState contains information related to Rx operations. - * RxState value coding follow below described bitmap : - * b7-b6 (not used) - * xx : Should be set to 00 - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP not initialized) - * b4-b2 (not used) - * xxx : Should be set to 000 - * b1 Rx state - * 0 : Ready (no Rx operation ongoing) - * 1 : Busy (Rx operation ongoing) - * b0 (not used) - * x : Should be set to 0. - */ -typedef enum -{ - HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized - Value is allowed for gState and RxState */ - HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ - HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing - Value is allowed for gState only */ - HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing - Value is allowed for gState only */ - HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing - Value is allowed for RxState only */ - HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ - HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state - Value is allowed for gState only */ - HAL_UART_STATE_ERROR = 0xE0U /*!< Error - Value is allowed for gState only */ -}HAL_UART_StateTypeDef; - -/** - * @brief UART clock sources definition - */ -typedef enum -{ - UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ - UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ - UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ - UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ - UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ - UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ -}UART_ClockSourceTypeDef; - -/** - * @brief UART handle Structure definition - */ -typedef struct -{ - USART_TypeDef *Instance; /*!< UART registers base address */ - - UART_InitTypeDef Init; /*!< UART communication parameters */ - - UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ - - uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ - - uint16_t TxXferSize; /*!< UART Tx Transfer size */ - - uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ - - uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ - - uint16_t RxXferSize; /*!< UART Rx Transfer size */ - - uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ - - uint16_t Mask; /*!< UART Rx RDR register mask */ - - DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ - - HAL_LockTypeDef Lock; /*!< Locking object */ - - __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ - - __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ - - __IO uint32_t ErrorCode; /*!< UART Error code */ - -}UART_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UART_Exported_Constants UART Exported Constants - * @{ - */ -/** @defgroup UART_Error_Definition UART Error Definition - * @{ - */ -#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ -#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -/** - * @} - */ -/** @defgroup UART_Stop_Bits UART Number of Stop Bits - * @{ - */ -#define UART_STOPBITS_1 ((uint32_t)0x00000000U) -#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) -/** - * @} - */ - -/** @defgroup UART_Parity UART Parity - * @{ - */ -#define UART_PARITY_NONE ((uint32_t)0x00000000U) -#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) -#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) -/** - * @} - */ - -/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control - * @{ - */ -#define UART_HWCONTROL_NONE ((uint32_t)0x00000000U) -#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) -#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) -#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) -/** - * @} - */ - -/** @defgroup UART_Mode UART Transfer Mode - * @{ - */ -#define UART_MODE_RX ((uint32_t)USART_CR1_RE) -#define UART_MODE_TX ((uint32_t)USART_CR1_TE) -#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) -/** - * @} - */ - - /** @defgroup UART_State UART State - * @{ - */ -#define UART_STATE_DISABLE ((uint32_t)0x00000000U) -#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) -/** - * @} - */ - -/** @defgroup UART_Over_Sampling UART Over Sampling - * @{ - */ -#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000U) -#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) -/** - * @} - */ - -/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method - * @{ - */ -#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000U) -#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) -/** - * @} - */ - -/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode - * @{ - */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000U) -#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) -/** - * @} - */ - -/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut - * @{ - */ -#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000U) -#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) -/** - * @} - */ - -/** @defgroup UART_LIN UART Local Interconnection Network mode - * @{ - */ -#define UART_LIN_DISABLE ((uint32_t)0x00000000U) -#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) -/** - * @} - */ - -/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection - * @{ - */ -#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000U) -#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) -/** - * @} - */ - -/** @defgroup UART_DMA_Tx UART DMA Tx - * @{ - */ -#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000U) -#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) -/** - * @} - */ - -/** @defgroup UART_DMA_Rx UART DMA Rx - * @{ - */ -#define UART_DMA_RX_DISABLE ((uint32_t)0x0000U) -#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) -/** - * @} - */ - -/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection - * @{ - */ -#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000U) -#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) -/** - * @} - */ - -/** @defgroup UART_WakeUp_Methods UART WakeUp Methods - * @{ - */ -#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000U) -#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) -/** - * @} - */ - -/** @defgroup UART_Request_Parameters UART Request Parameters - * @{ - */ -#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */ -#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */ -#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */ -#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ -#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ -/** - * @} - */ - -/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type - * @{ - */ -#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000U) -#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001U) -#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002U) -#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004U) -#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008U) -#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010U) -#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020U) -#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040U) -#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080U) -/** - * @} - */ - -/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion - * @{ - */ -#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000U) -#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) -/** - * @} - */ - -/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion - * @{ - */ -#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000U) -#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) -/** - * @} - */ - -/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion - * @{ - */ -#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000U) -#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) -/** - * @} - */ - -/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap - * @{ - */ -#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000U) -#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) -/** - * @} - */ - -/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable - * @{ - */ -#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000U) -#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) -/** - * @} - */ - -/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable - * @{ - */ -#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000U) -#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) -/** - * @} - */ - -/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error - * @{ - */ -#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000U) -#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) -/** - * @} - */ - -/** @defgroup UART_MSB_First UART Advanced Feature MSB First - * @{ - */ -#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000U) -#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) -/** - * @} - */ - -/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable - * @{ - */ -#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000U) -#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) -/** - * @} - */ - -/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register - * @{ - */ -#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24U) -/** - * @} - */ - -/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity - * @{ - */ -#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000U) -#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) -/** - * @} - */ - -/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register - * @{ - */ -#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21U) -/** - * @} - */ - -/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register - * @{ - */ -#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16U) -/** - * @} - */ - -/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask - * @{ - */ -#define UART_IT_MASK ((uint32_t)0x001FU) -/** - * @} - */ - -/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value - * @{ - */ -#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU -/** - * @} - */ - -/** @defgroup UART_Flags UART Status Flags - * Elements values convention: 0xXXXX - * - 0xXXXX : Flag mask in the ISR register - * @{ - */ -#define UART_FLAG_TEACK ((uint32_t)0x00200000U) -#define UART_FLAG_SBKF ((uint32_t)0x00040000U) -#define UART_FLAG_CMF ((uint32_t)0x00020000U) -#define UART_FLAG_BUSY ((uint32_t)0x00010000U) -#define UART_FLAG_ABRF ((uint32_t)0x00008000U) -#define UART_FLAG_ABRE ((uint32_t)0x00004000U) -#define UART_FLAG_EOBF ((uint32_t)0x00001000U) -#define UART_FLAG_RTOF ((uint32_t)0x00000800U) -#define UART_FLAG_CTS ((uint32_t)0x00000400U) -#define UART_FLAG_CTSIF ((uint32_t)0x00000200U) -#define UART_FLAG_LBDF ((uint32_t)0x00000100U) -#define UART_FLAG_TXE ((uint32_t)0x00000080U) -#define UART_FLAG_TC ((uint32_t)0x00000040U) -#define UART_FLAG_RXNE ((uint32_t)0x00000020U) -#define UART_FLAG_IDLE ((uint32_t)0x00000010U) -#define UART_FLAG_ORE ((uint32_t)0x00000008U) -#define UART_FLAG_NE ((uint32_t)0x00000004U) -#define UART_FLAG_FE ((uint32_t)0x00000002U) -#define UART_FLAG_PE ((uint32_t)0x00000001U) -/** - * @} - */ - -/** @defgroup UART_Interrupt_definition UART Interrupts Definition - * Elements values convention: 0000ZZZZ0XXYYYYYb - * - YYYYY : Interrupt source position in the XX register (5bits) - * - XX : Interrupt source register (2bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register - * - ZZZZ : Flag position in the ISR register(4bits) - * @{ - */ -#define UART_IT_PE ((uint32_t)0x0028U) -#define UART_IT_TXE ((uint32_t)0x0727U) -#define UART_IT_TC ((uint32_t)0x0626U) -#define UART_IT_RXNE ((uint32_t)0x0525U) -#define UART_IT_IDLE ((uint32_t)0x0424U) -#define UART_IT_LBD ((uint32_t)0x0846U) -#define UART_IT_CTS ((uint32_t)0x096AU) -#define UART_IT_CM ((uint32_t)0x112EU) - -/** Elements values convention: 000000000XXYYYYYb - * - YYYYY : Interrupt source position in the XX register (5bits) - * - XX : Interrupt source register (2bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register - */ -#define UART_IT_ERR ((uint32_t)0x0060U) - -/** Elements values convention: 0000ZZZZ00000000b - * - ZZZZ : Flag position in the ISR register(4bits) - */ -#define UART_IT_ORE ((uint32_t)0x0300U) -#define UART_IT_NE ((uint32_t)0x0200U) -#define UART_IT_FE ((uint32_t)0x0100U) -/** - * @} - */ - -/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags - * @{ - */ -#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ -#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ -#define UART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ -#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ -#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ -#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ -#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ -#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */ -#define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */ -#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ -/** - * @} - */ - - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup UART_Exported_Macros UART Exported Macros - * @{ - */ - -/** @brief Reset UART handle state - * @param __HANDLE__: UART handle. - * @retval None - */ -#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ - } while(0) - -/** @brief Flush the UART Data registers - * @param __HANDLE__: specifies the UART Handle. - */ -#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ - } while(0) - -/** @brief Clears the specified UART ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__: specifies the UART Handle. - * @param __FLAG__: specifies the interrupt clear register flag that needs to be set - * to clear the corresponding interrupt - * This parameter can be one of the following values: - * @arg UART_CLEAR_PEF: Parity Error Clear Flag - * @arg UART_CLEAR_FEF: Framing Error Clear Flag - * @arg UART_CLEAR_NEF: Noise detected Clear Flag - * @arg UART_CLEAR_OREF: OverRun Error Clear Flag - * @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag - * @arg UART_CLEAR_TCF: Transmission Complete Clear Flag - * @arg UART_CLEAR_LBDF: LIN Break Detection Clear Flag - * @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag - * @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag - * @arg UART_CLEAR_EOBF: End Of Block Clear Flag - * @arg UART_CLEAR_CMF: Character Match Clear Flag - * @retval None - */ -#define __HAL_UART_CLEAR_IT(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__FLAG__)) - -/** @brief Clear the UART PE pending flag. - * @param __HANDLE__: specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_PEF) - -/** @brief Clear the UART FE pending flag. - * @param __HANDLE__: specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_FEF) - -/** @brief Clear the UART NE pending flag. - * @param __HANDLE__: specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_NEF) - -/** @brief Clear the UART ORE pending flag. - * @param __HANDLE__: specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_OREF) - -/** @brief Clear the UART IDLE pending flag. - * @param __HANDLE__: specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_IDLEF) - -/** @brief Checks whether the specified UART flag is set or not. - * @param __HANDLE__: specifies the UART Handle. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg UART_FLAG_REACK: Receive enable acknowledge flag - * @arg UART_FLAG_TEACK: Transmit enable acknowledge flag - * @arg UART_FLAG_WUF: Wake up from stop mode flag - * @arg UART_FLAG_RWU: Receiver wake up flag (is the UART in mute mode) - * @arg UART_FLAG_SBKF: Send Break flag - * @arg UART_FLAG_CMF: Character match flag - * @arg UART_FLAG_BUSY: Busy flag - * @arg UART_FLAG_ABRF: Auto Baud rate detection flag - * @arg UART_FLAG_ABRE: Auto Baud rate detection error flag - * @arg UART_FLAG_EOBF: End of block flag - * @arg UART_FLAG_RTOF: Receiver timeout flag - * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) - * @arg UART_FLAG_LBD: LIN Break detection flag - * @arg UART_FLAG_TXE: Transmit data register empty flag - * @arg UART_FLAG_TC: Transmission Complete flag - * @arg UART_FLAG_RXNE: Receive data register not empty flag - * @arg UART_FLAG_IDLE: Idle Line detection flag - * @arg UART_FLAG_ORE: OverRun Error flag - * @arg UART_FLAG_NE: Noise Error flag - * @arg UART_FLAG_FE: Framing Error flag - * @arg UART_FLAG_PE: Parity Error flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) - -/** @brief Enables the specified UART interrupt. - * @param __HANDLE__: specifies the UART Handle. - * @param __INTERRUPT__: specifies the UART interrupt source to enable. - * This parameter can be one of the following values: - * @arg UART_IT_WUF: Wakeup from stop mode interrupt - * @arg UART_IT_CM: Character match interrupt - * @arg UART_IT_CTS: CTS change interrupt - * @arg UART_IT_LBD: LIN Break detection interrupt - * @arg UART_IT_TXE: Transmit Data Register empty interrupt - * @arg UART_IT_TC: Transmission complete interrupt - * @arg UART_IT_RXNE: Receive Data register not empty interrupt - * @arg UART_IT_IDLE: Idle line detection interrupt - * @arg UART_IT_PE: Parity Error interrupt - * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK)))) - - -/** @brief Disables the specified UART interrupt. - * @param __HANDLE__: specifies the UART Handle. - * @param __INTERRUPT__: specifies the UART interrupt source to disable. - * This parameter can be one of the following values: - * @arg UART_IT_CM: Character match interrupt - * @arg UART_IT_CTS: CTS change interrupt - * @arg UART_IT_LBD: LIN Break detection interrupt - * @arg UART_IT_TXE: Transmit Data Register empty interrupt - * @arg UART_IT_TC: Transmission complete interrupt - * @arg UART_IT_RXNE: Receive Data register not empty interrupt - * @arg UART_IT_IDLE: Idle line detection interrupt - * @arg UART_IT_PE: Parity Error interrupt - * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK)))) - -/** @brief Checks whether the specified UART interrupt has occurred or not. - * @param __HANDLE__: specifies the UART Handle. - * @param __IT__: specifies the UART interrupt to check. - * This parameter can be one of the following values: - * @arg UART_IT_CM: Character match interrupt - * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg UART_IT_LBD: LIN Break detection interrupt - * @arg UART_IT_TXE: Transmit Data Register empty interrupt - * @arg UART_IT_TC: Transmission complete interrupt - * @arg UART_IT_RXNE: Receive Data register not empty interrupt - * @arg UART_IT_IDLE: Idle line detection interrupt - * @arg UART_IT_ORE: OverRun Error interrupt - * @arg UART_IT_NE: Noise Error interrupt - * @arg UART_IT_FE: Framing Error interrupt - * @arg UART_IT_PE: Parity Error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) - -/** @brief Checks whether the specified UART interrupt source is enabled. - * @param __HANDLE__: specifies the UART Handle. - * @param __IT__: specifies the UART interrupt source to check. - * This parameter can be one of the following values: - * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg UART_IT_LBD: LIN Break detection interrupt - * @arg UART_IT_TXE: Transmit Data Register empty interrupt - * @arg UART_IT_TC: Transmission complete interrupt - * @arg UART_IT_RXNE: Receive Data register not empty interrupt - * @arg UART_IT_IDLE: Idle line detection interrupt - * @arg UART_IT_ORE: OverRun Error interrupt - * @arg UART_IT_NE: Noise Error interrupt - * @arg UART_IT_FE: Framing Error interrupt - * @arg UART_IT_PE: Parity Error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK))) - -/** @brief Set a specific UART request flag. - * @param __HANDLE__: specifies the UART Handle. - * @param __REQ__: specifies the request flag to set - * This parameter can be one of the following values: - * @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request - * @arg UART_SENDBREAK_REQUEST: Send Break Request - * @arg UART_MUTE_MODE_REQUEST: Mute Mode Request - * @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request - * @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request - * @retval None - */ -#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__)) - -/** @brief Enables the UART one bit sample method - * @param __HANDLE__: specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) - -/** @brief Disables the UART one bit sample method - * @param __HANDLE__: specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) - -/** @brief Enable UART - * @param __HANDLE__: specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) - -/** @brief Disable UART - * @param __HANDLE__: specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) - -/** @brief Enable CTS flow control - * This macro allows to enable CTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. - * The Handle Instance can be USART1, USART2 or LPUART. - * @retval None - */ -#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ - } while(0) - -/** @brief Disable CTS flow control - * This macro allows to disable CTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. - * The Handle Instance can be USART1, USART2 or LPUART. - * @retval None - */ -#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ - } while(0) - -/** @brief Enable RTS flow control - * This macro allows to enable RTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. - * The Handle Instance can be USART1, USART2 or LPUART. - * @retval None - */ -#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ - } while(0) - -/** @brief Disable RTS flow control - * This macro allows to disable RTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. - * The Handle Instance can be USART1, USART2 or LPUART. - * @retval None - */ -#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ - } while(0) - -/** - * @} - */ - -/* Private macros --------------------------------------------------------*/ -/** @defgroup UART_Private_Macros UART Private Macros - * @{ - */ -/** @brief BRR division operation to set BRR register with LPUART - * @param _PCLK_: LPUART clock - * @param _BAUD_: Baud rate set by the user - * @retval Division result - */ -#define UART_DIV_LPUART(_PCLK_, _BAUD_) ((((_PCLK_)*256)+((_BAUD_)/2))/((_BAUD_))) - -/** @brief BRR division operation to set BRR register in 8-bit oversampling mode - * @param _PCLK_: UART clock - * @param _BAUD_: Baud rate set by the user - * @retval Division result - */ -#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) ((((_PCLK_)*2)+((_BAUD_)/2))/((_BAUD_))) - -/** @brief BRR division operation to set BRR register in 16-bit oversampling mode - * @param _PCLK_: UART clock - * @param _BAUD_: Baud rate set by the user - * @retval Division result - */ -#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) ((((_PCLK_))+((_BAUD_)/2))/((_BAUD_))) - -/** @brief Check UART Baud rate - * @param BAUDRATE: Baudrate specified by the user - * The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 216 MHz) - * divided by the smallest oversampling used on the USART (i.e. 8) - * @retval Test result (TRUE or FALSE). - */ -#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001) - -/** @brief Check UART assertion time - * @param TIME: 5-bit value assertion time - * @retval Test result (TRUE or FALSE). - */ -#define IS_UART_ASSERTIONTIME(TIME) ((TIME) <= 0x1F) - -/** @brief Check UART deassertion time - * @param TIME: 5-bit value deassertion time - * @retval Test result (TRUE or FALSE). - */ -#define IS_UART_DEASSERTIONTIME(TIME) ((TIME) <= 0x1F) - -#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ - ((STOPBITS) == UART_STOPBITS_2)) - -#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ - ((PARITY) == UART_PARITY_EVEN) || \ - ((PARITY) == UART_PARITY_ODD)) - -#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == UART_HWCONTROL_NONE) || \ - ((CONTROL) == UART_HWCONTROL_RTS) || \ - ((CONTROL) == UART_HWCONTROL_CTS) || \ - ((CONTROL) == UART_HWCONTROL_RTS_CTS)) - -#define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((MODE) != (uint32_t)0x00)) - -#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ - ((STATE) == UART_STATE_ENABLE)) - -#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \ - ((SAMPLING) == UART_OVERSAMPLING_8)) - -#define IS_UART_ONE_BIT_SAMPLE(ONEBIT) (((ONEBIT) == UART_ONE_BIT_SAMPLE_DISABLE) || \ - ((ONEBIT) == UART_ONE_BIT_SAMPLE_ENABLE)) - -#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE) (((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ - ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ - ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ - ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) - -#define IS_UART_RECEIVER_TIMEOUT(TIMEOUT) (((TIMEOUT) == UART_RECEIVER_TIMEOUT_DISABLE) || \ - ((TIMEOUT) == UART_RECEIVER_TIMEOUT_ENABLE)) - -#define IS_UART_LIN(LIN) (((LIN) == UART_LIN_DISABLE) || \ - ((LIN) == UART_LIN_ENABLE)) - -#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \ - ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) - -#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ - ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) - -#define IS_UART_DMA_TX(DMATX) (((DMATX) == UART_DMA_TX_DISABLE) || \ - ((DMATX) == UART_DMA_TX_ENABLE)) - -#define IS_UART_DMA_RX(DMARX) (((DMARX) == UART_DMA_RX_DISABLE) || \ - ((DMARX) == UART_DMA_RX_ENABLE)) - -#define IS_UART_HALF_DUPLEX(HDSEL) (((HDSEL) == UART_HALF_DUPLEX_DISABLE) || \ - ((HDSEL) == UART_HALF_DUPLEX_ENABLE)) - -#define IS_UART_REQUEST_PARAMETER(PARAM) (((PARAM) == UART_AUTOBAUD_REQUEST) || \ - ((PARAM) == UART_SENDBREAK_REQUEST) || \ - ((PARAM) == UART_MUTE_MODE_REQUEST) || \ - ((PARAM) == UART_RXDATA_FLUSH_REQUEST) || \ - ((PARAM) == UART_TXDATA_FLUSH_REQUEST)) - -#define IS_UART_ADVFEATURE_INIT(INIT) ((INIT) <= (UART_ADVFEATURE_NO_INIT | \ - UART_ADVFEATURE_TXINVERT_INIT | \ - UART_ADVFEATURE_RXINVERT_INIT | \ - UART_ADVFEATURE_DATAINVERT_INIT | \ - UART_ADVFEATURE_SWAP_INIT | \ - UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ - UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ - UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ - UART_ADVFEATURE_MSBFIRST_INIT)) - -#define IS_UART_ADVFEATURE_TXINV(TXINV) (((TXINV) == UART_ADVFEATURE_TXINV_DISABLE) || \ - ((TXINV) == UART_ADVFEATURE_TXINV_ENABLE)) - -#define IS_UART_ADVFEATURE_RXINV(RXINV) (((RXINV) == UART_ADVFEATURE_RXINV_DISABLE) || \ - ((RXINV) == UART_ADVFEATURE_RXINV_ENABLE)) - -#define IS_UART_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == UART_ADVFEATURE_DATAINV_DISABLE) || \ - ((DATAINV) == UART_ADVFEATURE_DATAINV_ENABLE)) - -#define IS_UART_ADVFEATURE_SWAP(SWAP) (((SWAP) == UART_ADVFEATURE_SWAP_DISABLE) || \ - ((SWAP) == UART_ADVFEATURE_SWAP_ENABLE)) - -#define IS_UART_OVERRUN(OVERRUN) (((OVERRUN) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ - ((OVERRUN) == UART_ADVFEATURE_OVERRUN_DISABLE)) - -#define IS_UART_ADVFEATURE_AUTOBAUDRATE(AUTOBAUDRATE) (((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ - ((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) - -#define IS_UART_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ - ((DMA) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) - -#define IS_UART_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ - ((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_ENABLE)) - -#define IS_UART_MUTE_MODE(MUTE) (((MUTE) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ - ((MUTE) == UART_ADVFEATURE_MUTEMODE_ENABLE)) - -#define IS_UART_DE_POLARITY(POLARITY) (((POLARITY) == UART_DE_POLARITY_HIGH) || \ - ((POLARITY) == UART_DE_POLARITY_LOW)) - -/** - * @} - */ -/* Include UART HAL Extension module */ -#include "stm32f7xx_hal_uart_ex.h" -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup UART_Exported_Functions UART Exported Functions - * @{ - */ - -/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); -HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime); -HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart); -void HAL_UART_MspInit(UART_HandleTypeDef *huart); -void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group2 IO operation functions - * @{ - */ - -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); - -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); -void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions - * @{ - */ - -/* Peripheral Control functions ************************************************/ -HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); -HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); -void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions - * @{ - */ - -/* Peripheral State and Errors functions **************************************************/ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** - * @} - */ - -/* Private functions -----------------------------------------------------------*/ -/** @addtogroup UART_Private_Functions UART Private Functions - * @{ - */ - -HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); -void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_UART_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h b/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h deleted file mode 100644 index a1b4cd2..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +++ /dev/null @@ -1,365 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_uart_ex.h - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Header file of UART HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_UART_EX_H -#define __STM32F7xx_HAL_UART_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup UARTEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants - * @{ - */ - -/** @defgroup UARTEx_Word_Length UARTEx Word Length - * @{ - */ -#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1) -#define UART_WORDLENGTH_8B ((uint32_t)0x0000U) -#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0) -#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ - ((__LENGTH__) == UART_WORDLENGTH_8B) || \ - ((__LENGTH__) == UART_WORDLENGTH_9B)) -#define IS_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B)) -/** - * @} - */ - - -/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length - * @{ - */ -#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000U) -#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) -#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ - ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) -/** - * @} - */ - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup UARTEx_Exported_Macros UARTEx Exported Macros - * @{ - */ - -/** @brief Reports the UART clock source. - * @param __HANDLE__: specifies the UART Handle - * @param __CLOCKSOURCE__: output variable - * @retval UART clocking source, written in __CLOCKSOURCE__. - */ -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ - case RCC_USART3CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART3CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART3CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART3CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == UART4) \ - { \ - switch(__HAL_RCC_GET_UART4_SOURCE()) \ - { \ - case RCC_UART4CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_UART4CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_UART4CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_UART4CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - break; \ - } \ - } \ - else if ((__HANDLE__)->Instance == UART5) \ - { \ - switch(__HAL_RCC_GET_UART5_SOURCE()) \ - { \ - case RCC_UART5CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_UART5CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_UART5CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_UART5CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART6) \ - { \ - switch(__HAL_RCC_GET_USART6_SOURCE()) \ - { \ - case RCC_USART6CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART6CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART6CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART6CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - break; \ - } \ - } \ - else if ((__HANDLE__)->Instance == UART7) \ - { \ - switch(__HAL_RCC_GET_UART7_SOURCE()) \ - { \ - case RCC_UART7CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_UART7CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_UART7CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_UART7CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - break; \ - } \ - } \ - else if ((__HANDLE__)->Instance == UART8) \ - { \ - switch(__HAL_RCC_GET_UART8_SOURCE()) \ - { \ - case RCC_UART8CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_UART8CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_UART8CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_UART8CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - break; \ - } \ - } \ - } while(0) - -/** @brief Reports the UART mask to apply to retrieve the received data - * according to the word length and to the parity bits activation. - * If PCE = 1, the parity bit is not included in the data extracted - * by the reception API(). - * This masking operation is not carried out in the case of - * DMA transfers. - * @param __HANDLE__: specifies the UART Handle - * @retval mask to apply to UART RDR register value. - */ -#define UART_MASK_COMPUTATION(__HANDLE__) \ - do { \ - if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x01FF ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x00FF ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x00FF ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x007F ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x007F ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x003F ; \ - } \ - } \ -} while(0) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup UARTEx_Exported_Functions - * @{ - */ - -/** @addtogroup UARTEx_Exported_Functions_Group1 - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime); - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup UARTEx_Exported_Functions_Group3 - * @{ - */ - -/* Peripheral Control functions **********************************************/ -HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_UART_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c deleted file mode 100644 index 5eb21fe..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c +++ /dev/null @@ -1,536 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief HAL module driver. - * This is the common part of the HAL initialization - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The common HAL driver contains a set of generic and common APIs that can be - used by the PPP peripheral drivers and the user to start using the HAL. - [..] - The HAL contains two APIs' categories: - (+) Common HAL APIs - (+) Services HAL APIs - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup HAL HAL - * @brief HAL module driver. - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup HAL_Private_Constants - * @{ - */ -/** - * @brief STM32F7xx HAL Driver version number V1.1.0 - */ -#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F7xx_HAL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ -#define __STM32F7xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\ - |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\ - |(__STM32F7xx_HAL_VERSION_SUB2 << 8 )\ - |(__STM32F7xx_HAL_VERSION_RC)) - -#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @addtogroup HAL_Private_Variables - * @{ - */ -__IO uint32_t uwTick; -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HAL_Exported_Functions HAL Exported Functions - * @{ - */ - -/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initializes the Flash interface the NVIC allocation and initial clock - configuration. It initializes the systick also when timeout is needed - and the backup domain when enabled. - (+) de-Initializes common part of the HAL - (+) Configure The time base source to have 1ms time base with a dedicated - Tick interrupt priority. - (++) Systick timer is used by default as source of time base, but user - can eventually implement his proper time base source (a general purpose - timer for example or other time source), keeping in mind that Time base - duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and - handled in milliseconds basis. - (++) Time base configuration function (HAL_InitTick ()) is called automatically - at the beginning of the program after reset by HAL_Init() or at any time - when clock is configured, by HAL_RCC_ClockConfig(). - (++) Source of time base is configured to generate interrupts at regular - time intervals. Care must be taken if HAL_Delay() is called from a - peripheral ISR process, the Tick interrupt line must have higher priority - (numerically lower) than the peripheral interrupt. Otherwise the caller - ISR process will be blocked. - (++) functions affecting time base configurations are declared as __weak - to make override possible in case of other implementations in user file. -@endverbatim - * @{ - */ - -/** - * @brief This function is used to initialize the HAL Library; it must be the first - * instruction to be executed in the main program (before to call any other - * HAL function), it performs the following: - * Configure the Flash prefetch, and instruction cache through ART accelerator. - * Configures the SysTick to generate an interrupt each 1 millisecond, - * which is clocked by the HSI (at this stage, the clock is not yet - * configured and thus the system is running from the internal HSI at 16 MHz). - * Set NVIC Group Priority to 4. - * Calls the HAL_MspInit() callback function defined in user file - * "stm32f7xx_hal_msp.c" to do the global low level hardware initialization - * - * @note SysTick is used as time base for the HAL_Delay() function, the application - * need to ensure that the SysTick time base is always set to 1 millisecond - * to have correct HAL operation. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_Init(void) -{ - /* Configure Flash prefetch and Instruction cache through ART accelerator */ -#if (ART_ACCLERATOR_ENABLE != 0) - __HAL_FLASH_ART_ENABLE(); -#endif /* ART_ACCLERATOR_ENABLE */ - - /* Set Interrupt Group Priority */ - HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - - /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ - HAL_InitTick(TICK_INT_PRIORITY); - - /* Init the low level hardware */ - HAL_MspInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief This function de-Initializes common part of the HAL and stops the systick. - * This function is optional. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DeInit(void) -{ - /* Reset of all peripherals */ - __HAL_RCC_APB1_FORCE_RESET(); - __HAL_RCC_APB1_RELEASE_RESET(); - - __HAL_RCC_APB2_FORCE_RESET(); - __HAL_RCC_APB2_RELEASE_RESET(); - - __HAL_RCC_AHB1_FORCE_RESET(); - __HAL_RCC_AHB1_RELEASE_RESET(); - - __HAL_RCC_AHB2_FORCE_RESET(); - __HAL_RCC_AHB2_RELEASE_RESET(); - - __HAL_RCC_AHB3_FORCE_RESET(); - __HAL_RCC_AHB3_RELEASE_RESET(); - - /* De-Init the low level hardware */ - HAL_MspDeInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the MSP. - * @retval None - */ -__weak void HAL_MspInit(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the MSP. - * @retval None - */ -__weak void HAL_MspDeInit(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief This function configures the source of the time base. - * The time source is configured to have 1ms time base with a dedicated - * Tick interrupt priority. - * @note This function is called automatically at the beginning of program after - * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). - * @note In the default implementation, SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals. - * Care must be taken if HAL_Delay() is called from a peripheral ISR process, - * The the SysTick interrupt must have higher priority (numerically lower) - * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. - * The function is declared as __weak to be overwritten in case of other - * implementation in user file. - * @param TickPriority: Tick interrupt priority. - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) -{ - /*Configure the SysTick to have interrupt in 1ms time basis*/ - HAL_SYSTICK_Config(SystemCoreClock/1000); - - /*Configure the SysTick IRQ priority */ - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions - * @brief HAL Control functions - * -@verbatim - =============================================================================== - ##### HAL Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Provide a tick value in millisecond - (+) Provide a blocking delay in millisecond - (+) Suspend the time base source interrupt - (+) Resume the time base source interrupt - (+) Get the HAL API driver version - (+) Get the device identifier - (+) Get the device revision identifier - (+) Enable/Disable Debug module during SLEEP mode - (+) Enable/Disable Debug module during STOP mode - (+) Enable/Disable Debug module during STANDBY mode - -@endverbatim - * @{ - */ - -/** - * @brief This function is called to increment a global variable "uwTick" - * used as application time base. - * @note In the default implementation, this variable is incremented each 1ms - * in Systick ISR. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_IncTick(void) -{ - uwTick++; -} - -/** - * @brief Provides a tick value in millisecond. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval tick value - */ -__weak uint32_t HAL_GetTick(void) -{ - return uwTick; -} - -/** - * @brief This function provides accurate delay (in milliseconds) based - * on variable incremented. - * @note In the default implementation , SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals where uwTick - * is incremented. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @param Delay: specifies the delay time length, in milliseconds. - * @retval None - */ -__weak void HAL_Delay(__IO uint32_t Delay) -{ - uint32_t tickstart = 0; - tickstart = HAL_GetTick(); - while((HAL_GetTick() - tickstart) < Delay) - { - } -} - -/** - * @brief Suspend Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() - * is called, the SysTick interrupt will be disabled and so Tick increment - * is suspended. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_SuspendTick(void) -{ - /* Disable SysTick Interrupt */ - SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; -} - -/** - * @brief Resume Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() - * is called, the SysTick interrupt will be enabled and so Tick increment - * is resumed. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_ResumeTick(void) -{ - /* Enable SysTick Interrupt */ - SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; -} - -/** - * @brief Returns the HAL revision - * @retval version : 0xXYZR (8bits for each decimal, R for RC) - */ -uint32_t HAL_GetHalVersion(void) -{ - return __STM32F7xx_HAL_VERSION; -} - -/** - * @brief Returns the device revision identifier. - * @retval Device revision identifier - */ -uint32_t HAL_GetREVID(void) -{ - return((DBGMCU->IDCODE) >> 16U); -} - -/** - * @brief Returns the device identifier. - * @retval Device identifier - */ -uint32_t HAL_GetDEVID(void) -{ - return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); -} - -/** - * @brief Enable the Debug Module during SLEEP mode - * @retval None - */ -void HAL_DBGMCU_EnableDBGSleepMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Disable the Debug Module during SLEEP mode - * @retval None - */ -void HAL_DBGMCU_DisableDBGSleepMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Enable the Debug Module during STOP mode - * @retval None - */ -void HAL_DBGMCU_EnableDBGStopMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Disable the Debug Module during STOP mode - * @retval None - */ -void HAL_DBGMCU_DisableDBGStopMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Enable the Debug Module during STANDBY mode - * @retval None - */ -void HAL_DBGMCU_EnableDBGStandbyMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Disable the Debug Module during STANDBY mode - * @retval None - */ -void HAL_DBGMCU_DisableDBGStandbyMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Enables the I/O Compensation Cell. - * @note The I/O compensation cell can be used only when the device supply - * voltage ranges from 2.4 to 3.6 V. - * @retval None - */ -void HAL_EnableCompensationCell(void) -{ - SYSCFG->CMPCR |= SYSCFG_CMPCR_CMP_PD; -} - -/** - * @brief Power-down the I/O Compensation Cell. - * @note The I/O compensation cell can be used only when the device supply - * voltage ranges from 2.4 to 3.6 V. - * @retval None - */ -void HAL_DisableCompensationCell(void) -{ - SYSCFG->CMPCR &= (uint32_t)~((uint32_t)SYSCFG_CMPCR_CMP_PD); -} - -/** - * @brief Enables the FMC Memory Mapping Swapping. - * - * @note SDRAM is accessible at 0x60000000 - * and NOR/RAM is accessible at 0xC0000000 - * - * @retval None - */ -void HAL_EnableFMCMemorySwapping(void) -{ - SYSCFG->MEMRMP |= SYSCFG_MEMRMP_SWP_FMC_0; -} - -/** - * @brief Disables the FMC Memory Mapping Swapping - * - * @note SDRAM is accessible at 0xC0000000 (default mapping) - * and NOR/RAM is accessible at 0x60000000 (default mapping) - * - * @retval None - */ -void HAL_DisableFMCMemorySwapping(void) -{ - - SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC); -} - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -/** -* @brief Enable the Internal FLASH Bank Swapping. -* -* @note This function can be used only for STM32F77xx/STM32F76xx devices. -* -* @note Flash Bank2 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) -* and Flash Bank1 mapped at 0x08100000 (AXI) (aliased at 0x00300000 (TCM)) -* -* @retval None -*/ -void HAL_EnableMemorySwappingBank(void) -{ - SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB); -} - -/** -* @brief Disable the Internal FLASH Bank Swapping. -* -* @note This function can be used only for STM32F77xx/STM32F76xx devices. -* -* @note The default state : Flash Bank1 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) -* and Flash Bank2 mapped at 0x08100000 (AXI)( aliased at 0x00300000 (TCM)) -* -* @retval None -*/ -void HAL_DisableMemorySwappingBank(void) -{ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB); -} -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c deleted file mode 100644 index fe398db..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c +++ /dev/null @@ -1,1686 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_adc.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + State and errors functions - * - @verbatim - ============================================================================== - ##### ADC Peripheral features ##### - ============================================================================== - [..] - (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. - (#) Interrupt generation at the end of conversion, end of injected conversion, - and in case of analog watchdog or overrun events - (#) Single and continuous conversion modes. - (#) Scan mode for automatic conversion of channel 0 to channel x. - (#) Data alignment with in-built data coherency. - (#) Channel-wise programmable sampling time. - (#) External trigger option with configurable polarity for both regular and - injected conversion. - (#) Dual/Triple mode (on devices with 2 ADCs or more). - (#) Configurable DMA data storage in Dual/Triple ADC mode. - (#) Configurable delay between conversions in Dual/Triple interleaved mode. - (#) ADC conversion type (refer to the datasheets). - (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at - slower speed. - (#) ADC input range: VREF(minus) = VIN = VREF(plus). - (#) DMA request generation during regular channel conversion. - - - ##### How to use this driver ##### - ============================================================================== - [..] - (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit(): - (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE() - (##) ADC pins configuration - (+++) Enable the clock for the ADC GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE() - (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() - (##) In case of using interrupts (e.g. HAL_ADC_Start_IT()) - (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority() - (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ() - (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler() - (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA()) - (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE() - (+++) Configure and enable two DMA streams stream for managing data - transfer from peripheral to memory (output stream) - (+++) Associate the initialized DMA handle to the CRYP DMA handle - using __HAL_LINKDMA() - (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the two DMA Streams. The output stream should have higher - priority than the input stream. - - *** Configuration of ADC, groups regular/injected, channels parameters *** - ============================================================================== - [..] - (#) Configure the ADC parameters (resolution, data alignment, ...) - and regular group parameters (conversion trigger, sequencer, ...) - using function HAL_ADC_Init(). - - (#) Configure the channels for regular group parameters (channel number, - channel rank into sequencer, ..., into regular group) - using function HAL_ADC_ConfigChannel(). - - (#) Optionally, configure the injected group parameters (conversion trigger, - sequencer, ..., of injected group) - and the channels for injected group parameters (channel number, - channel rank into sequencer, ..., into injected group) - using function HAL_ADCEx_InjectedConfigChannel(). - - (#) Optionally, configure the analog watchdog parameters (channels - monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig(). - - (#) Optionally, for devices with several ADC instances: configure the - multimode parameters using function HAL_ADCEx_MultiModeConfigChannel(). - - *** Execution of ADC conversions *** - ============================================================================== - [..] - (#) ADC driver can be used among three modes: polling, interruption, - transfer by DMA. - - *** Polling mode IO operation *** - ================================= - [..] - (+) Start the ADC peripheral using HAL_ADC_Start() - (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage - user can specify the value of timeout according to his end application - (+) To read the ADC converted values, use the HAL_ADC_GetValue() function. - (+) Stop the ADC peripheral using HAL_ADC_Stop() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Start the ADC peripheral using HAL_ADC_Start_IT() - (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine - (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADC_ConvCpltCallback - (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADC_ErrorCallback - (+) Stop the ADC peripheral using HAL_ADC_Stop_IT() - - *** DMA mode IO operation *** - ============================== - [..] - (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length - of data to be transferred at each end of conversion - (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADC_ConvCpltCallback - (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADC_ErrorCallback - (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA() - - *** ADC HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in ADC HAL driver. - - (+) __HAL_ADC_ENABLE : Enable the ADC peripheral - (+) __HAL_ADC_DISABLE : Disable the ADC peripheral - (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt - (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt - (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled - (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags - (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status - (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register - - [..] - (@) You can refer to the ADC HAL driver header file for more useful macros - - *** Deinitialization of ADC *** - ============================================================================== - [..] - (#) Disable the ADC interface - (++) ADC clock can be hard reset and disabled at RCC top level. - (++) Hard reset of ADC peripherals - using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET(). - (++) ADC clock disable using the equivalent macro/functions as configuration step. - (+++) Example: - Into HAL_ADC_MspDeInit() (recommended code location) or with - other device clock parameters configuration: - (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure); - (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI; - (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock) - (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); - - (#) ADC pins configuration - (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE() - - (#) Optionally, in case of usage of ADC with interruptions: - (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn) - - (#) Optionally, in case of usage of DMA: - (++) Deinitialize the DMA using function HAL_DMA_DeInit(). - (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn) - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup ADC ADC - * @brief ADC driver modules - * @{ - */ - -#ifdef HAL_ADC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @addtogroup ADC_Private_Functions - * @{ - */ -/* Private function prototypes -----------------------------------------------*/ -static void ADC_Init(ADC_HandleTypeDef* hadc); -static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); -static void ADC_DMAError(DMA_HandleTypeDef *hdma); -static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup ADC_Exported_Functions ADC Exported Functions - * @{ - */ - -/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the ADC. - (+) De-initialize the ADC. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct and initializes the ADC MSP. - * - * @note This function is used to configure the global features of the ADC ( - * ClockPrescaler, Resolution, Data Alignment and number of conversion), however, - * the rest of the configuration parameters are specific to the regular - * channels group (scan mode activation, continuous mode activation, - * External trigger source and edge, DMA continuous request after the - * last transfer and End of conversion selection). - * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check ADC handle */ - if(hadc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); - assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv)); - assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); - assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); - assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); - - if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) - { - assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); - } - - if(hadc->State == HAL_ADC_STATE_RESET) - { - /* Initialize ADC error code */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Allocate lock resource and initialize it */ - hadc->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ - HAL_ADC_MspInit(hadc); - } - - /* Configuration of ADC parameters if previous preliminary actions are */ - /* correctly completed. */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_BUSY_INTERNAL); - - /* Set ADC parameters */ - ADC_Init(hadc); - - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Set the ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_READY); - } - else - { - tmp_hal_status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Deinitializes the ADCx peripheral registers to their default reset values. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check ADC handle */ - if(hadc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); - - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - __HAL_ADC_DISABLE(hadc); - - /* Configuration of ADC parameters if previous preliminary actions are */ - /* correctly completed. */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* DeInit the low level hardware */ - HAL_ADC_MspDeInit(hadc); - - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Set ADC state */ - hadc->State = HAL_ADC_STATE_RESET; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Initializes the ADC MSP. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval None - */ -__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ADC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the ADC MSP. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval None - */ -__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ADC_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Start conversion of regular channel. - (+) Stop conversion of regular channel. - (+) Start conversion of regular channel and enable interrupt. - (+) Stop conversion of regular channel and disable interrupt. - (+) Start conversion of regular channel and enable DMA transfer. - (+) Stop conversion of regular channel and disable DMA transfer. - (+) Handle ADC interrupt request. - -@endverbatim - * @{ - */ - -/** - * @brief Enables ADC and starts conversion of the regular channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) -{ - __IO uint32_t counter = 0; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - /* Check if ADC peripheral is disabled in order to enable it and wait during - Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) - { - /* Enable the Peripheral */ - __HAL_ADC_ENABLE(hadc); - - /* Delay for ADC stabilization time */ - /* Compute number of CPU cycles to wait for */ - counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); - while(counter != 0) - { - counter--; - } - } - - /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular group operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, - HAL_ADC_STATE_REG_BUSY); - - /* If conversions on group regular are also triggering group injected, */ - /* update ADC state. */ - if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - } - - /* State machine update: Check if an injected conversion is ongoing */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - /* Reset ADC error code fields related to conversions on group regular */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); - } - else - { - /* Reset ADC all error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Clear regular group conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); - - /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) - { - /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) - { - /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; - } - } - else - { - /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ - if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) - { - /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; - } - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Disables ADC and stop conversion of regular channels. - * - * @note Caution: This function will stop also injected channels. - * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - __HAL_ADC_DISABLE(hadc); - - /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Poll for regular conversion complete - * @note ADC conversion flags EOS (end of sequence) and EOC (end of - * conversion) are cleared by this function. - * @note This function cannot be used in a particular setup: ADC configured - * in DMA mode and polling for end of each conversion (ADC init - * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). - * In this case, DMA resets the flag EOC and polling cannot be - * performed on each conversion. Nevertheless, polling can still - * be performed on the complete sequence. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param Timeout: Timeout value in millisecond. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Verification that ADC configuration is compliant with polling for */ - /* each conversion: */ - /* Particular case is ADC configured in DMA mode and ADC sequencer with */ - /* several ranks and polling for end of each conversion. */ - /* For code simplicity sake, this particular case is generalized to */ - /* ADC configured in DMA mode and polling for end of each conversion. */ - if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) && - HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check End of conversion flag */ - while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) - { - /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_TIMEOUT; - } - } - } - - /* Clear regular group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); - - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - - /* Determine whether any further conversion upcoming on group regular */ - /* by external trigger, continuous mode or scan sequence on going. */ - /* Note: On STM32F7, there is no independent flag of end of sequence. */ - /* The test of scan sequence on going is done either with scan */ - /* sequence disabled or with end of conversion flag set to */ - /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) && - (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) - { - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - - /* Return ADC state */ - return HAL_OK; -} - -/** - * @brief Poll for conversion event - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param EventType: the ADC event type. - * This parameter can be one of the following values: - * @arg ADC_AWD_EVENT: ADC Analog watch Dog event. - * @arg ADC_OVR_EVENT: ADC Overrun event. - * @param Timeout: Timeout value in millisecond. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_EVENT_TYPE(EventType)); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check selected event flag */ - while(!(__HAL_ADC_GET_FLAG(hadc,EventType))) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_TIMEOUT; - } - } - } - - /* Analog watchdog (level out of window) event */ - if(EventType == ADC_AWD_EVENT) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); - } - /* Overrun event */ - else - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); - /* Set ADC error code to overrun */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - - /* Clear ADC overrun flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - } - - /* Return ADC state */ - return HAL_OK; -} - - -/** - * @brief Enables the interrupt and starts ADC conversion of regular channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) -{ - __IO uint32_t counter = 0; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - /* Check if ADC peripheral is disabled in order to enable it and wait during - Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) - { - /* Enable the Peripheral */ - __HAL_ADC_ENABLE(hadc); - - /* Delay for ADC stabilization time */ - /* Compute number of CPU cycles to wait for */ - counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); - while(counter != 0) - { - counter--; - } - } - - /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular group operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, - HAL_ADC_STATE_REG_BUSY); - - /* If conversions on group regular are also triggering group injected, */ - /* update ADC state. */ - if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - } - - /* State machine update: Check if an injected conversion is ongoing */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - /* Reset ADC error code fields related to conversions on group regular */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); - } - else - { - /* Reset ADC all error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Clear regular group conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); - - /* Enable end of conversion interrupt for regular group */ - __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); - - /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) - { - /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) - { - /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; - } - } - else - { - /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ - if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) - { - /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; - } - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Disables the interrupt and stop ADC conversion of regular channels. - * - * @note Caution: This function will stop also injected channels. - * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - __HAL_ADC_DISABLE(hadc); - - /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Disable ADC end of conversion interrupt for regular group */ - __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); - - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Handles ADC interrupt request - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval None - */ -void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) -{ - uint32_t tmp1 = 0, tmp2 = 0; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); - assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); - - tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC); - tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC); - /* Check End of conversion flag for regular channels */ - if(tmp1 && tmp2) - { - /* Update state machine on conversion status if not in error state */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - } - - /* Determine whether any further conversion upcoming on group regular */ - /* by external trigger, continuous mode or scan sequence on going. */ - /* Note: On STM32F7, there is no independent flag of end of sequence. */ - /* The test of scan sequence on going is done either with scan */ - /* sequence disabled or with end of conversion flag set to */ - /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) && - (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) - { - /* Disable ADC end of single conversion interrupt on group regular */ - /* Note: Overrun interrupt was enabled with EOC interrupt in */ - /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ - /* by overrun IRQ process below. */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); - - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - - /* Conversion complete callback */ - HAL_ADC_ConvCpltCallback(hadc); - - /* Clear regular group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); - } - - tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC); - tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC); - /* Check End of conversion flag for injected channels */ - if(tmp1 && tmp2) - { - /* Update state machine on conversion status if not in error state */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); - } - - /* Determine whether any further conversion upcoming on group injected */ - /* by external trigger, scan sequence on going or by automatic injected */ - /* conversion from group regular (same conditions as group regular */ - /* interruption disabling above). */ - if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && - (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) && - (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && - (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE)))) - { - /* Disable ADC end of single conversion interrupt on group injected */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); - - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - - /* Conversion complete callback */ - HAL_ADCEx_InjectedConvCpltCallback(hadc); - - /* Clear injected group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); - } - - tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD); - tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD); - /* Check Analog watchdog flag */ - if(tmp1 && tmp2) - { - if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - - /* Level out of window callback */ - HAL_ADC_LevelOutOfWindowCallback(hadc); - - /* Clear the ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); - } - } - - tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR); - tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR); - /* Check Overrun flag */ - if(tmp1 && tmp2) - { - /* Note: On STM32F7, ADC overrun can be set through other parameters */ - /* refer to description of parameter "EOCSelection" for more */ - /* details. */ - - /* Set ADC error code to overrun */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - - /* Clear ADC overrun flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - - /* Error callback */ - HAL_ADC_ErrorCallback(hadc); - - /* Clear the Overrun flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - } -} - -/** - * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from ADC peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) -{ - __IO uint32_t counter = 0; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - /* Check if ADC peripheral is disabled in order to enable it and wait during - Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) - { - /* Enable the Peripheral */ - __HAL_ADC_ENABLE(hadc); - - /* Delay for ADC stabilization time */ - /* Compute number of CPU cycles to wait for */ - counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); - while(counter != 0) - { - counter--; - } - } - - /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular group operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, - HAL_ADC_STATE_REG_BUSY); - - /* If conversions on group regular are also triggering group injected, */ - /* update ADC state. */ - if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - } - - /* State machine update: Check if an injected conversion is ongoing */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - /* Reset ADC error code fields related to conversions on group regular */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); - } - else - { - /* Reset ADC all error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Set the DMA transfer complete callback */ - hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; - - /* Set the DMA half transfer complete callback */ - hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; - - /* Set the DMA error callback */ - hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; - - - /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ - /* start (in case of SW start): */ - - /* Clear regular group conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); - - /* Enable ADC overrun interrupt */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - - /* Enable ADC DMA mode */ - hadc->Instance->CR2 |= ADC_CR2_DMA; - - /* Start the DMA channel */ - HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); - - /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) - { - /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) - { - /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; - } - } - else - { - /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ - if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) - { - /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; - } - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - __HAL_ADC_DISABLE(hadc); - - /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Disable the selected ADC DMA mode */ - hadc->Instance->CR2 &= ~ADC_CR2_DMA; - - /* Disable the DMA channel (in case of DMA in circular mode or stop while */ - /* DMA transfer is on going) */ - tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - - /* Disable ADC overrun interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Gets the converted value from data register of regular channel. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval Converted value - */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) -{ - /* Return the selected ADC converted value */ - return hadc->Instance->DR; -} - -/** - * @brief Regular conversion complete callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval None - */ -__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ADC_ConvCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Regular conversion half DMA transfer callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval None - */ -__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Analog watchdog callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval None - */ -__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file - */ -} - -/** - * @brief Error ADC callback. - * @note In case of error due to overrun when using ADC with DMA transfer - * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"): - * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". - * - If needed, restart a new ADC conversion using function - * "HAL_ADC_Start_DMA()" - * (this function is also clearing overrun flag) - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval None - */ -__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ADC_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure regular channels. - (+) Configure injected channels. - (+) Configure multimode. - (+) Configure the analog watch dog. - -@endverbatim - * @{ - */ - - /** - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param sConfig: ADC configuration structure. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) -{ - __IO uint32_t counter = 0; - - /* Check the parameters */ - assert_param(IS_ADC_CHANNEL(sConfig->Channel)); - assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); - assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ - if (sConfig->Channel > ADC_CHANNEL_9) - { - /* Clear the old sample time */ - hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel); - - if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) - { - /* Set the new sample time */ - hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18); - } - else - { - /* Set the new sample time */ - hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel); - } - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Clear the old sample time */ - hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel); - - /* Set the new sample time */ - hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel); - } - - /* For Rank 1 to 6 */ - if (sConfig->Rank < 7) - { - /* Clear the old SQx bits for the selected rank */ - hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank); - - /* Set the SQx bits for the selected rank */ - hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank); - } - /* For Rank 7 to 12 */ - else if (sConfig->Rank < 13) - { - /* Clear the old SQx bits for the selected rank */ - hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank); - - /* Set the SQx bits for the selected rank */ - hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank); - } - /* For Rank 13 to 16 */ - else - { - /* Clear the old SQx bits for the selected rank */ - hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank); - - /* Set the SQx bits for the selected rank */ - hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank); - } - - /* if ADC1 Channel_18 is selected enable VBAT Channel */ - if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT)) - { - /* Enable the VBAT channel*/ - ADC->CCR |= ADC_CCR_VBATE; - } - - /* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */ - if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT))) - { - /* Enable the TSVREFE channel*/ - ADC->CCR |= ADC_CCR_TSVREFE; - - if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) - { - /* Delay for temperature sensor stabilization time */ - /* Compute number of CPU cycles to wait for */ - counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); - while(counter != 0) - { - counter--; - } - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configures the analog watchdog. - * @note Analog watchdog thresholds can be modified while ADC conversion - * is on going. - * In this case, some constraints must be taken into account: - * the programmed threshold values are effective from the next - * ADC EOC (end of unitary conversion). - * Considering that registers write delay may happen due to - * bus activity, this might cause an uncertainty on the - * effective timing of the new programmed threshold values. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure - * that contains the configuration information of ADC analog watchdog. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) -{ -#ifdef USE_FULL_ASSERT - uint32_t tmp = 0; -#endif /* USE_FULL_ASSERT */ - - /* Check the parameters */ - assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode)); - assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); - assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); - -#ifdef USE_FULL_ASSERT - tmp = ADC_GET_RESOLUTION(hadc); - assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold)); - assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold)); -#endif /* USE_FULL_ASSERT */ - - /* Process locked */ - __HAL_LOCK(hadc); - - if(AnalogWDGConfig->ITMode == ENABLE) - { - /* Enable the ADC Analog watchdog interrupt */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); - } - else - { - /* Disable the ADC Analog watchdog interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); - } - - /* Clear AWDEN, JAWDEN and AWDSGL bits */ - hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN); - - /* Set the analog watchdog enable mode */ - hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode; - - /* Set the high threshold */ - hadc->Instance->HTR = AnalogWDGConfig->HighThreshold; - - /* Set the low threshold */ - hadc->Instance->LTR = AnalogWDGConfig->LowThreshold; - - /* Clear the Analog watchdog channel select bits */ - hadc->Instance->CR1 &= ~ADC_CR1_AWDCH; - - /* Set the Analog watchdog channel */ - hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel)); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions - * @brief ADC Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State and errors functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the ADC state - (+) Check the ADC Error - -@endverbatim - * @{ - */ - -/** - * @brief return the ADC state - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval HAL state - */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) -{ - /* Return ADC state */ - return hadc->State; -} - -/** - * @brief Return the ADC error code - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval ADC Error Code - */ -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) -{ - return hadc->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup ADC_Private_Functions ADC Private Functions - * @{ - */ - -/** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct without initializing the ADC MSP. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval None - */ -static void ADC_Init(ADC_HandleTypeDef* hadc) -{ - /* Set ADC parameters */ - /* Set the ADC clock prescaler */ - ADC->CCR &= ~(ADC_CCR_ADCPRE); - ADC->CCR |= hadc->Init.ClockPrescaler; - - /* Set ADC scan mode */ - hadc->Instance->CR1 &= ~(ADC_CR1_SCAN); - hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode); - - /* Set ADC resolution */ - hadc->Instance->CR1 &= ~(ADC_CR1_RES); - hadc->Instance->CR1 |= hadc->Init.Resolution; - - /* Set ADC data alignment */ - hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN); - hadc->Instance->CR2 |= hadc->Init.DataAlign; - - /* Enable external trigger if trigger selection is different of software */ - /* start. */ - /* Note: This configuration keeps the hardware feature of parameter */ - /* ExternalTrigConvEdge "trigger edge none" equivalent to */ - /* software start. */ - if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) - { - /* Select external trigger to start conversion */ - hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); - hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv; - - /* Select external trigger polarity */ - hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); - hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge; - } - else - { - /* Reset the external trigger */ - hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); - hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); - } - - /* Enable or disable ADC continuous conversion mode */ - hadc->Instance->CR2 &= ~(ADC_CR2_CONT); - hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode); - - if(hadc->Init.DiscontinuousConvMode != DISABLE) - { - assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion)); - - /* Enable the selected ADC regular discontinuous mode */ - hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN; - - /* Set the number of channels to be converted in discontinuous mode */ - hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM); - hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion); - } - else - { - /* Disable the selected ADC regular discontinuous mode */ - hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN); - } - - /* Set ADC number of conversion */ - hadc->Instance->SQR1 &= ~(ADC_SQR1_L); - hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion); - - /* Enable or disable ADC DMA continuous request */ - hadc->Instance->CR2 &= ~(ADC_CR2_DDS); - hadc->Instance->CR2 |= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests); - - /* Enable or disable ADC end of conversion selection */ - hadc->Instance->CR2 &= ~(ADC_CR2_EOCS); - hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection); -} - -/** - * @brief DMA transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Update state machine on conversion status if not in error state */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) - { - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - - /* Determine whether any further conversion upcoming on group regular */ - /* by external trigger, continuous mode or scan sequence on going. */ - /* Note: On STM32F7, there is no independent flag of end of sequence. */ - /* The test of scan sequence on going is done either with scan */ - /* sequence disabled or with end of conversion flag set to */ - /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) && - (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) - { - /* Disable ADC end of single conversion interrupt on group regular */ - /* Note: Overrun interrupt was enabled with EOC interrupt in */ - /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ - /* by overrun IRQ process below. */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); - - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - - /* Conversion complete callback */ - HAL_ADC_ConvCpltCallback(hadc); - } - else - { - /* Call DMA error callback */ - hadc->DMA_Handle->XferErrorCallback(hdma); - } -} - -/** - * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) -{ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Conversion complete callback */ - HAL_ADC_ConvHalfCpltCallback(hadc); -} - -/** - * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void ADC_DMAError(DMA_HandleTypeDef *hdma) -{ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hadc->State= HAL_ADC_STATE_ERROR_DMA; - /* Set ADC error code to DMA error */ - hadc->ErrorCode |= HAL_ADC_ERROR_DMA; - HAL_ADC_ErrorCallback(hadc); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_ADC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c deleted file mode 100644 index 88dd329..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c +++ /dev/null @@ -1,1069 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_adc_ex.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the ADC extension peripheral: - * + Extended features functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit(): - (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE() - (##) ADC pins configuration - (+++) Enable the clock for the ADC GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE() - (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() - (##) In case of using interrupts (e.g. HAL_ADC_Start_IT()) - (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority() - (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ() - (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler() - (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA()) - (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE() - (+++) Configure and enable two DMA streams stream for managing data - transfer from peripheral to memory (output stream) - (+++) Associate the initialized DMA handle to the ADC DMA handle - using __HAL_LINKDMA() - (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the two DMA Streams. The output stream should have higher - priority than the input stream. - (#) Configure the ADC Prescaler, conversion resolution and data alignment - using the HAL_ADC_Init() function. - - (#) Configure the ADC Injected channels group features, use HAL_ADC_Init() - and HAL_ADC_ConfigChannel() functions. - - (#) Three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart() - (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage - user can specify the value of timeout according to his end application - (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function. - (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT() - (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine - (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback - (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback - (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT() - - - *** DMA mode IO operation *** - ============================== - [..] - (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length - of data to be transferred at each end of conversion - (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback - (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback - (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA() - - *** Multi mode ADCs Regular channels configuration *** - ====================================================== - [..] - (+) Select the Multi mode ADC regular channels features (dual or triple mode) - and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions. - (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length - of data to be transferred at each end of conversion - (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function. - - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup ADCEx ADCEx - * @brief ADC Extended driver modules - * @{ - */ - -#ifdef HAL_ADC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @addtogroup ADCEx_Private_Functions - * @{ - */ -/* Private function prototypes -----------------------------------------------*/ -static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma); -static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma); -static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup ADCEx_Exported_Functions ADC Exported Functions - * @{ - */ - -/** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Start conversion of injected channel. - (+) Stop conversion of injected channel. - (+) Start multimode and enable DMA transfer. - (+) Stop multimode and disable DMA transfer. - (+) Get result of injected channel conversion. - (+) Get result of multimode conversion. - (+) Configure injected channels. - (+) Configure multimode. - -@endverbatim - * @{ - */ - -/** - * @brief Enables the selected ADC software start conversion of the injected channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) -{ - __IO uint32_t counter = 0; - uint32_t tmp1 = 0, tmp2 = 0; - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - - /* Check if ADC peripheral is disabled in order to enable it and wait during - Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) - { - /* Enable the Peripheral */ - __HAL_ADC_ENABLE(hadc); - - /* Delay for ADC stabilization time */ - /* Compute number of CPU cycles to wait for */ - counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); - while(counter != 0) - { - counter--; - } - } - - /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Set ADC state */ - /* - Clear state bitfield related to injected group conversion results */ - /* - Set state bitfield related to injected operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, - HAL_ADC_STATE_INJ_BUSY); - - /* Check if a regular conversion is ongoing */ - /* Note: On this device, there is no ADC error code fields related to */ - /* conversions on group injected only. In case of conversion on */ - /* going on group regular, no error code is reset. */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - { - /* Reset ADC all error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Clear injected group conversion flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); - - /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) - { - tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); - tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if(tmp1 && tmp2) - { - /* Enable the selected ADC software conversion for injected group */ - hadc->Instance->CR2 |= ADC_CR2_JSWSTART; - } - } - else - { - tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); - tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if((hadc->Instance == ADC1) && tmp1 && tmp2) - { - /* Enable the selected ADC software conversion for injected group */ - hadc->Instance->CR2 |= ADC_CR2_JSWSTART; - } - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Enables the interrupt and starts ADC conversion of injected channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) -{ - __IO uint32_t counter = 0; - uint32_t tmp1 = 0, tmp2 = 0; - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - - /* Check if ADC peripheral is disabled in order to enable it and wait during - Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) - { - /* Enable the Peripheral */ - __HAL_ADC_ENABLE(hadc); - - /* Delay for ADC stabilization time */ - /* Compute number of CPU cycles to wait for */ - counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); - while(counter != 0) - { - counter--; - } - } - - /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Set ADC state */ - /* - Clear state bitfield related to injected group conversion results */ - /* - Set state bitfield related to injected operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, - HAL_ADC_STATE_INJ_BUSY); - - /* Check if a regular conversion is ongoing */ - /* Note: On this device, there is no ADC error code fields related to */ - /* conversions on group injected only. In case of conversion on */ - /* going on group regular, no error code is reset. */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - { - /* Reset ADC all error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Clear injected group conversion flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); - - /* Enable end of conversion interrupt for injected channels */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); - - /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) - { - tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); - tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if(tmp1 && tmp2) - { - /* Enable the selected ADC software conversion for injected group */ - hadc->Instance->CR2 |= ADC_CR2_JSWSTART; - } - } - else - { - tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); - tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if((hadc->Instance == ADC1) && tmp1 && tmp2) - { - /* Enable the selected ADC software conversion for injected group */ - hadc->Instance->CR2 |= ADC_CR2_JSWSTART; - } - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop conversion of injected channels. Disable ADC peripheral if - * no regular conversion is on going. - * @note If ADC must be disabled and if conversion is on going on - * regular group, function HAL_ADC_Stop must be used to stop both - * injected and regular groups, and disable the ADC. - * @note If injected group mode auto-injection is enabled, - * function HAL_ADC_Stop must be used. - * @note In case of auto-injection mode, HAL_ADC_Stop must be used. - * @param hadc: ADC handle - * @retval None - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion and disable ADC peripheral */ - /* Conditioned to: */ - /* - No conversion on the other group (regular group) is intended to */ - /* continue (injected and regular groups stop conversion and ADC disable */ - /* are common) */ - /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ - if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && - HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) - { - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - __HAL_ADC_DISABLE(hadc); - - /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Poll for injected conversion complete - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param Timeout: Timeout value in millisecond. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check End of conversion flag */ - while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hadc->State= HAL_ADC_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; - } - } - } - - /* Clear injected group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC); - - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); - - /* Determine whether any further conversion upcoming on group injected */ - /* by external trigger, continuous mode or scan sequence on going. */ - /* Note: On STM32F7, there is no independent flag of end of sequence. */ - /* The test of scan sequence on going is done either with scan */ - /* sequence disabled or with end of conversion flag set to */ - /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && - (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && - (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && - (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) - { - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - - /* Return ADC state */ - return HAL_OK; -} - -/** - * @brief Stop conversion of injected channels, disable interruption of - * end-of-conversion. Disable ADC peripheral if no regular conversion - * is on going. - * @note If ADC must be disabled and if conversion is on going on - * regular group, function HAL_ADC_Stop must be used to stop both - * injected and regular groups, and disable the ADC. - * @note If injected group mode auto-injection is enabled, - * function HAL_ADC_Stop must be used. - * @param hadc: ADC handle - * @retval None - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion and disable ADC peripheral */ - /* Conditioned to: */ - /* - No conversion on the other group (regular group) is intended to */ - /* continue (injected and regular groups stop conversion and ADC disable */ - /* are common) */ - /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ - if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && - HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) - { - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - __HAL_ADC_DISABLE(hadc); - - /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Disable ADC end of conversion interrupt for injected channels */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); - - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Gets the converted value from data register of injected channel. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param InjectedRank: the ADC injected rank. - * This parameter can be one of the following values: - * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected - * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected - * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected - * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected - * @retval None - */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); - - /* Clear injected group conversion flag to have similar behaviour as */ - /* regular group: reading data register also clears end of conversion flag. */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); - - /* Return the selected ADC converted value */ - switch(InjectedRank) - { - case ADC_INJECTED_RANK_4: - { - tmp = hadc->Instance->JDR4; - } - break; - case ADC_INJECTED_RANK_3: - { - tmp = hadc->Instance->JDR3; - } - break; - case ADC_INJECTED_RANK_2: - { - tmp = hadc->Instance->JDR2; - } - break; - case ADC_INJECTED_RANK_1: - { - tmp = hadc->Instance->JDR1; - } - break; - default: - break; - } - return tmp; -} - -/** - * @brief Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral - * - * @note Caution: This function must be used only with the ADC master. - * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param pData: Pointer to buffer in which transferred from ADC peripheral to memory will be stored. - * @param Length: The length of data to be transferred from ADC peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) -{ - __IO uint32_t counter = 0; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Check if ADC peripheral is disabled in order to enable it and wait during - Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) - { - /* Enable the Peripheral */ - __HAL_ADC_ENABLE(hadc); - - /* Delay for temperature sensor stabilization time */ - /* Compute number of CPU cycles to wait for */ - counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); - while(counter != 0) - { - counter--; - } - } - - /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular group operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, - HAL_ADC_STATE_REG_BUSY); - - /* If conversions on group regular are also triggering group injected, */ - /* update ADC state. */ - if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - } - - /* State machine update: Check if an injected conversion is ongoing */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - /* Reset ADC error code fields related to conversions on group regular */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); - } - else - { - /* Reset ADC all error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Set the DMA transfer complete callback */ - hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt; - - /* Set the DMA half transfer complete callback */ - hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt; - - /* Set the DMA error callback */ - hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ; - - /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ - /* start (in case of SW start): */ - - /* Clear regular group conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); - - /* Enable ADC overrun interrupt */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - - if (hadc->Init.DMAContinuousRequests != DISABLE) - { - /* Enable the selected ADC DMA request after last transfer */ - ADC->CCR |= ADC_CCR_DDS; - } - else - { - /* Disable the selected ADC EOC rising on each regular channel conversion */ - ADC->CCR &= ~ADC_CCR_DDS; - } - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length); - - /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) - { - /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - __HAL_ADC_DISABLE(hadc); - - /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Disable the selected ADC DMA mode for multimode */ - ADC->CCR &= ~ADC_CCR_DDS; - - /* Disable the DMA channel (in case of DMA in circular mode or stop while */ - /* DMA transfer is on going) */ - tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - - /* Disable ADC overrun interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results - * data in the selected multi mode. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval The converted data value. - */ -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) -{ - /* Return the multi mode conversion value */ - return ADC->CDR; -} - -/** - * @brief Injected conversion complete callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval None - */ -__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param sConfigInjected: ADC configuration structure for injected channel. - * @retval None - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) -{ - -#ifdef USE_FULL_ASSERT - uint32_t tmp = 0; -#endif /* USE_FULL_ASSERT */ - - /* Check the parameters */ - assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); - assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); - assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); - assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv)); - assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); - -#ifdef USE_FULL_ASSERT - tmp = ADC_GET_RESOLUTION(hadc); - assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset)); -#endif /* USE_FULL_ASSERT */ - - if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START) - { - assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); - } - - /* Process locked */ - __HAL_LOCK(hadc); - - /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ - if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9) - { - /* Clear the old sample time */ - hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel); - - /* Set the new sample time */ - hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Clear the old sample time */ - hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel); - - /* Set the new sample time */ - hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); - } - - /*---------------------------- ADCx JSQR Configuration -----------------*/ - hadc->Instance->JSQR &= ~(ADC_JSQR_JL); - hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion); - - /* Rank configuration */ - - /* Clear the old SQx bits for the selected rank */ - hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); - - /* Set the SQx bits for the selected rank */ - hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); - - /* Enable external trigger if trigger selection is different of software */ - /* start. */ - /* Note: This configuration keeps the hardware feature of parameter */ - /* ExternalTrigConvEdge "trigger edge none" equivalent to */ - /* software start. */ - if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) - { - /* Select external trigger to start conversion */ - hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); - hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv; - - /* Select external trigger polarity */ - hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); - hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge; - } - else - { - /* Reset the external trigger */ - hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); - hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); - } - - if (sConfigInjected->AutoInjectedConv != DISABLE) - { - /* Enable the selected ADC automatic injected group conversion */ - hadc->Instance->CR1 |= ADC_CR1_JAUTO; - } - else - { - /* Disable the selected ADC automatic injected group conversion */ - hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO); - } - - if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE) - { - /* Enable the selected ADC injected discontinuous mode */ - hadc->Instance->CR1 |= ADC_CR1_JDISCEN; - } - else - { - /* Disable the selected ADC injected discontinuous mode */ - hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN); - } - - switch(sConfigInjected->InjectedRank) - { - case 1: - /* Set injected channel 1 offset */ - hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1); - hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset; - break; - case 2: - /* Set injected channel 2 offset */ - hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2); - hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset; - break; - case 3: - /* Set injected channel 3 offset */ - hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3); - hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset; - break; - default: - /* Set injected channel 4 offset */ - hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4); - hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset; - break; - } - - /* if ADC1 Channel_18 is selected enable VBAT Channel */ - if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)) - { - /* Enable the VBAT channel*/ - ADC->CCR |= ADC_CCR_VBATE; - } - - /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */ - if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT))) - { - /* Enable the TSVREFE channel*/ - ADC->CCR |= ADC_CCR_TSVREFE; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configures the ADC multi-mode - * @param hadc : pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param multimode : pointer to an ADC_MultiModeTypeDef structure that contains - * the configuration information for multimode. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) -{ - /* Check the parameters */ - assert_param(IS_ADC_MODE(multimode->Mode)); - assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode)); - assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Set ADC mode */ - ADC->CCR &= ~(ADC_CCR_MULTI); - ADC->CCR |= multimode->Mode; - - /* Set the ADC DMA access mode */ - ADC->CCR &= ~(ADC_CCR_DMA); - ADC->CCR |= multimode->DMAAccessMode; - - /* Set delay between two sampling phases */ - ADC->CCR &= ~(ADC_CCR_DELAY); - ADC->CCR |= multimode->TwoSamplingDelay; - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - - /** - * @brief DMA transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Update state machine on conversion status if not in error state */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) - { - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - - /* Determine whether any further conversion upcoming on group regular */ - /* by external trigger, continuous mode or scan sequence on going. */ - /* Note: On STM32F7, there is no independent flag of end of sequence. */ - /* The test of scan sequence on going is done either with scan */ - /* sequence disabled or with end of conversion flag set to */ - /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) && - (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) - { - /* Disable ADC end of single conversion interrupt on group regular */ - /* Note: Overrun interrupt was enabled with EOC interrupt in */ - /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ - /* by overrun IRQ process below. */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); - - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - - /* Conversion complete callback */ - HAL_ADC_ConvCpltCallback(hadc); - } - else - { - /* Call DMA error callback */ - hadc->DMA_Handle->XferErrorCallback(hdma); - } -} - -/** - * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) -{ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Conversion complete callback */ - HAL_ADC_ConvHalfCpltCallback(hadc); -} - -/** - * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma) -{ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hadc->State= HAL_ADC_STATE_ERROR_DMA; - /* Set ADC error code to DMA error */ - hadc->ErrorCode |= HAL_ADC_ERROR_DMA; - HAL_ADC_ErrorCallback(hadc); -} - -/** - * @} - */ - -#endif /* HAL_ADC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_can.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_can.c deleted file mode 100644 index efdabae..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_can.c +++ /dev/null @@ -1,1410 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_can.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief CAN HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Controller Area Network (CAN) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Error functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable the CAN controller interface clock using - __HAL_RCC_CAN1_CLK_ENABLE() for CAN1, __HAL_RCC_CAN2_CLK_ENABLE() for CAN2 - and __HAL_RCC_CAN3_CLK_ENABLE() for CAN3 - -@- In case you are using CAN2 only, you have to enable the CAN1 clock. - - (#) CAN pins configuration - (++) Enable the clock for the CAN GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE() - (++) Connect and configure the involved CAN pins to AF9 using the - following function HAL_GPIO_Init() - - (#) Initialize and configure the CAN using HAL_CAN_Init() function. - - (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function. - - (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function. - - (#) Receive a CAN frame using HAL_CAN_Receive() function. - - (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function. - - *** Polling mode IO operation *** - ================================= - [..] - (+) Start the CAN peripheral transmission and wait the end of this operation - using HAL_CAN_Transmit(), at this stage user can specify the value of timeout - according to his end application - (+) Start the CAN peripheral reception and wait the end of this operation - using HAL_CAN_Receive(), at this stage user can specify the value of timeout - according to his end application - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT() - (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() - (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine - (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_CAN_TxCpltCallback - (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_CAN_ErrorCallback - - *** CAN HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in CAN HAL driver. - - (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts - (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts - (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled - (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags - (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status - - [..] - (@) You can refer to the CAN HAL driver header file for more useful macros - - @endverbatim - - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup CAN CAN - * @brief CAN driver modules - * @{ - */ - -#ifdef HAL_CAN_MODULE_ENABLED - - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup CAN_Private_Constants - * @{ - */ -#define CAN_TIMEOUT_VALUE 10 -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup CAN_Private_Functions - * @{ - */ -static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber); -static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup CAN_Exported_Functions CAN Exported Functions - * @{ - */ - -/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the CAN. - (+) De-initialize the CAN. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) -{ - uint32_t InitStatus = CAN_INITSTATUS_FAILED; - uint32_t tickstart = 0; - - /* Check CAN handle */ - if(hcan == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP)); - assert_param(IS_CAN_MODE(hcan->Init.Mode)); - assert_param(IS_CAN_SJW(hcan->Init.SJW)); - assert_param(IS_CAN_BS1(hcan->Init.BS1)); - assert_param(IS_CAN_BS2(hcan->Init.BS2)); - assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); - - - if(hcan->State == HAL_CAN_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hcan->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ - HAL_CAN_MspInit(hcan); - } - - /* Initialize the CAN state*/ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Exit from sleep mode */ - hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP); - - /* Request initialisation */ - hcan->Instance->MCR |= CAN_MCR_INRQ ; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - - /* Check acknowledge */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - /* Set the time triggered communication mode */ - if (hcan->Init.TTCM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_TTCM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM; - } - - /* Set the automatic bus-off management */ - if (hcan->Init.ABOM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_ABOM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM; - } - - /* Set the automatic wake-up mode */ - if (hcan->Init.AWUM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_AWUM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM; - } - - /* Set the no automatic retransmission */ - if (hcan->Init.NART == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_NART; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART; - } - - /* Set the receive FIFO locked mode */ - if (hcan->Init.RFLM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_RFLM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM; - } - - /* Set the transmit FIFO priority */ - if (hcan->Init.TXFP == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_TXFP; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP; - } - - /* Set the bit timing register */ - hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \ - ((uint32_t)hcan->Init.SJW) | \ - ((uint32_t)hcan->Init.BS1) | \ - ((uint32_t)hcan->Init.BS2) | \ - ((uint32_t)hcan->Init.Prescaler - 1); - - /* Request leave initialisation */ - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - - /* Check acknowledged */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - InitStatus = CAN_INITSTATUS_SUCCESS; - } - } - - if(InitStatus == CAN_INITSTATUS_SUCCESS) - { - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Configures the CAN reception filter according to the specified - * parameters in the CAN_FilterInitStruct. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that - * contains the filter configuration information. - * @retval None - */ -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) -{ - uint32_t filternbrbitpos = 0; - CAN_TypeDef *can_ip; - - /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); - assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber)); - - filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber; -#if defined (CAN3) - /* Check the CAN instance */ - if(hcan->Instance == CAN3) - { - can_ip = CAN3; - } - else - { - can_ip = CAN1; - } -#else - can_ip = CAN1; -#endif - - /* Initialisation mode for the filter */ - can_ip->FMR |= (uint32_t)CAN_FMR_FINIT; - - /* Select the start slave bank */ - can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); - can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8); - - /* Filter Deactivation */ - can_ip->FA1R &= ~(uint32_t)filternbrbitpos; - - /* Filter Scale */ - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) - { - /* 16-bit scale for the filter */ - can_ip->FS1R &= ~(uint32_t)filternbrbitpos; - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh); - } - - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) - { - /* 32-bit scale for the filter */ - can_ip->FS1R |= filternbrbitpos; - - /* 32-bit identifier or First 32-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); - - /* 32-bit mask or Second 32-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow); - } - - /* Filter Mode */ - if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) - { - /*Id/Mask mode for the filter*/ - can_ip->FM1R &= ~(uint32_t)filternbrbitpos; - } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ - { - /*Identifier list mode for the filter*/ - can_ip->FM1R |= (uint32_t)filternbrbitpos; - } - - /* Filter FIFO assignment */ - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) - { - /* FIFO 0 assignation for the filter */ - can_ip->FFA1R &= ~(uint32_t)filternbrbitpos; - } - - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1) - { - /* FIFO 1 assignation for the filter */ - can_ip->FFA1R |= (uint32_t)filternbrbitpos; - } - - /* Filter activation */ - if (sFilterConfig->FilterActivation == ENABLE) - { - can_ip->FA1R |= filternbrbitpos; - } - - /* Leave the initialisation mode for the filter */ - can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Deinitializes the CANx peripheral registers to their default reset values. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) -{ - /* Check CAN handle */ - if(hcan == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* DeInit the low level hardware */ - HAL_CAN_MspDeInit(hcan); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CAN MSP. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the CAN MSP. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Transmit a CAN frame message. - (+) Receive a CAN frame message. - (+) Enter CAN peripheral in sleep mode. - (+) Wake up the CAN peripheral from sleep mode. - -@endverbatim - * @{ - */ - -/** - * @brief Initiates and transmits a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) -{ - uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); - assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); - assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - - if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ - ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ - ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) - { - /* Process locked */ - __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } - - /* Select one empty transmit mailbox */ - if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmitmailbox = CAN_TXMAILBOX_0; - } - else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmitmailbox = CAN_TXMAILBOX_1; - } - else - { - transmitmailbox = CAN_TXMAILBOX_2; - } - - /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if (hcan->pTxMsg->IDE == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ - hcan->pTxMsg->RTR); - } - else - { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); - } - - /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; - - /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | - ((uint32_t)hcan->pTxMsg->Data[2] << 16) | - ((uint32_t)hcan->pTxMsg->Data[1] << 8) | - ((uint32_t)hcan->pTxMsg->Data[0])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | - ((uint32_t)hcan->pTxMsg->Data[6] << 16) | - ((uint32_t)hcan->pTxMsg->Data[5] << 8) | - ((uint32_t)hcan->pTxMsg->Data[4])); - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check End of transmission flag */ - while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - } - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - } - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Initiates and transmits a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) -{ - uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; - - /* Check the parameters */ - assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); - assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); - assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - - if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ - ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ - ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) - { - /* Process Locked */ - __HAL_LOCK(hcan); - - /* Select one empty transmit mailbox */ - if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmitmailbox = CAN_TXMAILBOX_0; - } - else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmitmailbox = CAN_TXMAILBOX_1; - } - else - { - transmitmailbox = CAN_TXMAILBOX_2; - } - - /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if(hcan->pTxMsg->IDE == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ - hcan->pTxMsg->RTR); - } - else - { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); - } - - /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; - - /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | - ((uint32_t)hcan->pTxMsg->Data[2] << 16) | - ((uint32_t)hcan->pTxMsg->Data[1] << 8) | - ((uint32_t)hcan->pTxMsg->Data[0])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | - ((uint32_t)hcan->pTxMsg->Data[6] << 16) | - ((uint32_t)hcan->pTxMsg->Data[5] << 8) | - ((uint32_t)hcan->pTxMsg->Data[4])); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } - - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hcan); - - /* Enable Error warning, Error passive, Bus-off, - Last error and Error Interrupts */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR | - CAN_IT_TME); - - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - /* Return function status */ - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Receives a correct CAN frame. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: FIFO Number value - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_CAN_FIFO(FIFONumber)); - - /* Process locked */ - __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check pending message */ - while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - } - - /* Get the Id */ - hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (hcan->pRxMsg->IDE == CAN_ID_STD) - { - hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21); - } - else - { - hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); - } - - hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8); - /* Get the data field */ - hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8); - hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16); - hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24); - hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8); - hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16); - hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24); - - /* Release the FIFO */ - if(FIFONumber == CAN_FIFO0) - { - /* Release FIFO0 */ - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); - } - else /* FIFONumber == CAN_FIFO1 */ - { - /* Release FIFO1 */ - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); - } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - } - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Receives a correct CAN frame. - * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: Specify the FIFO number - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_CAN_FIFO(FIFONumber)); - - tmp = hcan->State; - if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_TX)) - { - /* Process locked */ - __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; - } - - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Enable Error warning, Error passive, Bus-off, - Last error and Error Interrupts */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR); - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - if(FIFONumber == CAN_FIFO0) - { - /* Enable FIFO 0 message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0); - } - else - { - /* Enable FIFO 1 message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1); - } - - } - else - { - return HAL_BUSY; - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Enters the Sleep (low power) mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) -{ - uint32_t tickstart = 0; - - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Request Sleep mode */ - hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Sleep mode status */ - if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) - { - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_ERROR; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) - { - if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral - * is in the normal mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) -{ - uint32_t tickstart = 0; - - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Wake up request */ - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Sleep mode status */ - while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) - { - if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) - { - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_ERROR; - } - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Handles CAN interrupt request - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) -{ - uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0; - - /* Check End of transmission flag */ - if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME)) - { - tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0); - tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1); - tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2); - if(tmp1 || tmp2 || tmp3) - { - /* Call transmit function */ - CAN_Transmit_IT(hcan); - } - } - - tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0); - /* Check End of reception flag for FIFO0 */ - if((tmp1 != 0) && tmp2) - { - /* Call receive function */ - CAN_Receive_IT(hcan, CAN_FIFO0); - } - - tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1); - /* Check End of reception flag for FIFO1 */ - if((tmp1 != 0) && tmp2) - { - /* Call receive function */ - CAN_Receive_IT(hcan, CAN_FIFO1); - } - - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG); - tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); - /* Check Error Warning Flag */ - if(tmp1 && tmp2 && tmp3) - { - /* Set CAN error code to EWG error */ - hcan->ErrorCode |= HAL_CAN_ERROR_EWG; - } - - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV); - tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); - /* Check Error Passive Flag */ - if(tmp1 && tmp2 && tmp3) - { - /* Set CAN error code to EPV error */ - hcan->ErrorCode |= HAL_CAN_ERROR_EPV; - } - - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF); - tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); - /* Check Bus-Off Flag */ - if(tmp1 && tmp2 && tmp3) - { - /* Set CAN error code to BOF error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BOF; - } - - tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC); - tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); - /* Check Last error code Flag */ - if((!tmp1) && tmp2 && tmp3) - { - tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC; - switch(tmp1) - { - case(CAN_ESR_LEC_0): - /* Set CAN error code to STF error */ - hcan->ErrorCode |= HAL_CAN_ERROR_STF; - break; - case(CAN_ESR_LEC_1): - /* Set CAN error code to FOR error */ - hcan->ErrorCode |= HAL_CAN_ERROR_FOR; - break; - case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0): - /* Set CAN error code to ACK error */ - hcan->ErrorCode |= HAL_CAN_ERROR_ACK; - break; - case(CAN_ESR_LEC_2): - /* Set CAN error code to BR error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BR; - break; - case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0): - /* Set CAN error code to BD error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BD; - break; - case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1): - /* Set CAN error code to CRC error */ - hcan->ErrorCode |= HAL_CAN_ERROR_CRC; - break; - default: - break; - } - - /* Clear Last error code Flag */ - hcan->Instance->ESR &= ~(CAN_ESR_LEC); - } - - /* Call the Error call Back in case of Errors */ - if(hcan->ErrorCode != HAL_CAN_ERROR_NONE) - { - /* Clear ERRI Flag */ - hcan->Instance->MSR = CAN_MSR_ERRI; - /* Set the CAN state ready to be able to start again the process */ - hcan->State = HAL_CAN_STATE_READY; - /* Call Error callback function */ - HAL_CAN_ErrorCallback(hcan); - } -} - -/** - * @brief Transmission complete callback in non blocking mode - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Transmission complete callback in non blocking mode - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Error CAN callback. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions - * @brief CAN Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Error functions ##### - ============================================================================== - [..] - This subsection provides functions allowing to : - (+) Check the CAN state. - (+) Check CAN Errors detected during interrupt process - -@endverbatim - * @{ - */ - -/** - * @brief return the CAN state - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL state - */ -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan) -{ - /* Return CAN state */ - return hcan->State; -} - -/** - * @brief Return the CAN error code - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval CAN Error Code - */ -uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) -{ - return hcan->ErrorCode; -} - -/** - * @} - */ -/** - * @brief Initiates and transmits a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) -{ - /* Disable Transmit mailbox empty Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) - { - /* Disable Error warning, Error passive, Bus-off, Last error code - and Error Interrupts */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR ); - } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - } - - /* Transmission complete callback */ - HAL_CAN_TxCpltCallback(hcan); - - return HAL_OK; -} - -/** - * @brief Receives a correct CAN frame. - * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: Specify the FIFO number - * @retval HAL status - * @retval None - */ -static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) -{ - /* Get the Id */ - hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (hcan->pRxMsg->IDE == CAN_ID_STD) - { - hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21); - } - else - { - hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); - } - - hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8); - /* Get the data field */ - hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8); - hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16); - hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24); - hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8); - hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16); - hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24); - /* Release the FIFO */ - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); - - /* Disable FIFO 0 message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0); - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); - - /* Disable FIFO 1 message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1); - } - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Disable Error warning, Error passive, Bus-off, Last error code - and Error Interrupts */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR); - } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) - { - /* Disable CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - } - - /* Receive complete callback */ - HAL_CAN_RxCpltCallback(hcan); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -#endif /* HAL_CAN_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cec.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cec.c deleted file mode 100644 index f6086ac..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cec.c +++ /dev/null @@ -1,668 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_cec.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief CEC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the High Definition Multimedia Interface - * Consumer Electronics Control Peripheral (CEC). - * + Initialization and de-initialization function - * + IO operation function - * + Peripheral Control function - * - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The CEC HAL driver can be used as follow: - - (#) Declare a CEC_HandleTypeDef handle structure. - (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API: - (##) Enable the CEC interface clock. - (##) CEC pins configuration: - (+++) Enable the clock for the CEC GPIOs. - (+++) Configure these CEC pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT() - and HAL_CEC_Receive_IT() APIs): - (+++) Configure the CEC interrupt priority. - (+++) Enable the NVIC CEC IRQ handle. - (+++) The specific CEC interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit - and receive process. - - (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in - in case of Bit Rising Error, Error-Bit generation conditions, device logical - address and Listen mode in the hcec Init structure. - - (#) Initialize the CEC registers by calling the HAL_CEC_Init() API. - - [..] - (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_CEC_MspInit() API. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup CEC CEC - * @brief HAL CEC module driver - * @{ - */ -#ifdef HAL_CEC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup CEC_Private_Constants CEC Private Constants - * @{ - */ -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup CEC_Private_Functions CEC Private Functions - * @{ - */ -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup CEC_Exported_Functions CEC Exported Functions - * @{ - */ - -/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the CEC - (+) The following parameters need to be configured: - (++) SignalFreeTime - (++) Tolerance - (++) BRERxStop (RX stopped or not upon Bit Rising Error) - (++) BREErrorBitGen (Error-Bit generation in case of Bit Rising Error) - (++) LBPEErrorBitGen (Error-Bit generation in case of Long Bit Period Error) - (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error) - (++) SignalFreeTimeOption (SFT Timer start definition) - (++) OwnAddress (CEC device address) - (++) ListenMode - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the CEC mode according to the specified - * parameters in the CEC_InitTypeDef and creates the associated handle . - * @param hcec: CEC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) -{ - /* Check the CEC handle allocation */ - if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance)); - assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime)); - assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance)); - assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop)); - assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen)); - assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen)); - assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen)); - assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption)); - assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode)); - assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress)); - - if(hcec->gState == HAL_CEC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hcec->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK */ - HAL_CEC_MspInit(hcec); - } - hcec->gState = HAL_CEC_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_CEC_DISABLE(hcec); - - /* Write to CEC Control Register */ - hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop|\ - hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen |\ - hcec->Init.SignalFreeTimeOption |((uint32_t)(hcec->Init.OwnAddress)<<16U) |\ - hcec->Init.ListenMode; - - /* Enable the following CEC Transmission/Reception interrupts as - * well as the following CEC Transmission/Reception Errors interrupts - * Rx Byte Received IT - * End of Reception IT - * Rx overrun - * Rx bit rising error - * Rx short bit period error - * Rx long bit period error - * Rx missing acknowledge - * Tx Byte Request IT - * End of Transmission IT - * Tx Missing Acknowledge IT - * Tx-Error IT - * Tx-Buffer Underrun IT - * Tx arbitration lost */ - __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR); - - /* Enable the CEC Peripheral */ - __HAL_CEC_ENABLE(hcec); - - hcec->ErrorCode = HAL_CEC_ERROR_NONE; - hcec->gState = HAL_CEC_STATE_READY; - hcec->RxState = HAL_CEC_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the CEC peripheral - * @param hcec: CEC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) -{ - /* Check the CEC handle allocation */ - if(hcec == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance)); - - hcec->gState = HAL_CEC_STATE_BUSY; - - /* DeInit the low level hardware */ - HAL_CEC_MspDeInit(hcec); - - /* Disable the Peripheral */ - __HAL_CEC_DISABLE(hcec); - - /* Clear Flags */ - __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXEND|CEC_FLAG_TXBR|CEC_FLAG_RXBR|CEC_FLAG_RXEND|CEC_ISR_ALL_ERROR); - - /* Disable the following CEC Transmission/Reception interrupts as - * well as the following CEC Transmission/Reception Errors interrupts - * Rx Byte Received IT - * End of Reception IT - * Rx overrun - * Rx bit rising error - * Rx short bit period error - * Rx long bit period error - * Rx missing acknowledge - * Tx Byte Request IT - * End of Transmission IT - * Tx Missing Acknowledge IT - * Tx-Error IT - * Tx-Buffer Underrun IT - * Tx arbitration lost */ - __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR); - - hcec->ErrorCode = HAL_CEC_ERROR_NONE; - hcec->gState = HAL_CEC_STATE_RESET; - hcec->RxState = HAL_CEC_STATE_RESET; - - /* Process Unlock */ - __HAL_UNLOCK(hcec); - - return HAL_OK; -} - -/** - * @brief Initializes the Own Address of the CEC device - * @param hcec: CEC handle - * @param CEC_OwnAddress: The CEC own address. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress) -{ - /* Check the parameters */ - assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress)); - - if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY)) - { - /* Process Locked */ - __HAL_LOCK(hcec); - - hcec->gState = HAL_CEC_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_CEC_DISABLE(hcec); - - if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE) - { - hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16); - } - else - { - hcec->Instance->CFGR &= ~(CEC_CFGR_OAR); - } - - hcec->gState = HAL_CEC_STATE_READY; - hcec->ErrorCode = HAL_CEC_ERROR_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hcec); - - /* Enable the Peripheral */ - __HAL_CEC_ENABLE(hcec); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief CEC MSP Init - * @param hcec: CEC handle - * @retval None - */ - __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcec); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CEC_MspInit can be implemented in the user file - */ -} - -/** - * @brief CEC MSP DeInit - * @param hcec: CEC handle - * @retval None - */ - __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcec); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CEC_MspDeInit can be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions - * @brief CEC Transmit/Receive functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of functions allowing to manage the CEC data transfers. - - (#) The CEC handle must contain the initiator (TX side) and the destination (RX side) - logical addresses (4-bit long addresses, 0xF for broadcast messages destination) - - (#) The communication is performed using Interrupts. - These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated CEC IRQ when using Interrupt mode. - The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_CEC_ErrorCallback() user callback will be executed when a communication - error is detected - - (#) API's with Interrupt are : - (+) HAL_CEC_Transmit_IT() - (+) HAL_CEC_IRQHandler() - - (#) A set of User Callbacks are provided: - (+) HAL_CEC_TxCpltCallback() - (+) HAL_CEC_RxCpltCallback() - (+) HAL_CEC_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Send data in interrupt mode - * @param hcec: CEC handle - * @param InitiatorAddress: Initiator address - * @param DestinationAddress: destination logical address - * @param pData: pointer to input byte data buffer - * @param Size: amount of data to be sent in bytes (without counting the header). - * 0 means only the header is sent (ping operation). - * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size) -{ - /* if the IP isn't already busy and if there is no previous transmission - already pending due to arbitration lost */ - if (hcec->gState == HAL_CEC_STATE_READY) - { - if((pData == NULL ) && (Size > 0)) - { - return HAL_ERROR; - } - - assert_param(IS_CEC_ADDRESS(DestinationAddress)); - assert_param(IS_CEC_ADDRESS(InitiatorAddress)); - assert_param(IS_CEC_MSGSIZE(Size)); - - /* Process Locked */ - __HAL_LOCK(hcec); - hcec->pTxBuffPtr = pData; - hcec->gState = HAL_CEC_STATE_BUSY_TX; - hcec->ErrorCode = HAL_CEC_ERROR_NONE; - - /* initialize the number of bytes to send, - * 0 means only one header is sent (ping operation) */ - hcec->TxXferCount = Size; - - /* in case of no payload (Size = 0), sender is only pinging the system; - Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */ - if (Size == 0) - { - __HAL_CEC_LAST_BYTE_TX_SET(hcec); - } - /* send header block */ - hcec->Instance->TXDR = ((uint8_t)(InitiatorAddress << CEC_INITIATOR_LSB_POS) |(uint8_t) DestinationAddress); - /* Set TX Start of Message (TXSOM) bit */ - __HAL_CEC_FIRST_BYTE_TX_SET(hcec); - - /* Process Unlocked */ - __HAL_UNLOCK(hcec); - - return HAL_OK; - - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Get size of the received frame. - * @param hcec: CEC handle - * @retval Frame size - */ -uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec) -{ - return hcec->RxXferSize; -} - -/** - * @brief Change Rx Buffer. - * @param hcec: CEC handle - * @param Rxbuffer: Rx Buffer - * @note This function can be called only inside the HAL_CEC_RxCpltCallback() - * @retval Frame size - */ -void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer) -{ - hcec->Init.RxBuffer = Rxbuffer; -} - -/** - * @brief This function handles CEC interrupt requests. - * @param hcec: CEC handle - * @retval None - */ -void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) -{ - - /* save interrupts register for further error or interrupts handling purposes */ - uint32_t reg = 0; - reg = hcec->Instance->ISR; - - - /* ----------------------------Arbitration Lost Management----------------------------------*/ - /* CEC TX arbitration error interrupt occurred --------------------------------------*/ - if((reg & CEC_FLAG_ARBLST) != RESET) - { - hcec->ErrorCode = HAL_CEC_ERROR_ARBLST; - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST); - } - - /* ----------------------------Rx Management----------------------------------*/ - /* CEC RX byte received interrupt ---------------------------------------------------*/ - if((reg & CEC_FLAG_RXBR) != RESET) - { - /* reception is starting */ - hcec->RxState = HAL_CEC_STATE_BUSY_RX; - hcec->RxXferSize++; - /* read received byte */ - *hcec->Init.RxBuffer++ = hcec->Instance->RXDR; - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR); - } - - /* CEC RX end received interrupt ---------------------------------------------------*/ - if((reg & CEC_FLAG_RXEND) != RESET) - { - /* clear IT */ - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND); - - /* Rx process is completed, restore hcec->RxState to Ready */ - hcec->RxState = HAL_CEC_STATE_READY; - hcec->ErrorCode = HAL_CEC_ERROR_NONE; - hcec->Init.RxBuffer-=hcec->RxXferSize; - HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize); - hcec->RxXferSize = 0; - } - - /* ----------------------------Tx Management----------------------------------*/ - /* CEC TX byte request interrupt ------------------------------------------------*/ - if((reg & CEC_FLAG_TXBR) != RESET) - { - if (hcec->TxXferCount == 0) - { - /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */ - __HAL_CEC_LAST_BYTE_TX_SET(hcec); - hcec->Instance->TXDR = *hcec->pTxBuffPtr++; - } - else - { - hcec->Instance->TXDR = *hcec->pTxBuffPtr++; - hcec->TxXferCount--; - } - /* clear Tx-Byte request flag */ - __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR); - } - - /* CEC TX end interrupt ------------------------------------------------*/ - if((reg & CEC_FLAG_TXEND) != RESET) - { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND); - - /* Tx process is ended, restore hcec->gState to Ready */ - hcec->gState = HAL_CEC_STATE_READY; - /* Call the Process Unlocked before calling the Tx call back API to give the possibility to - start again the Transmission under the Tx call back API */ - __HAL_UNLOCK(hcec); - hcec->ErrorCode = HAL_CEC_ERROR_NONE; - HAL_CEC_TxCpltCallback(hcec); - } - - /* ----------------------------Rx/Tx Error Management----------------------------------*/ - if ((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0) - { - hcec->ErrorCode = reg; - __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR|HAL_CEC_ERROR_BRE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|HAL_CEC_ERROR_RXACKE|HAL_CEC_ERROR_TXUDR|HAL_CEC_ERROR_TXERR|HAL_CEC_ERROR_TXACKE); - - - if((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE)) != RESET) - { - hcec->Init.RxBuffer-=hcec->RxXferSize; - hcec->RxXferSize = 0; - hcec->RxState = HAL_CEC_STATE_READY; - } - else if (((reg & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != RESET) && ((reg & CEC_ISR_ARBLST) == RESET)) - { - /* Set the CEC state ready to be able to start again the process */ - hcec->gState = HAL_CEC_STATE_READY; - } - - /* Error Call Back */ - HAL_CEC_ErrorCallback(hcec); - } - -} - -/** - * @brief Tx Transfer completed callback - * @param hcec: CEC handle - * @retval None - */ - __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcec); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CEC_TxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callback - * @param hcec: CEC handle - * @param RxFrameSize: Size of frame - * @retval None - */ -__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcec); - UNUSED(RxFrameSize); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CEC_RxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief CEC error callbacks - * @param hcec: CEC handle - * @retval None - */ - __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcec); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CEC_ErrorCallback can be implemented in the user file - */ -} -/** - * @} - */ - -/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function - * @brief CEC control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control function ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the CEC. - (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral. - (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral. -@endverbatim - * @{ - */ -/** - * @brief return the CEC state - * @param hcec: pointer to a CEC_HandleTypeDef structure that contains - * the configuration information for the specified CEC module. - * @retval HAL state - */ -HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec) -{ - uint32_t temp1= 0x00U, temp2 = 0x00U; - temp1 = hcec->gState; - temp2 = hcec->RxState; - - return (HAL_CEC_StateTypeDef)(temp1 | temp2); -} - -/** -* @brief Return the CEC error code -* @param hcec : pointer to a CEC_HandleTypeDef structure that contains - * the configuration information for the specified CEC. -* @retval CEC Error Code -*/ -uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec) -{ - return hcec->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ -#endif /* HAL_CEC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c deleted file mode 100644 index 8db58f5..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c +++ /dev/null @@ -1,483 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_cortex.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief CORTEX HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the CORTEX: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - - [..] - *** How to configure Interrupts using CORTEX HAL driver *** - =========================================================== - [..] - This section provides functions allowing to configure the NVIC interrupts (IRQ). - The Cortex-M4 exceptions are managed by CMSIS functions. - - (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() - function according to the following table. - (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). - (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). - (#) please refer to programming manual for details in how to configure priority. - - -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. - The pending IRQ priority will be managed only by the sub priority. - - -@- IRQ priority order (sorted by highest to lowest priority): - (+@) Lowest preemption priority - (+@) Lowest sub priority - (+@) Lowest hardware priority (IRQ number) - - [..] - *** How to configure Systick using CORTEX HAL driver *** - ======================================================== - [..] - Setup SysTick Timer for time base. - - (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which - is a CMSIS function that: - (++) Configures the SysTick Reload register with value passed as function parameter. - (++) Configures the SysTick IRQ priority to the lowest value (0x0F). - (++) Resets the SysTick Counter register. - (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). - (++) Enables the SysTick Interrupt. - (++) Starts the SysTick Counter. - - (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro - __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the - HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined - inside the stm32f7xx_hal_cortex.h file. - - (+) You can change the SysTick IRQ priority by calling the - HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function - call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. - - (+) To adjust the SysTick time base, use the following formula: - - Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) - (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function - (++) Reload Value should not exceed 0xFFFFFF - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup CORTEX CORTEX - * @brief CORTEX HAL module driver - * @{ - */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions - * @{ - */ - - -/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] - This section provides the CORTEX HAL driver functions allowing to configure Interrupts - Systick functionalities - -@endverbatim - * @{ - */ - - -/** - * @brief Sets the priority grouping field (preemption priority and subpriority) - * using the required unlock sequence. - * @param PriorityGroup: The priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority - * 4 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority - * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority - * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority - * 1 bits for subpriority - * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority - * 0 bits for subpriority - * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * @retval None - */ -void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ - NVIC_SetPriorityGrouping(PriorityGroup); -} - -/** - * @brief Sets the priority of an interrupt. - * @param IRQn: External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) - * @param PreemptPriority: The preemption priority for the IRQn channel. - * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority - * @param SubPriority: the subpriority level for the IRQ channel. - * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority. - * @retval None - */ -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t prioritygroup = 0x00; - - /* Check the parameters */ - assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); - - prioritygroup = NVIC_GetPriorityGrouping(); - - NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); -} - -/** - * @brief Enables a device specific interrupt in the NVIC interrupt controller. - * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) - * @retval None - */ -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Enable interrupt */ - NVIC_EnableIRQ(IRQn); -} - -/** - * @brief Disables a device specific interrupt in the NVIC interrupt controller. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) - * @retval None - */ -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Disable interrupt */ - NVIC_DisableIRQ(IRQn); -} - -/** - * @brief Initiates a system reset request to reset the MCU. - * @retval None - */ -void HAL_NVIC_SystemReset(void) -{ - /* System Reset */ - NVIC_SystemReset(); -} - -/** - * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. - * Counter is in free running mode to generate periodic interrupts. - * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. - * @retval status: - 0 Function succeeded. - * - 1 Function failed. - */ -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) -{ - return SysTick_Config(TicksNumb); -} -/** - * @} - */ - -/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions - * @brief Cortex control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the CORTEX - (NVIC, SYSTICK, MPU) functionalities. - - -@endverbatim - * @{ - */ - -#if (__MPU_PRESENT == 1) -/** - * @brief Initializes and configures the Region and the memory to be protected. - * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains - * the initialization and configuration information. - * @retval None - */ -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) -{ - /* Check the parameters */ - assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); - assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); - - /* Set the Region number */ - MPU->RNR = MPU_Init->Number; - - if ((MPU_Init->Enable) != RESET) - { - /* Check the parameters */ - assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); - assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); - assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); - assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); - assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); - assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); - assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); - assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); - - MPU->RBAR = MPU_Init->BaseAddress; - MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | - ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | - ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | - ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | - ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | - ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | - ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | - ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | - ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); - } - else - { - MPU->RBAR = 0x00; - MPU->RASR = 0x00; - } -} -#endif /* __MPU_PRESENT */ - -/** - * @brief Gets the priority grouping field from the NVIC Interrupt Controller. - * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) - */ -uint32_t HAL_NVIC_GetPriorityGrouping(void) -{ - /* Get the PRIGROUP[10:8] field value */ - return NVIC_GetPriorityGrouping(); -} - -/** - * @brief Gets the priority of an interrupt. - * @param IRQn: External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) - * @param PriorityGroup: the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority - * 4 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority - * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority - * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority - * 1 bits for subpriority - * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority - * 0 bits for subpriority - * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). - * @param pSubPriority: Pointer on the Subpriority value (starting from 0). - * @retval None - */ -void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - /* Get priority for Cortex-M system or device specific interrupts */ - NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); -} - -/** - * @brief Sets Pending bit of an external interrupt. - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) - * @retval None - */ -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Set interrupt pending */ - NVIC_SetPendingIRQ(IRQn); -} - -/** - * @brief Gets Pending Interrupt (reads the pending register in the NVIC - * and returns the pending bit for the specified interrupt). - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) - * @retval status: - 0 Interrupt status is not pending. - * - 1 Interrupt status is pending. - */ -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Return 1 if pending else 0 */ - return NVIC_GetPendingIRQ(IRQn); -} - -/** - * @brief Clears the pending bit of an external interrupt. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) - * @retval None - */ -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Clear pending interrupt */ - NVIC_ClearPendingIRQ(IRQn); -} - -/** - * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) - * @retval status: - 0 Interrupt status is not pending. - * - 1 Interrupt status is pending. - */ -uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Return 1 if active else 0 */ - return NVIC_GetActive(IRQn); -} - -/** - * @brief Configures the SysTick clock source. - * @param CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); - if (CLKSource == SYSTICK_CLKSOURCE_HCLK) - { - SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; - } - else - { - SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; - } -} - -/** - * @brief This function handles SYSTICK interrupt request. - * @retval None - */ -void HAL_SYSTICK_IRQHandler(void) -{ - HAL_SYSTICK_Callback(); -} - -/** - * @brief SYSTICK callback. - * @retval None - */ -__weak void HAL_SYSTICK_Callback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SYSTICK_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_CORTEX_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.c deleted file mode 100644 index b9b1172..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.c +++ /dev/null @@ -1,522 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_crc.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief CRC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Cyclic Redundancy Check (CRC) peripheral: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - =============================================================================== - ##### CRC How to use this driver ##### - =============================================================================== - [..] - - (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE(); - - (#) Initialize CRC calculator - (++) specify generating polynomial (IP default or non-default one) - (++) specify initialization value (IP default or non-default one) - (++) specify input data format - (++) specify input or output data inversion mode if any - - (#) Use HAL_CRC_Accumulate() function to compute the CRC value of the - input data buffer starting with the previously computed CRC as - initialization value - - (#) Use HAL_CRC_Calculate() function to compute the CRC value of the - input data buffer starting with the defined initialization value - (default or non-default) to initiate CRC calculation - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup CRC CRC - * @brief CRC HAL module driver. - * @{ - */ - -#ifdef HAL_CRC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength); -static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength); -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup CRC_Exported_Functions CRC Exported Functions - * @{ - */ - -/** @defgroup HAL_CRC_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions. - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the CRC according to the specified parameters - in the CRC_InitTypeDef and create the associated handle - (+) DeInitialize the CRC peripheral - (+) Initialize the CRC MSP - (+) DeInitialize CRC MSP - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the CRC according to the specified - * parameters in the CRC_InitTypeDef and create the associated handle. - * @param hcrc: CRC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) -{ - /* Check the CRC handle allocation */ - if(hcrc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); - - if(hcrc->State == HAL_CRC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hcrc->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ - HAL_CRC_MspInit(hcrc); - } - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_BUSY; - - /* check whether or not non-default generating polynomial has been - * picked up by user */ - assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); - if(hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) - { - /* initialize IP with default generating polynomial */ - WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); - MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); - } - else - { - /* initialize CRC IP with generating polynomial defined by user */ - if(HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK) - { - return HAL_ERROR; - } - } - - /* check whether or not non-default CRC initial value has been - * picked up by user */ - assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); - if(hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) - { - WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); - } - else - { - WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); - } - - - /* set input data inversion mode */ - assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); - MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); - - /* set output data inversion mode */ - assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); - MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); - - /* makes sure the input data format (bytes, halfwords or words stream) - * is properly specified by user */ - assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief DeInitialize the CRC peripheral. - * @param hcrc: CRC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) -{ - /* Check the CRC handle allocation */ - if(hcrc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); - - /* Check the CRC peripheral state */ - if(hcrc->State == HAL_CRC_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_BUSY; - - /* Reset CRC calculation unit */ - __HAL_CRC_DR_RESET(hcrc); - - /* DeInit the low level hardware */ - HAL_CRC_MspDeInit(hcrc); - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_RESET; - - /* Process unlocked */ - __HAL_UNLOCK(hcrc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initialize the CRC MSP. - * @param hcrc: CRC handle - * @retval None - */ -__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcrc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CRC_MspInit can be implemented in the user file - */ -} - -/** - * @brief DeInitialize the CRC MSP. - * @param hcrc: CRC handle - * @retval None - */ -__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcrc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CRC_MspDeInit can be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup HAL_CRC_Group2 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer - using combination of the previous CRC value and the new one. - - or - - (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer - independently of the previous CRC value. - -@endverbatim - * @{ - */ - -/** - * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer - * starting with the previously computed CRC as initialization value. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer, exact input data format is - * provided by hcrc->InputDataFormat. - * @param BufferLength: input data buffer length (number of bytes if pBuffer - * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, - * number of words if pBuffer type is * uint32_t). - * @note By default, the API expects a uint32_t pointer as input buffer parameter. - * Input buffer pointers with other types simply need to be cast in uint32_t - * and the API will internally adjust its input data processing based on the - * handle field hcrc->InputDataFormat. - * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) - */ -uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; /* CRC input data buffer index */ - uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */ - - /* Process locked */ - __HAL_LOCK(hcrc); - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_BUSY; - - switch (hcrc->InputDataFormat) - { - case CRC_INPUTDATA_FORMAT_WORDS: - /* Enter Data to the CRC calculator */ - for(index = 0; index < BufferLength; index++) - { - hcrc->Instance->DR = pBuffer[index]; - } - temp = hcrc->Instance->DR; - break; - - case CRC_INPUTDATA_FORMAT_BYTES: - temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength); - break; - - case CRC_INPUTDATA_FORMAT_HALFWORDS: - temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength); - break; - default: - break; - } - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcrc); - - /* Return the CRC computed value */ - return temp; -} - -/** - * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer - * starting with hcrc->Instance->INIT as initialization value. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer, exact input data format is - * provided by hcrc->InputDataFormat. - * @param BufferLength: input data buffer length (number of bytes if pBuffer - * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, - * number of words if pBuffer type is * uint32_t). - * @note By default, the API expects a uint32_t pointer as input buffer parameter. - * Input buffer pointers with other types simply need to be cast in uint32_t - * and the API will internally adjust its input data processing based on the - * handle field hcrc->InputDataFormat. - * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) - */ -uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; /* CRC input data buffer index */ - uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */ - - /* Process locked */ - __HAL_LOCK(hcrc); - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_BUSY; - - /* Reset CRC Calculation Unit (hcrc->Instance->INIT is - * written in hcrc->Instance->DR) */ - __HAL_CRC_DR_RESET(hcrc); - - switch (hcrc->InputDataFormat) - { - case CRC_INPUTDATA_FORMAT_WORDS: - /* Enter 32-bit input data to the CRC calculator */ - for(index = 0; index < BufferLength; index++) - { - hcrc->Instance->DR = pBuffer[index]; - } - temp = hcrc->Instance->DR; - break; - - case CRC_INPUTDATA_FORMAT_BYTES: - /* Specific 8-bit input data handling */ - temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength); - break; - - case CRC_INPUTDATA_FORMAT_HALFWORDS: - /* Specific 16-bit input data handling */ - temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength); - break; - default: - break; - } - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcrc); - - /* Return the CRC computed value */ - return temp; -} - -/** - * @brief Enter 8-bit input data to the CRC calculator. - * Specific data handling to optimize processing time. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer - * @param BufferLength: input data buffer length - * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) - */ -static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) -{ - uint32_t i = 0; /* input data buffer index */ - - /* Processing time optimization: 4 bytes are entered in a row with a single word write, - * last bytes must be carefully fed to the CRC calculator to ensure a correct type - * handling by the IP */ - for(i = 0; i < (BufferLength/4); i++) - { - hcrc->Instance->DR = (uint32_t)(((uint32_t)(pBuffer[4*i])<<24) | ((uint32_t)(pBuffer[4*i+1])<<16) | ((uint32_t)(pBuffer[4*i+2])<<8) | (uint32_t)(pBuffer[4*i+3])); - } - /* last bytes specific handling */ - if((BufferLength%4) != 0) - { - if(BufferLength%4 == 1) - { - *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i]; - } - if(BufferLength%4 == 2) - { - *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)((uint16_t)((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1])); - } - if(BufferLength%4 == 3) - { - *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)((uint16_t)((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1])); - *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; - } - } - - /* Return the CRC computed value */ - return hcrc->Instance->DR; -} - -/** - * @brief Enter 16-bit input data to the CRC calculator. - * Specific data handling to optimize processing time. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer - * @param BufferLength: input data buffer length - * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) - */ -static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) -{ - uint32_t i = 0; /* input data buffer index */ - - /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, - * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure - * a correct type handling by the IP */ - for(i = 0; i < (BufferLength/2); i++) - { - hcrc->Instance->DR = (((uint32_t)(pBuffer[2*i])<<16) | (uint32_t)(pBuffer[2*i+1])); - } - if((BufferLength%2) != 0) - { - *(__IO uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i]; - } - - /* Return the CRC computed value */ - return hcrc->Instance->DR; -} - -/** - * @} - */ - -/** @defgroup HAL_CRC_Group3 Peripheral State functions - * @brief Peripheral State functions. - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the CRC state. - * @param hcrc: CRC handle - * @retval HAL state - */ -HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) -{ - return hcrc->State; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_CRC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.c deleted file mode 100644 index d368d9a..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.c +++ /dev/null @@ -1,242 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_crc_ex.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Extended CRC HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the CRC peripheral: - * + Initialization/de-initialization functions - * - @verbatim - ============================================================================== - ##### CRC specific features ##### - ============================================================================== - [..] - (#) Polynomial configuration. - (#) Input data reverse mode. - (#) Output data reverse mode. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup CRCEx - * @brief CRC Extended HAL module driver - * @{ - */ - -#ifdef HAL_CRC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @addtogroup CRCEx_Exported_Functions - * @{ - */ - -/** @addtogroup CRCEx_Exported_Functions_Group1 - * @brief Extended CRC features functions - * -@verbatim - =============================================================================== - ##### CRC Extended features functions ##### - =============================================================================== - [..] -This subsection provides function allowing to: - (+) Set CRC polynomial if different from default one. - -@endverbatim - * @{ - */ - - -/** - * @brief Initializes the CRC polynomial if different from default one. - * @param hcrc: CRC handle - * @param Pol: CRC generating polynomial (7, 8, 16 or 32-bit long) - * This parameter is written in normal representation, e.g. - * for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 - * for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021 - * @param PolyLength: CRC polynomial length - * This parameter can be one of the following values: - * @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7) - * @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8) - * @arg CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16) - * @arg CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) -{ - uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */ - - /* Check the parameters */ - assert_param(IS_CRC_POL_LENGTH(PolyLength)); - - /* check polynomial definition vs polynomial size: - * polynomial length must be aligned with polynomial - * definition. HAL_ERROR is reported if Pol degree is - * larger than that indicated by PolyLength. - * Look for MSB position: msb will contain the degree of - * the second to the largest polynomial member. E.g., for - * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ - while (((Pol & ((uint32_t)(0x1) << msb)) == 0) && (msb-- > 0)) - { - } - - switch (PolyLength) - { - case CRC_POLYLENGTH_7B: - if (msb >= HAL_CRC_LENGTH_7B) - { - return HAL_ERROR; - } - break; - case CRC_POLYLENGTH_8B: - if (msb >= HAL_CRC_LENGTH_8B) - { - return HAL_ERROR; - } - break; - case CRC_POLYLENGTH_16B: - if (msb >= HAL_CRC_LENGTH_16B) - { - return HAL_ERROR; - } - break; - case CRC_POLYLENGTH_32B: - /* no polynomial definition vs. polynomial length issue possible */ - break; - default: - break; - } - - /* set generating polynomial */ - WRITE_REG(hcrc->Instance->POL, Pol); - - /* set generating polynomial size */ - MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Set the Reverse Input data mode. - * @param hcrc: CRC handle - * @param InputReverseMode: Input Data inversion mode - * This parameter can be one of the following values: - * @arg CRC_INPUTDATA_INVERSION_NONE: no change in bit order (default value) - * @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal - * @arg CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal - * @arg CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode) -{ - /* Check the parameters */ - assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode)); - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_BUSY; - - /* set input data inversion mode */ - MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode); - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Set the Reverse Output data mode. - * @param hcrc: CRC handle - * @param OutputReverseMode: Output Data inversion mode - * This parameter can be one of the following values: - * @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value) - * @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode) -{ - /* Check the parameters */ - assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode)); - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_BUSY; - - /* set output data inversion mode */ - MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode); - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - - - - -/** - * @} - */ - - -/** - * @} - */ - - -#endif /* HAL_CRC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp.c deleted file mode 100644 index ac4a390..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp.c +++ /dev/null @@ -1,3823 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_cryp.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief CRYP HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Cryptography (CRYP) peripheral: - * + Initialization and de-initialization functions - * + AES processing functions - * + DES processing functions - * + TDES processing functions - * + DMA callback functions - * + CRYP IRQ handler management - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The CRYP HAL driver can be used as follows: - - (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit(): - (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE() - (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT()) - (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority() - (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ() - (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler() - (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA()) - (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE() - (+++) Configure and enable two DMA streams one for managing data transfer from - memory to peripheral (input stream) and another stream for managing data - transfer from peripheral to memory (output stream) - (+++) Associate the initialized DMA handle to the CRYP DMA handle - using __HAL_LINKDMA() - (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the two DMA Streams. The output stream should have higher - priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() - - (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly: - (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit - (##) The key size: 128, 192 and 256. This parameter is relevant only for AES - (##) The encryption/decryption key. It's size depends on the algorithm - used for encryption/decryption - (##) The initialization vector (counter). It is not used ECB mode. - - (#)Three processing (encryption/decryption) functions are available: - (##) Polling mode: encryption and decryption APIs are blocking functions - i.e. they process the data and wait till the processing is finished, - e.g. HAL_CRYP_AESCBC_Encrypt() - (##) Interrupt mode: encryption and decryption APIs are not blocking functions - i.e. they process the data under interrupt, - e.g. HAL_CRYP_AESCBC_Encrypt_IT() - (##) DMA mode: encryption and decryption APIs are not blocking functions - i.e. the data transfer is ensured by DMA, - e.g. HAL_CRYP_AESCBC_Encrypt_DMA() - - (#)When the processing function is called at first time after HAL_CRYP_Init() - the CRYP peripheral is initialized and processes the buffer in input. - At second call, the processing function performs an append of the already - processed buffer. - When a new data block is to be processed, call HAL_CRYP_Init() then the - processing function. - - (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) -/** @defgroup CRYP CRYP - * @brief CRYP HAL module driver. - * @{ - */ - - -#ifdef HAL_CRYP_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup CRYP_Private_define - * @{ - */ -#define CRYP_TIMEOUT_VALUE 1 -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup CRYP_Private_Functions_prototypes - * @{ - */ -static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize); -static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize); -static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout); -static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout); -static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma); -static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma); -static void CRYP_DMAError(DMA_HandleTypeDef *hdma); -static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr); -static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction); -static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction); -static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction); -static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction); -/** - * @} - */ -/* Private functions ---------------------------------------------------------*/ - -/** @addtogroup CRYP_Private_Functions - * @{ - */ - -/** - * @brief DMA CRYP Input Data process complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) -{ - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit - in the DMACR register */ - hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN); - - /* Call input data transfer complete callback */ - HAL_CRYP_InCpltCallback(hcryp); -} - -/** - * @brief DMA CRYP Output Data process complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) -{ - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Disable the DMA transfer for output FIFO request by resetting the DOEN bit - in the DMACR register */ - hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN); - - /* Disable CRYP */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change the CRYP state to ready */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Call output data transfer complete callback */ - HAL_CRYP_OutCpltCallback(hcryp); -} - -/** - * @brief DMA CRYP communication error callback. - * @param hdma: DMA handle - * @retval None - */ -static void CRYP_DMAError(DMA_HandleTypeDef *hdma) -{ - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - hcryp->State= HAL_CRYP_STATE_READY; - HAL_CRYP_ErrorCallback(hcryp); -} - -/** - * @brief Writes the Key in Key registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Key: Pointer to Key buffer - * @param KeySize: Size of Key - * @retval None - */ -static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize) -{ - uint32_t keyaddr = (uint32_t)Key; - - switch(KeySize) - { - case CRYP_KEYSIZE_256B: - /* Key Initialisation */ - hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr)); - break; - case CRYP_KEYSIZE_192B: - hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr)); - break; - case CRYP_KEYSIZE_128B: - hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr)); - break; - default: - break; - } -} - -/** - * @brief Writes the InitVector/InitCounter in IV registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param InitVector: Pointer to InitVector/InitCounter buffer - * @param IVSize: Size of the InitVector/InitCounter - * @retval None - */ -static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize) -{ - uint32_t ivaddr = (uint32_t)InitVector; - - switch(IVSize) - { - case CRYP_KEYSIZE_128B: - hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; - hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; - hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; - hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr)); - break; - /* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */ - case CRYP_KEYSIZE_192B: - hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; - hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr)); - break; - case CRYP_KEYSIZE_256B: - hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; - hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr)); - break; - default: - break; - } -} - -/** - * @brief Process Data: Writes Input data in polling mode and read the output data - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Input: Pointer to the Input buffer - * @param Ilength: Length of the Input buffer, must be a multiple of 16. - * @param Output: Pointer to the returned buffer - * @param Timeout: Timeout value - * @retval None - */ -static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - uint32_t i = 0; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - - for(i=0; (i < Ilength); i+=16) - { - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Process Data: Write Input data in polling mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Input: Pointer to the Input buffer - * @param Ilength: Length of the Input buffer, must be a multiple of 8 - * @param Output: Pointer to the returned buffer - * @param Timeout: Specify Timeout value - * @retval None - */ -static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - uint32_t i = 0; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - - for(i=0; (i < Ilength); i+=8) - { - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Set the DMA configuration and start the DMA transfer - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param inputaddr: address of the Input buffer - * @param Size: Size of the Input buffer, must be a multiple of 16. - * @param outputaddr: address of the Output buffer - * @retval None - */ -static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) -{ - /* Set the CRYP DMA transfer complete callback */ - hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt; - /* Set the DMA error callback */ - hcryp->hdmain->XferErrorCallback = CRYP_DMAError; - - /* Set the CRYP DMA transfer complete callback */ - hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt; - /* Set the DMA error callback */ - hcryp->hdmaout->XferErrorCallback = CRYP_DMAError; - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Enable the DMA In DMA Stream */ - HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4); - - /* Enable In DMA request */ - hcryp->Instance->DMACR = (CRYP_DMACR_DIEN); - - /* Enable the DMA Out DMA Stream */ - HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4); - - /* Enable Out DMA request */ - hcryp->Instance->DMACR |= CRYP_DMACR_DOEN; - -} - -/** - * @brief Sets the CRYP peripheral in DES ECB mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Direction: Encryption or decryption - * @retval None - */ -static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) -{ - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_ECB | Direction); - - /* Set the key */ - hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey)); - hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4)); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } -} - -/** - * @brief Sets the CRYP peripheral in DES CBC mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Direction: Encryption or decryption - * @retval None - */ -static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) -{ - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_CBC | Direction); - - /* Set the key */ - hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey)); - hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4)); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } -} - -/** - * @brief Sets the CRYP peripheral in TDES ECB mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Direction: Encryption or decryption - * @retval None - */ -static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) -{ - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_ECB | Direction); - - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } -} - -/** - * @brief Sets the CRYP peripheral in TDES CBC mode - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Direction: Encryption or decryption - * @retval None - */ -static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) -{ - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the CRYP peripheral in AES CBC mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_CBC | Direction); - - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } -} - -/** - * @} - */ - - /* Exported functions --------------------------------------------------------*/ -/** @addtogroup CRYP_Exported_Functions - * @{ - */ - -/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the CRYP according to the specified parameters - in the CRYP_InitTypeDef and creates the associated handle - (+) DeInitialize the CRYP peripheral - (+) Initialize the CRYP MSP - (+) DeInitialize CRYP MSP - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the CRYP according to the specified - * parameters in the CRYP_InitTypeDef and creates the associated handle. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) -{ - /* Check the CRYP handle allocation */ - if(hcryp == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize)); - assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType)); - - if(hcryp->State == HAL_CRYP_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hcryp->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ - HAL_CRYP_MspInit(hcryp); - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set the key size and data type*/ - CRYP->CR = (uint32_t) (hcryp->Init.KeySize | hcryp->Init.DataType); - - /* Reset CrypInCount and CrypOutCount */ - hcryp->CrypInCount = 0; - hcryp->CrypOutCount = 0; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Set the default CRYP phase */ - hcryp->Phase = HAL_CRYP_PHASE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief DeInitializes the CRYP peripheral. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) -{ - /* Check the CRYP handle allocation */ - if(hcryp == NULL) - { - return HAL_ERROR; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set the default CRYP phase */ - hcryp->Phase = HAL_CRYP_PHASE_READY; - - /* Reset CrypInCount and CrypOutCount */ - hcryp->CrypInCount = 0; - hcryp->CrypOutCount = 0; - - /* Disable the CRYP Peripheral Clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* DeInit the low level hardware: CLOCK, NVIC.*/ - HAL_CRYP_MspDeInit(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval None - */ -__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcryp); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval None - */ -__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcryp); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions - * @brief processing functions. - * -@verbatim - ============================================================================== - ##### AES processing functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Encrypt plaintext using AES-128/192/256 using chaining modes - (+) Decrypt cyphertext using AES-128/192/256 using chaining modes - [..] Three processing functions are available: - (+) Polling mode - (+) Interrupt mode - (+) DMA mode - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the CRYP peripheral in AES ECB encryption mode - * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) -{ - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Write Plain Data and Get Cypher Data */ - if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in AES CBC encryption mode - * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) -{ - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Write Plain Data and Get Cypher Data */ - if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in AES CTR encryption mode - * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) -{ - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Write Plain Data and Get Cypher Data */ - if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - - - -/** - * @brief Initializes the CRYP peripheral in AES ECB decryption mode - * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES Key mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - - /* Disable CRYP */ - __HAL_CRYP_DISABLE(hcryp); - - /* Reset the ALGOMODE bits*/ - CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE); - - /* Set the CRYP peripheral in AES ECB decryption mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR); - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Write Plain Data and Get Cypher Data */ - if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in AES ECB decryption mode - * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES Key mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - - /* Reset the ALGOMODE bits*/ - CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE); - - /* Set the CRYP peripheral in AES CBC decryption mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Write Plain Data and Get Cypher Data */ - if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in AES CTR decryption mode - * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) -{ - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES CTR mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Write Plain Data and Get Cypher Data */ - if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if(hcryp->State == HAL_CRYP_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pPlainData; - hcryp->pCrypOutBuffPtr = pCypherData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Return function status */ - return HAL_OK; - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI)) - { - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - if(hcryp->CrypInCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - /* Call the Input data transfer complete callback */ - HAL_CRYP_InCpltCallback(hcryp); - } - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI)) - { - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; - if(hcryp->CrypOutCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - /* Process Locked */ - __HAL_UNLOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Call Input transfer complete callback */ - HAL_CRYP_OutCpltCallback(hcryp); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if(hcryp->State == HAL_CRYP_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pPlainData; - hcryp->pCrypOutBuffPtr = pCypherData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES CBC mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Return function status */ - return HAL_OK; - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI)) - { - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - if(hcryp->CrypInCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - /* Call the Input data transfer complete callback */ - HAL_CRYP_InCpltCallback(hcryp); - } - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI)) - { - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; - if(hcryp->CrypOutCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - /* Process Locked */ - __HAL_UNLOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Call Input transfer complete callback */ - HAL_CRYP_OutCpltCallback(hcryp); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if(hcryp->State == HAL_CRYP_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pPlainData; - hcryp->pCrypOutBuffPtr = pCypherData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES CTR mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Return function status */ - return HAL_OK; - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI)) - { - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - if(hcryp->CrypInCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - /* Call the Input data transfer complete callback */ - HAL_CRYP_InCpltCallback(hcryp); - } - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI)) - { - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; - if(hcryp->CrypOutCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Call Input transfer complete callback */ - HAL_CRYP_OutCpltCallback(hcryp); - } - } - - /* Return function status */ - return HAL_OK; -} - - -/** - * @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t tickstart = 0; - - uint32_t inputaddr; - uint32_t outputaddr; - - if(hcryp->State == HAL_CRYP_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pCypherData; - hcryp->pCrypOutBuffPtr = pPlainData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES Key mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR); - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - - /* Reset the ALGOMODE bits*/ - CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE); - - /* Set the CRYP peripheral in AES ECB decryption mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Return function status */ - return HAL_OK; - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI)) - { - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - if(hcryp->CrypInCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - /* Call the Input data transfer complete callback */ - HAL_CRYP_InCpltCallback(hcryp); - } - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI)) - { - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; - if(hcryp->CrypOutCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Call Input transfer complete callback */ - HAL_CRYP_OutCpltCallback(hcryp); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - - uint32_t tickstart = 0; - uint32_t inputaddr; - uint32_t outputaddr; - - if(hcryp->State == HAL_CRYP_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Get the buffer addresses and sizes */ - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pCypherData; - hcryp->pCrypOutBuffPtr = pPlainData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES Key mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - - /* Reset the ALGOMODE bits*/ - CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE); - - /* Set the CRYP peripheral in AES CBC decryption mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Return function status */ - return HAL_OK; - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI)) - { - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - if(hcryp->CrypInCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - /* Call the Input data transfer complete callback */ - HAL_CRYP_InCpltCallback(hcryp); - } - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI)) - { - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; - if(hcryp->CrypOutCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Call Input transfer complete callback */ - HAL_CRYP_OutCpltCallback(hcryp); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if(hcryp->State == HAL_CRYP_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Get the buffer addresses and sizes */ - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pCypherData; - hcryp->pCrypOutBuffPtr = pPlainData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES CTR mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Return function status */ - return HAL_OK; - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI)) - { - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - if(hcryp->CrypInCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - /* Call the Input data transfer complete callback */ - HAL_CRYP_InCpltCallback(hcryp); - } - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI)) - { - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; - if(hcryp->CrypOutCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Call Input transfer complete callback */ - HAL_CRYP_OutCpltCallback(hcryp); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pPlainData; - outputaddr = (uint32_t)pCypherData; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pPlainData; - outputaddr = (uint32_t)pCypherData; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pPlainData; - outputaddr = (uint32_t)pCypherData; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pPlainData: Pointer to the plaintext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t tickstart = 0; - uint32_t inputaddr; - uint32_t outputaddr; - - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pCypherData; - outputaddr = (uint32_t)pPlainData; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES Key mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - - /* Reset the ALGOMODE bits*/ - CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE); - - /* Set the CRYP peripheral in AES ECB decryption mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pPlainData: Pointer to the plaintext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t tickstart = 0; - uint32_t inputaddr; - uint32_t outputaddr; - - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pCypherData; - outputaddr = (uint32_t)pPlainData; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES Key mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - - /* Reset the ALGOMODE bits*/ - CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE); - - /* Set the CRYP peripheral in AES CBC decryption mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pCypherData; - outputaddr = (uint32_t)pPlainData; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES CTR mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - - -/** - * @} - */ - -/** @defgroup CRYP_Exported_Functions_Group3 DES processing functions - * @brief processing functions. - * -@verbatim - ============================================================================== - ##### DES processing functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Encrypt plaintext using DES using ECB or CBC chaining modes - (+) Decrypt cyphertext using ECB or CBC chaining modes - [..] Three processing functions are available: - (+) Polling mode - (+) Interrupt mode - (+) DMA mode - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the CRYP peripheral in DES ECB encryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) -{ - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in DES ECB encryption mode */ - CRYP_SetDESECBMode(hcryp, 0); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Write Plain Data and Get Cypher Data */ - if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in DES ECB decryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) -{ - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in DES ECB decryption mode */ - CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Write Plain Data and Get Cypher Data */ - if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in DES CBC encryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) -{ - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in DES CBC encryption mode */ - CRYP_SetDESCBCMode(hcryp, 0); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Write Plain Data and Get Cypher Data */ - if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in DES ECB decryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) -{ - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in DES CBC decryption mode */ - CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Write Plain Data and Get Cypher Data */ - if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in DES ECB encryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if(hcryp->State == HAL_CRYP_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pPlainData; - hcryp->pCrypOutBuffPtr = pCypherData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in DES ECB encryption mode */ - CRYP_SetDESECBMode(hcryp, 0); - - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Return function status */ - return HAL_OK; - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI)) - { - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - - hcryp->pCrypInBuffPtr += 8; - hcryp->CrypInCount -= 8; - if(hcryp->CrypInCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - /* Call the Input data transfer complete callback */ - HAL_CRYP_InCpltCallback(hcryp); - } - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI)) - { - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - - hcryp->pCrypOutBuffPtr += 8; - hcryp->CrypOutCount -= 8; - if(hcryp->CrypOutCount == 0) - { - /* Disable IT */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - /* Disable CRYP */ - __HAL_CRYP_DISABLE(hcryp); - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Call Input transfer complete callback */ - HAL_CRYP_OutCpltCallback(hcryp); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in DES CBC encryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if(hcryp->State == HAL_CRYP_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pPlainData; - hcryp->pCrypOutBuffPtr = pCypherData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in DES CBC encryption mode */ - CRYP_SetDESCBCMode(hcryp, 0); - - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Return function status */ - return HAL_OK; - } - - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI)) - { - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - - hcryp->pCrypInBuffPtr += 8; - hcryp->CrypInCount -= 8; - if(hcryp->CrypInCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - /* Call the Input data transfer complete callback */ - HAL_CRYP_InCpltCallback(hcryp); - } - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI)) - { - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - - hcryp->pCrypOutBuffPtr += 8; - hcryp->CrypOutCount -= 8; - if(hcryp->CrypOutCount == 0) - { - /* Disable IT */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - /* Disable CRYP */ - __HAL_CRYP_DISABLE(hcryp); - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Call Input transfer complete callback */ - HAL_CRYP_OutCpltCallback(hcryp); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in DES ECB decryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if(hcryp->State == HAL_CRYP_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pCypherData; - hcryp->pCrypOutBuffPtr = pPlainData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in DES ECB decryption mode */ - CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR); - - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Return function status */ - return HAL_OK; - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI)) - { - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - - hcryp->pCrypInBuffPtr += 8; - hcryp->CrypInCount -= 8; - if(hcryp->CrypInCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - /* Call the Input data transfer complete callback */ - HAL_CRYP_InCpltCallback(hcryp); - } - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI)) - { - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - - hcryp->pCrypOutBuffPtr += 8; - hcryp->CrypOutCount -= 8; - if(hcryp->CrypOutCount == 0) - { - /* Disable IT */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - /* Disable CRYP */ - __HAL_CRYP_DISABLE(hcryp); - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Call Input transfer complete callback */ - HAL_CRYP_OutCpltCallback(hcryp); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in DES ECB decryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if(hcryp->State == HAL_CRYP_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pCypherData; - hcryp->pCrypOutBuffPtr = pPlainData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in DES CBC decryption mode */ - CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR); - - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Return function status */ - return HAL_OK; - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI)) - { - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - - hcryp->pCrypInBuffPtr += 8; - hcryp->CrypInCount -= 8; - if(hcryp->CrypInCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - /* Call the Input data transfer complete callback */ - HAL_CRYP_InCpltCallback(hcryp); - } - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI)) - { - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - - hcryp->pCrypOutBuffPtr += 8; - hcryp->CrypOutCount -= 8; - if(hcryp->CrypOutCount == 0) - { - /* Disable IT */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - /* Disable CRYP */ - __HAL_CRYP_DISABLE(hcryp); - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Call Input transfer complete callback */ - HAL_CRYP_OutCpltCallback(hcryp); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in DES ECB encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pPlainData; - outputaddr = (uint32_t)pCypherData; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in DES ECB encryption mode */ - CRYP_SetDESECBMode(hcryp, 0); - - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in DES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pPlainData; - outputaddr = (uint32_t)pCypherData; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in DES CBC encryption mode */ - CRYP_SetDESCBCMode(hcryp, 0); - - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pCypherData; - outputaddr = (uint32_t)pPlainData; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in DES ECB decryption mode */ - CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR); - - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pCypherData; - outputaddr = (uint32_t)pPlainData; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in DES CBC decryption mode */ - CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR); - - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @} - */ - -/** @defgroup CRYP_Exported_Functions_Group4 TDES processing functions - * @brief processing functions. - * -@verbatim - ============================================================================== - ##### TDES processing functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Encrypt plaintext using TDES based on ECB or CBC chaining modes - (+) Decrypt cyphertext using TDES based on ECB or CBC chaining modes - [..] Three processing functions are available: - (+) Polling mode - (+) Interrupt mode - (+) DMA mode - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the CRYP peripheral in TDES ECB encryption mode - * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) -{ - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in TDES ECB encryption mode */ - CRYP_SetTDESECBMode(hcryp, 0); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Write Plain Data and Get Cypher Data */ - if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in TDES ECB decryption mode - * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) -{ - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in TDES ECB decryption mode */ - CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Write Cypher Data and Get Plain Data */ - if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in TDES CBC encryption mode - * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) -{ - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in TDES CBC encryption mode */ - CRYP_SetTDESCBCMode(hcryp, 0); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Write Plain Data and Get Cypher Data */ - if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in TDES CBC decryption mode - * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) -{ - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in TDES CBC decryption mode */ - CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Write Cypher Data and Get Plain Data */ - if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if(hcryp->State == HAL_CRYP_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pPlainData; - hcryp->pCrypOutBuffPtr = pCypherData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in TDES ECB encryption mode */ - CRYP_SetTDESECBMode(hcryp, 0); - - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Return function status */ - return HAL_OK; - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI)) - { - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - - hcryp->pCrypInBuffPtr += 8; - hcryp->CrypInCount -= 8; - if(hcryp->CrypInCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - /* Call the Input data transfer complete callback */ - HAL_CRYP_InCpltCallback(hcryp); - } - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI)) - { - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - - hcryp->pCrypOutBuffPtr += 8; - hcryp->CrypOutCount -= 8; - if(hcryp->CrypOutCount == 0) - { - /* Disable IT */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - /* Disable CRYP */ - __HAL_CRYP_DISABLE(hcryp); - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Call the Output data transfer complete callback */ - HAL_CRYP_OutCpltCallback(hcryp); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in TDES CBC encryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if(hcryp->State == HAL_CRYP_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pPlainData; - hcryp->pCrypOutBuffPtr = pCypherData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in TDES CBC encryption mode */ - CRYP_SetTDESCBCMode(hcryp, 0); - - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Return function status */ - return HAL_OK; - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI)) - { - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - - hcryp->pCrypInBuffPtr += 8; - hcryp->CrypInCount -= 8; - if(hcryp->CrypInCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - /* Call the Input data transfer complete callback */ - HAL_CRYP_InCpltCallback(hcryp); - } - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI)) - { - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - - hcryp->pCrypOutBuffPtr += 8; - hcryp->CrypOutCount -= 8; - if(hcryp->CrypOutCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - /* Disable CRYP */ - __HAL_CRYP_DISABLE(hcryp); - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Call Input transfer complete callback */ - HAL_CRYP_OutCpltCallback(hcryp); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in TDES ECB decryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if(hcryp->State == HAL_CRYP_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pCypherData; - hcryp->pCrypOutBuffPtr = pPlainData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in TDES ECB decryption mode */ - CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR); - - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Return function status */ - return HAL_OK; - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI)) - { - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - - hcryp->pCrypInBuffPtr += 8; - hcryp->CrypInCount -= 8; - if(hcryp->CrypInCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - /* Call the Input data transfer complete callback */ - HAL_CRYP_InCpltCallback(hcryp); - } - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI)) - { - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - - hcryp->pCrypOutBuffPtr += 8; - hcryp->CrypOutCount -= 8; - if(hcryp->CrypOutCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - /* Disable CRYP */ - __HAL_CRYP_DISABLE(hcryp); - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Call Input transfer complete callback */ - HAL_CRYP_OutCpltCallback(hcryp); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in TDES CBC decryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if(hcryp->State == HAL_CRYP_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pCypherData; - hcryp->pCrypOutBuffPtr = pPlainData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in TDES CBC decryption mode */ - CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR); - - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Return function status */ - return HAL_OK; - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI)) - { - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - - hcryp->pCrypInBuffPtr += 8; - hcryp->CrypInCount -= 8; - if(hcryp->CrypInCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - /* Call the Input data transfer complete callback */ - HAL_CRYP_InCpltCallback(hcryp); - } - } - else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI)) - { - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - - hcryp->pCrypOutBuffPtr += 8; - hcryp->CrypOutCount -= 8; - if(hcryp->CrypOutCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - /* Disable CRYP */ - __HAL_CRYP_DISABLE(hcryp); - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Call Input transfer complete callback */ - HAL_CRYP_OutCpltCallback(hcryp); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pPlainData; - outputaddr = (uint32_t)pCypherData; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in TDES ECB encryption mode */ - CRYP_SetTDESECBMode(hcryp, 0); - - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in TDES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pPlainData; - outputaddr = (uint32_t)pCypherData; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in TDES CBC encryption mode */ - CRYP_SetTDESCBCMode(hcryp, 0); - - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in TDES ECB decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pCypherData; - outputaddr = (uint32_t)pPlainData; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in TDES ECB decryption mode */ - CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR); - - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in TDES CBC decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pCypherData; - outputaddr = (uint32_t)pPlainData; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set CRYP peripheral in TDES CBC decryption mode */ - CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR); - - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @} - */ - -/** @defgroup CRYP_Exported_Functions_Group5 DMA callback functions - * @brief DMA callback functions. - * -@verbatim - ============================================================================== - ##### DMA callback functions ##### - ============================================================================== - [..] This section provides DMA callback functions: - (+) DMA Input data transfer complete - (+) DMA Output data transfer complete - (+) DMA error - -@endverbatim - * @{ - */ - -/** - * @brief Input FIFO transfer completed callbacks. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval None - */ -__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcryp); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_InCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Output FIFO transfer completed callbacks. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval None - */ -__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcryp); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_OutCpltCallback could be implemented in the user file - */ -} - -/** - * @brief CRYP error callbacks. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval None - */ - __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcryp); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup CRYP_Exported_Functions_Group6 CRYP IRQ handler management - * @brief CRYP IRQ handler. - * -@verbatim - ============================================================================== - ##### CRYP IRQ handler management ##### - ============================================================================== -[..] This section provides CRYP IRQ handler function. - -@endverbatim - * @{ - */ - -/** - * @brief This function handles CRYP interrupt request. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval None - */ -void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) -{ - switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION) - { - case CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT: - HAL_CRYP_TDESECB_Encrypt_IT(hcryp, NULL, 0, NULL); - break; - - case CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT: - HAL_CRYP_TDESECB_Decrypt_IT(hcryp, NULL, 0, NULL); - break; - - case CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT: - HAL_CRYP_TDESCBC_Encrypt_IT(hcryp, NULL, 0, NULL); - break; - - case CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT: - HAL_CRYP_TDESCBC_Decrypt_IT(hcryp, NULL, 0, NULL); - break; - - case CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT: - HAL_CRYP_DESECB_Encrypt_IT(hcryp, NULL, 0, NULL); - break; - - case CRYP_CR_ALGOMODE_DES_ECB_DECRYPT: - HAL_CRYP_DESECB_Decrypt_IT(hcryp, NULL, 0, NULL); - break; - - case CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT: - HAL_CRYP_DESCBC_Encrypt_IT(hcryp, NULL, 0, NULL); - break; - - case CRYP_CR_ALGOMODE_DES_CBC_DECRYPT: - HAL_CRYP_DESCBC_Decrypt_IT(hcryp, NULL, 0, NULL); - break; - - case CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT: - HAL_CRYP_AESECB_Encrypt_IT(hcryp, NULL, 0, NULL); - break; - - case CRYP_CR_ALGOMODE_AES_ECB_DECRYPT: - HAL_CRYP_AESECB_Decrypt_IT(hcryp, NULL, 0, NULL); - break; - - case CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT: - HAL_CRYP_AESCBC_Encrypt_IT(hcryp, NULL, 0, NULL); - break; - - case CRYP_CR_ALGOMODE_AES_CBC_DECRYPT: - HAL_CRYP_AESCBC_Decrypt_IT(hcryp, NULL, 0, NULL); - break; - - case CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT: - HAL_CRYP_AESCTR_Encrypt_IT(hcryp, NULL, 0, NULL); - break; - - case CRYP_CR_ALGOMODE_AES_CTR_DECRYPT: - HAL_CRYP_AESCTR_Decrypt_IT(hcryp, NULL, 0, NULL); - break; - - default: - break; - } -} - -/** - * @} - */ - -/** @defgroup CRYP_Exported_Functions_Group7 Peripheral State functions - * @brief Peripheral State functions. - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the CRYP state. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval HAL state - */ -HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp) -{ - return hcryp->State; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_CRYP_MODULE_ENABLED */ - - -/** - * @} - */ -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp_ex.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp_ex.c deleted file mode 100644 index 7afbb3b..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp_ex.c +++ /dev/null @@ -1,3040 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_cryp_ex.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Extended CRYP HAL module driver - * This file provides firmware functions to manage the following - * functionalities of CRYP extension peripheral: - * + Extended AES processing functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The CRYP Extension HAL driver can be used as follows: - (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit(): - (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE() - (##) In case of using interrupts (e.g. HAL_CRYPEx_AESGCM_Encrypt_IT()) - (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority() - (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ() - (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler() - (##) In case of using DMA to control data transfer (e.g. HAL_AES_ECB_Encrypt_DMA()) - (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE() - (+++) Configure and enable two DMA streams one for managing data transfer from - memory to peripheral (input stream) and another stream for managing data - transfer from peripheral to memory (output stream) - (+++) Associate the initialized DMA handle to the CRYP DMA handle - using __HAL_LINKDMA() - (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the two DMA Streams. The output stream should have higher - priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() - (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly: - (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit - (##) The key size: 128, 192 and 256. This parameter is relevant only for AES - (##) The encryption/decryption key. Its size depends on the algorithm - used for encryption/decryption - (##) The initialization vector (counter). It is not used ECB mode. - (#)Three processing (encryption/decryption) functions are available: - (##) Polling mode: encryption and decryption APIs are blocking functions - i.e. they process the data and wait till the processing is finished - e.g. HAL_CRYPEx_AESGCM_Encrypt() - (##) Interrupt mode: encryption and decryption APIs are not blocking functions - i.e. they process the data under interrupt - e.g. HAL_CRYPEx_AESGCM_Encrypt_IT() - (##) DMA mode: encryption and decryption APIs are not blocking functions - i.e. the data transfer is ensured by DMA - e.g. HAL_CRYPEx_AESGCM_Encrypt_DMA() - (#)When the processing function is called at first time after HAL_CRYP_Init() - the CRYP peripheral is initialized and processes the buffer in input. - At second call, the processing function performs an append of the already - processed buffer. - When a new data block is to be processed, call HAL_CRYP_Init() then the - processing function. - (#)In AES-GCM and AES-CCM modes are an authenticated encryption algorithms - which provide authentication messages. - HAL_AES_GCM_Finish() and HAL_AES_CCM_Finish() are used to provide those - authentication messages. - Call those functions after the processing ones (polling, interrupt or DMA). - e.g. in AES-CCM mode call HAL_CRYPEx_AESCCM_Encrypt() to encrypt the plain data - then call HAL_CRYPEx_AESCCM_Finish() to get the authentication message - -@- For CCM Encrypt/Decrypt API's, only DataType = 8-bit is supported by this version. - -@- The HAL_CRYPEx_AESGCM_xxxx() implementation is limited to 32bits inputs data length - (Plain/Cyphertext, Header) compared with GCM standards specifications (800-38D). - (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) -/** @defgroup CRYPEx CRYPEx - * @brief CRYP Extension HAL module driver. - * @{ - */ - - -#ifdef HAL_CRYP_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup CRYPEx_Private_define - * @{ - */ -#define CRYPEx_TIMEOUT_VALUE 1 -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup CRYPEx_Private_Functions_prototypes CRYP Private Functions Prototypes - * @{ - */ -static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector); -static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize); -static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout); -static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout); -static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma); -static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma); -static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma); -static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr); -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup CRYPEx_Private_Functions - * @{ - */ - -/** - * @brief DMA CRYP Input Data process complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma) -{ - CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Disable the DMA transfer for input Fifo request by resetting the DIEN bit - in the DMACR register */ - hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN); - - /* Call input data transfer complete callback */ - HAL_CRYP_InCpltCallback(hcryp); -} - -/** - * @brief DMA CRYP Output Data process complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma) -{ - CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Disable the DMA transfer for output Fifo request by resetting the DOEN bit - in the DMACR register */ - hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Call output data transfer complete callback */ - HAL_CRYP_OutCpltCallback(hcryp); -} - -/** - * @brief DMA CRYP communication error callback. - * @param hdma: DMA handle - * @retval None - */ -static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma) -{ - CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hcryp->State= HAL_CRYP_STATE_READY; - HAL_CRYP_ErrorCallback(hcryp); -} - -/** - * @brief Writes the Key in Key registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Key: Pointer to Key buffer - * @param KeySize: Size of Key - * @retval None - */ -static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize) -{ - uint32_t keyaddr = (uint32_t)Key; - - switch(KeySize) - { - case CRYP_KEYSIZE_256B: - /* Key Initialisation */ - hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr)); - break; - case CRYP_KEYSIZE_192B: - hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr)); - break; - case CRYP_KEYSIZE_128B: - hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr)); - break; - default: - break; - } -} - -/** - * @brief Writes the InitVector/InitCounter in IV registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param InitVector: Pointer to InitVector/InitCounter buffer - * @retval None - */ -static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector) -{ - uint32_t ivaddr = (uint32_t)InitVector; - - hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; - hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; - hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; - hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr)); -} - -/** - * @brief Process Data: Writes Input data in polling mode and read the Output data. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Input: Pointer to the Input buffer. - * @param Ilength: Length of the Input buffer, must be a multiple of 16 - * @param Output: Pointer to the returned buffer - * @param Timeout: Timeout value - * @retval None - */ -static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout) -{ - uint32_t tickstart = 0; - uint32_t i = 0; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - - for(i=0; (i < Ilength); i+=16) - { - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - /* Read the Output block from the OUT FIFO */ - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Sets the header phase - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Input: Pointer to the Input buffer. - * @param Ilength: Length of the Input buffer, must be a multiple of 16 - * @param Timeout: Timeout value - * @retval None - */ -static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout) -{ - uint32_t tickstart = 0; - uint32_t loopcounter = 0; - uint32_t headeraddr = (uint32_t)Input; - - /***************************** Header phase *********************************/ - if(hcryp->Init.HeaderSize != 0) - { - /* Select header phase */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - for(loopcounter = 0; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=16) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - } - - /* Wait until the complete message has been processed */ - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Sets the DMA configuration and start the DMA transfer. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param inputaddr: Address of the Input buffer - * @param Size: Size of the Input buffer, must be a multiple of 16 - * @param outputaddr: Address of the Output buffer - * @retval None - */ -static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) -{ - /* Set the CRYP DMA transfer complete callback */ - hcryp->hdmain->XferCpltCallback = CRYPEx_GCMCCM_DMAInCplt; - /* Set the DMA error callback */ - hcryp->hdmain->XferErrorCallback = CRYPEx_GCMCCM_DMAError; - - /* Set the CRYP DMA transfer complete callback */ - hcryp->hdmaout->XferCpltCallback = CRYPEx_GCMCCM_DMAOutCplt; - /* Set the DMA error callback */ - hcryp->hdmaout->XferErrorCallback = CRYPEx_GCMCCM_DMAError; - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* Enable the DMA In DMA Stream */ - HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4); - - /* Enable In DMA request */ - hcryp->Instance->DMACR = CRYP_DMACR_DIEN; - - /* Enable the DMA Out DMA Stream */ - HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4); - - /* Enable Out DMA request */ - hcryp->Instance->DMACR |= CRYP_DMACR_DOEN; -} - -/** - * @} - */ - -/* Exported functions---------------------------------------------------------*/ -/** @addtogroup CRYPEx_Exported_Functions - * @{ - */ - -/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions - * @brief Extended processing functions. - * -@verbatim - ============================================================================== - ##### Extended AES processing functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Encrypt plaintext using AES-128/192/256 using GCM and CCM chaining modes - (+) Decrypt cyphertext using AES-128/192/256 using GCM and CCM chaining modes - (+) Finish the processing. This function is available only for GCM and CCM - [..] Three processing methods are available: - (+) Polling mode - (+) Interrupt mode - (+) DMA mode - -@endverbatim - * @{ - */ - - -/** - * @brief Initializes the CRYP peripheral in AES CCM encryption mode then - * encrypt pPlainData. The cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) -{ - uint32_t tickstart = 0; - uint32_t headersize = hcryp->Init.HeaderSize; - uint32_t headeraddr = (uint32_t)hcryp->Init.Header; - uint32_t loopcounter = 0; - uint32_t bufferidx = 0; - uint8_t blockb0[16] = {0};/* Block B0 */ - uint8_t ctr[16] = {0}; /* Counter */ - uint32_t b0addr = (uint32_t)blockb0; - - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /************************ Formatting the header block *********************/ - if(headersize != 0) - { - /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */ - if(headersize < 65280) - { - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF); - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF); - headersize += 2; - } - else - { - /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */ - hcryp->Init.pScratch[bufferidx++] = 0xFF; - hcryp->Init.pScratch[bufferidx++] = 0xFE; - hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU; - headersize += 6; - } - /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */ - for(loopcounter = 0; loopcounter < headersize; loopcounter++) - { - hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter]; - } - /* Check if the header size is modulo 16 */ - if ((headersize % 16) != 0) - { - /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */ - for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++) - { - hcryp->Init.pScratch[loopcounter] = 0; - } - /* Set the header size to modulo 16 */ - headersize = ((headersize/16) + 1) * 16; - } - /* Set the pointer headeraddr to hcryp->Init.pScratch */ - headeraddr = (uint32_t)hcryp->Init.pScratch; - } - /*********************** Formatting the block B0 **************************/ - if(headersize != 0) - { - blockb0[0] = 0x40; - } - /* Flags byte */ - /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */ - blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3); - blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07); - - for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++) - { - blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter]; - } - for ( ; loopcounter < 13; loopcounter++) - { - blockb0[loopcounter+1] = 0; - } - - blockb0[14] = (Size >> 8); - blockb0[15] = (Size & 0xFF); - - /************************* Formatting the initial counter *****************/ - /* Byte 0: - Bits 7 and 6 are reserved and shall be set to 0 - Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter blocks - are distinct from B0 - Bits 0, 1, and 2 contain the same encoding of q as in B0 - */ - ctr[0] = blockb0[0] & 0x07; - /* byte 1 to NonceSize is the IV (Nonce) */ - for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++) - { - ctr[loopcounter] = blockb0[loopcounter]; - } - /* Set the LSB to 1 */ - ctr[15] |= 0x01; - - /* Set the key */ - CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES CCM mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT); - - /* Set the Initialization Vector */ - CRYPEx_GCMCCM_SetInitVector(hcryp, ctr); - - /* Select init phase */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - - b0addr = (uint32_t)blockb0; - /* Write the blockb0 block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(b0addr); - b0addr+=4; - hcryp->Instance->DR = *(uint32_t*)(b0addr); - b0addr+=4; - hcryp->Instance->DR = *(uint32_t*)(b0addr); - b0addr+=4; - hcryp->Instance->DR = *(uint32_t*)(b0addr); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - /***************************** Header phase *******************************/ - if(headersize != 0) - { - /* Select header phase */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)) - { - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - } - /* Write the header block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - } - /* Save formatted counter into the scratch buffer pScratch */ - for(loopcounter = 0; (loopcounter < 16); loopcounter++) - { - hcryp->Init.pScratch[loopcounter] = ctr[loopcounter]; - } - /* Reset bit 0 */ - hcryp->Init.pScratch[15] &= 0xfe; - - /* Select payload phase once the header phase is performed */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Write Plain Data and Get Cypher Data */ - if(CRYPEx_GCMCCM_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in AES GCM encryption mode then - * encrypt pPlainData. The cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES GCM mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT); - - /* Set the Initialization Vector */ - CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - - /* Set the header phase */ - if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); - - /* Select payload phase once the header phase is performed */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Write Plain Data and Get Cypher Data */ - if(CRYPEx_GCMCCM_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in AES GCM decryption mode then - * decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the cyphertext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES GCM decryption mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT); - - /* Set the Initialization Vector */ - CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - - /* Set the header phase */ - if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); - - /* Select payload phase once the header phase is performed */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Write Plain Data and Get Cypher Data */ - if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Computes the authentication TAG. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Size: Total length of the plain/cyphertext buffer - * @param AuthTag: Pointer to the authentication buffer - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout) -{ - uint32_t tickstart = 0; - uint64_t headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */ - uint64_t inputlength = Size * 8; /* input length in bits */ - uint32_t tagaddr = (uint32_t)AuthTag; - - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS) - { - /* Change the CRYP phase */ - hcryp->Phase = HAL_CRYP_PHASE_FINAL; - - /* Disable CRYP to start the final phase */ - __HAL_CRYP_DISABLE(hcryp); - - /* Select final phase */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* Write the number of bits in header (64 bits) followed by the number of bits - in the payload */ - if(hcryp->Init.DataType == CRYP_DATATYPE_1B) - { - hcryp->Instance->DR = __RBIT(headerlength >> 32); - hcryp->Instance->DR = __RBIT(headerlength); - hcryp->Instance->DR = __RBIT(inputlength >> 32); - hcryp->Instance->DR = __RBIT(inputlength); - } - else if(hcryp->Init.DataType == CRYP_DATATYPE_8B) - { - hcryp->Instance->DR = __REV(headerlength >> 32); - hcryp->Instance->DR = __REV(headerlength); - hcryp->Instance->DR = __REV(inputlength >> 32); - hcryp->Instance->DR = __REV(inputlength); - } - else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) - { - hcryp->Instance->DR = __ROR((uint32_t)(headerlength >> 32), 16); - hcryp->Instance->DR = __ROR((uint32_t)headerlength, 16); - hcryp->Instance->DR = __ROR((uint32_t)(inputlength >> 32), 16); - hcryp->Instance->DR = __ROR((uint32_t)inputlength, 16); - } - else if(hcryp->Init.DataType == CRYP_DATATYPE_32B) - { - hcryp->Instance->DR = (uint32_t)(headerlength >> 32); - hcryp->Instance->DR = (uint32_t)(headerlength); - hcryp->Instance->DR = (uint32_t)(inputlength >> 32); - hcryp->Instance->DR = (uint32_t)(inputlength); - } - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - - /* Read the Auth TAG in the IN FIFO */ - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT; - tagaddr+=4; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT; - tagaddr+=4; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT; - tagaddr+=4; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT; - } - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Computes the authentication TAG for AES CCM mode. - * @note This API is called after HAL_AES_CCM_Encrypt()/HAL_AES_CCM_Decrypt() - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param AuthTag: Pointer to the authentication buffer - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout) -{ - uint32_t tickstart = 0; - uint32_t tagaddr = (uint32_t)AuthTag; - uint32_t ctraddr = (uint32_t)hcryp->Init.pScratch; - uint32_t temptag[4] = {0}; /* Temporary TAG (MAC) */ - uint32_t loopcounter; - - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS) - { - /* Change the CRYP phase */ - hcryp->Phase = HAL_CRYP_PHASE_FINAL; - - /* Disable CRYP to start the final phase */ - __HAL_CRYP_DISABLE(hcryp); - - /* Select final phase */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* Write the counter block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)ctraddr; - ctraddr+=4; - hcryp->Instance->DR = *(uint32_t*)ctraddr; - ctraddr+=4; - hcryp->Instance->DR = *(uint32_t*)ctraddr; - ctraddr+=4; - hcryp->Instance->DR = *(uint32_t*)ctraddr; - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - - /* Read the Auth TAG in the IN FIFO */ - temptag[0] = hcryp->Instance->DOUT; - temptag[1] = hcryp->Instance->DOUT; - temptag[2] = hcryp->Instance->DOUT; - temptag[3] = hcryp->Instance->DOUT; - } - - /* Copy temporary authentication TAG in user TAG buffer */ - for(loopcounter = 0; loopcounter < hcryp->Init.TagSize ; loopcounter++) - { - /* Set the authentication TAG buffer */ - *((uint8_t*)tagaddr+loopcounter) = *((uint8_t*)temptag+loopcounter); - } - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in AES CCM decryption mode then - * decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) -{ - uint32_t tickstart = 0; - uint32_t headersize = hcryp->Init.HeaderSize; - uint32_t headeraddr = (uint32_t)hcryp->Init.Header; - uint32_t loopcounter = 0; - uint32_t bufferidx = 0; - uint8_t blockb0[16] = {0};/* Block B0 */ - uint8_t ctr[16] = {0}; /* Counter */ - uint32_t b0addr = (uint32_t)blockb0; - - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /************************ Formatting the header block *********************/ - if(headersize != 0) - { - /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */ - if(headersize < 65280) - { - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU); - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU); - headersize += 2; - } - else - { - /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */ - hcryp->Init.pScratch[bufferidx++] = 0xFFU; - hcryp->Init.pScratch[bufferidx++] = 0xFEU; - hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU; - headersize += 6; - } - /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */ - for(loopcounter = 0; loopcounter < headersize; loopcounter++) - { - hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter]; - } - /* Check if the header size is modulo 16 */ - if ((headersize % 16) != 0) - { - /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */ - for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++) - { - hcryp->Init.pScratch[loopcounter] = 0; - } - /* Set the header size to modulo 16 */ - headersize = ((headersize/16) + 1) * 16; - } - /* Set the pointer headeraddr to hcryp->Init.pScratch */ - headeraddr = (uint32_t)hcryp->Init.pScratch; - } - /*********************** Formatting the block B0 **************************/ - if(headersize != 0) - { - blockb0[0] = 0x40; - } - /* Flags byte */ - /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */ - blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3); - blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07); - - for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++) - { - blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter]; - } - for ( ; loopcounter < 13; loopcounter++) - { - blockb0[loopcounter+1] = 0; - } - - blockb0[14] = (Size >> 8); - blockb0[15] = (Size & 0xFF); - - /************************* Formatting the initial counter *****************/ - /* Byte 0: - Bits 7 and 6 are reserved and shall be set to 0 - Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter - blocks are distinct from B0 - Bits 0, 1, and 2 contain the same encoding of q as in B0 - */ - ctr[0] = blockb0[0] & 0x07; - /* byte 1 to NonceSize is the IV (Nonce) */ - for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++) - { - ctr[loopcounter] = blockb0[loopcounter]; - } - /* Set the LSB to 1 */ - ctr[15] |= 0x01; - - /* Set the key */ - CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES CCM mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT); - - /* Set the Initialization Vector */ - CRYPEx_GCMCCM_SetInitVector(hcryp, ctr); - - /* Select init phase */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - - b0addr = (uint32_t)blockb0; - /* Write the blockb0 block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(b0addr); - b0addr+=4; - hcryp->Instance->DR = *(uint32_t*)(b0addr); - b0addr+=4; - hcryp->Instance->DR = *(uint32_t*)(b0addr); - b0addr+=4; - hcryp->Instance->DR = *(uint32_t*)(b0addr); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - /***************************** Header phase *******************************/ - if(headersize != 0) - { - /* Select header phase */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - - /* Enable Crypto processor */ - __HAL_CRYP_ENABLE(hcryp); - - for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - /* Write the header block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - } - /* Save formatted counter into the scratch buffer pScratch */ - for(loopcounter = 0; (loopcounter < 16); loopcounter++) - { - hcryp->Init.pScratch[loopcounter] = ctr[loopcounter]; - } - /* Reset bit 0 */ - hcryp->Init.pScratch[15] &= 0xfe; - /* Select payload phase once the header phase is performed */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Write Plain Data and Get Cypher Data */ - if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in AES GCM encryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t tickstart = 0; - uint32_t inputaddr; - uint32_t outputaddr; - - if(hcryp->State == HAL_CRYP_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Get the buffer addresses and sizes */ - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pPlainData; - hcryp->pCrypOutBuffPtr = pCypherData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES GCM mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT); - - /* Set the Initialization Vector */ - CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Enable CRYP to start the init phase */ - __HAL_CRYP_ENABLE(hcryp); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) - { - /* Check for the Timeout */ - - if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - - } - } - - /* Set the header phase */ - if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK) - { - return HAL_TIMEOUT; - } - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); - - /* Select payload phase once the header phase is performed */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - if(Size != 0) - { - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - } - else - { - /* Process Locked */ - __HAL_UNLOCK(hcryp); - /* Change the CRYP state and phase */ - hcryp->State = HAL_CRYP_STATE_READY; - } - /* Return function status */ - return HAL_OK; - } - else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI)) - { - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - if(hcryp->CrypInCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - /* Call the Input data transfer complete callback */ - HAL_CRYP_InCpltCallback(hcryp); - } - } - else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI)) - { - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; - if(hcryp->CrypOutCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Call Input transfer complete callback */ - HAL_CRYP_OutCpltCallback(hcryp); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t tickstart = 0; - uint32_t inputaddr; - uint32_t outputaddr; - - uint32_t headersize = hcryp->Init.HeaderSize; - uint32_t headeraddr = (uint32_t)hcryp->Init.Header; - uint32_t loopcounter = 0; - uint32_t bufferidx = 0; - uint8_t blockb0[16] = {0};/* Block B0 */ - uint8_t ctr[16] = {0}; /* Counter */ - uint32_t b0addr = (uint32_t)blockb0; - - if(hcryp->State == HAL_CRYP_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pPlainData; - hcryp->pCrypOutBuffPtr = pCypherData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /************************ Formatting the header block *******************/ - if(headersize != 0) - { - /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */ - if(headersize < 65280) - { - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU); - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU); - headersize += 2; - } - else - { - /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */ - hcryp->Init.pScratch[bufferidx++] = 0xFFU; - hcryp->Init.pScratch[bufferidx++] = 0xFEU; - hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU; - headersize += 6; - } - /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */ - for(loopcounter = 0; loopcounter < headersize; loopcounter++) - { - hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter]; - } - /* Check if the header size is modulo 16 */ - if ((headersize % 16) != 0) - { - /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */ - for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++) - { - hcryp->Init.pScratch[loopcounter] = 0; - } - /* Set the header size to modulo 16 */ - headersize = ((headersize/16) + 1) * 16; - } - /* Set the pointer headeraddr to hcryp->Init.pScratch */ - headeraddr = (uint32_t)hcryp->Init.pScratch; - } - /*********************** Formatting the block B0 ************************/ - if(headersize != 0) - { - blockb0[0] = 0x40; - } - /* Flags byte */ - /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */ - blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3); - blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07); - - for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++) - { - blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter]; - } - for ( ; loopcounter < 13; loopcounter++) - { - blockb0[loopcounter+1] = 0; - } - - blockb0[14] = (Size >> 8); - blockb0[15] = (Size & 0xFF); - - /************************* Formatting the initial counter ***************/ - /* Byte 0: - Bits 7 and 6 are reserved and shall be set to 0 - Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter - blocks are distinct from B0 - Bits 0, 1, and 2 contain the same encoding of q as in B0 - */ - ctr[0] = blockb0[0] & 0x07; - /* byte 1 to NonceSize is the IV (Nonce) */ - for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++) - { - ctr[loopcounter] = blockb0[loopcounter]; - } - /* Set the LSB to 1 */ - ctr[15] |= 0x01; - - /* Set the key */ - CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES CCM mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT); - - /* Set the Initialization Vector */ - CRYPEx_GCMCCM_SetInitVector(hcryp, ctr); - - /* Select init phase */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - - b0addr = (uint32_t)blockb0; - /* Write the blockb0 block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(b0addr); - b0addr+=4; - hcryp->Instance->DR = *(uint32_t*)(b0addr); - b0addr+=4; - hcryp->Instance->DR = *(uint32_t*)(b0addr); - b0addr+=4; - hcryp->Instance->DR = *(uint32_t*)(b0addr); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - /***************************** Header phase *****************************/ - if(headersize != 0) - { - /* Select header phase */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - - /* Enable Crypto processor */ - __HAL_CRYP_ENABLE(hcryp); - - for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - /* Write the header block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - /* Save formatted counter into the scratch buffer pScratch */ - for(loopcounter = 0; (loopcounter < 16); loopcounter++) - { - hcryp->Init.pScratch[loopcounter] = ctr[loopcounter]; - } - /* Reset bit 0 */ - hcryp->Init.pScratch[15] &= 0xfe; - - /* Select payload phase once the header phase is performed */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - if(Size != 0) - { - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - } - else - { - /* Change the CRYP state and phase */ - hcryp->State = HAL_CRYP_STATE_READY; - } - - /* Return function status */ - return HAL_OK; - } - else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI)) - { - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - if(hcryp->CrypInCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - /* Call Input transfer complete callback */ - HAL_CRYP_InCpltCallback(hcryp); - } - } - else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI)) - { - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; - if(hcryp->CrypOutCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Call Input transfer complete callback */ - HAL_CRYP_OutCpltCallback(hcryp); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in AES GCM decryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the cyphertext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t tickstart = 0; - uint32_t inputaddr; - uint32_t outputaddr; - - if(hcryp->State == HAL_CRYP_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Get the buffer addresses and sizes */ - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pCypherData; - hcryp->pCrypOutBuffPtr = pPlainData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES GCM decryption mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT); - - /* Set the Initialization Vector */ - CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Enable CRYP to start the init phase */ - __HAL_CRYP_ENABLE(hcryp); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - - /* Set the header phase */ - if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK) - { - return HAL_TIMEOUT; - } - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); - - /* Select payload phase once the header phase is performed */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - if(Size != 0) - { - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - } - else - { - /* Process Locked */ - __HAL_UNLOCK(hcryp); - /* Change the CRYP state and phase */ - hcryp->State = HAL_CRYP_STATE_READY; - } - - /* Return function status */ - return HAL_OK; - } - else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI)) - { - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - if(hcryp->CrypInCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - /* Call the Input data transfer complete callback */ - HAL_CRYP_InCpltCallback(hcryp); - } - } - else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI)) - { - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; - if(hcryp->CrypOutCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Call Input transfer complete callback */ - HAL_CRYP_OutCpltCallback(hcryp); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in AES CCM decryption mode using interrupt - * then decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t inputaddr; - uint32_t outputaddr; - uint32_t tickstart = 0; - uint32_t headersize = hcryp->Init.HeaderSize; - uint32_t headeraddr = (uint32_t)hcryp->Init.Header; - uint32_t loopcounter = 0; - uint32_t bufferidx = 0; - uint8_t blockb0[16] = {0};/* Block B0 */ - uint8_t ctr[16] = {0}; /* Counter */ - uint32_t b0addr = (uint32_t)blockb0; - - if(hcryp->State == HAL_CRYP_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pCypherData; - hcryp->pCrypOutBuffPtr = pPlainData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /************************ Formatting the header block *******************/ - if(headersize != 0) - { - /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */ - if(headersize < 65280) - { - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU); - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU); - headersize += 2; - } - else - { - /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */ - hcryp->Init.pScratch[bufferidx++] = 0xFFU; - hcryp->Init.pScratch[bufferidx++] = 0xFEU; - hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU; - headersize += 6; - } - /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */ - for(loopcounter = 0; loopcounter < headersize; loopcounter++) - { - hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter]; - } - /* Check if the header size is modulo 16 */ - if ((headersize % 16) != 0) - { - /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */ - for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++) - { - hcryp->Init.pScratch[loopcounter] = 0; - } - /* Set the header size to modulo 16 */ - headersize = ((headersize/16) + 1) * 16; - } - /* Set the pointer headeraddr to hcryp->Init.pScratch */ - headeraddr = (uint32_t)hcryp->Init.pScratch; - } - /*********************** Formatting the block B0 ************************/ - if(headersize != 0) - { - blockb0[0] = 0x40; - } - /* Flags byte */ - /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */ - blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3); - blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07); - - for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++) - { - blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter]; - } - for ( ; loopcounter < 13; loopcounter++) - { - blockb0[loopcounter+1] = 0; - } - - blockb0[14] = (Size >> 8); - blockb0[15] = (Size & 0xFF); - - /************************* Formatting the initial counter ***************/ - /* Byte 0: - Bits 7 and 6 are reserved and shall be set to 0 - Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter - blocks are distinct from B0 - Bits 0, 1, and 2 contain the same encoding of q as in B0 - */ - ctr[0] = blockb0[0] & 0x07; - /* byte 1 to NonceSize is the IV (Nonce) */ - for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++) - { - ctr[loopcounter] = blockb0[loopcounter]; - } - /* Set the LSB to 1 */ - ctr[15] |= 0x01; - - /* Set the key */ - CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES CCM mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT); - - /* Set the Initialization Vector */ - CRYPEx_GCMCCM_SetInitVector(hcryp, ctr); - - /* Select init phase */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - - b0addr = (uint32_t)blockb0; - /* Write the blockb0 block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(b0addr); - b0addr+=4; - hcryp->Instance->DR = *(uint32_t*)(b0addr); - b0addr+=4; - hcryp->Instance->DR = *(uint32_t*)(b0addr); - b0addr+=4; - hcryp->Instance->DR = *(uint32_t*)(b0addr); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - /***************************** Header phase *****************************/ - if(headersize != 0) - { - /* Select header phase */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - - /* Enable Crypto processor */ - __HAL_CRYP_ENABLE(hcryp); - - for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - /* Write the header block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - /* Save formatted counter into the scratch buffer pScratch */ - for(loopcounter = 0; (loopcounter < 16); loopcounter++) - { - hcryp->Init.pScratch[loopcounter] = ctr[loopcounter]; - } - /* Reset bit 0 */ - hcryp->Init.pScratch[15] &= 0xfe; - /* Select payload phase once the header phase is performed */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* Return function status */ - return HAL_OK; - } - else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI)) - { - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - /* Write the Input block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - if(hcryp->CrypInCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - /* Call the Input data transfer complete callback */ - HAL_CRYP_InCpltCallback(hcryp); - } - } - else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI)) - { - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - outputaddr+=4; - *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT; - hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; - if(hcryp->CrypOutCount == 0) - { - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Call Input transfer complete callback */ - HAL_CRYP_OutCpltCallback(hcryp); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in AES GCM encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t tickstart = 0; - uint32_t inputaddr; - uint32_t outputaddr; - - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pPlainData; - outputaddr = (uint32_t)pCypherData; - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES GCM mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT); - - /* Set the Initialization Vector */ - CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Enable CRYP to start the init phase */ - __HAL_CRYP_ENABLE(hcryp); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the header phase */ - if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK) - { - return HAL_TIMEOUT; - } - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); - - /* Select payload phase once the header phase is performed */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Set the input and output addresses and start DMA transfer */ - CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Unlock process */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t tickstart = 0; - uint32_t inputaddr; - uint32_t outputaddr; - uint32_t headersize; - uint32_t headeraddr; - uint32_t loopcounter = 0; - uint32_t bufferidx = 0; - uint8_t blockb0[16] = {0};/* Block B0 */ - uint8_t ctr[16] = {0}; /* Counter */ - uint32_t b0addr = (uint32_t)blockb0; - - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pPlainData; - outputaddr = (uint32_t)pCypherData; - - headersize = hcryp->Init.HeaderSize; - headeraddr = (uint32_t)hcryp->Init.Header; - - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pPlainData; - hcryp->pCrypOutBuffPtr = pCypherData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /************************ Formatting the header block *******************/ - if(headersize != 0) - { - /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */ - if(headersize < 65280) - { - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU); - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU); - headersize += 2; - } - else - { - /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */ - hcryp->Init.pScratch[bufferidx++] = 0xFFU; - hcryp->Init.pScratch[bufferidx++] = 0xFEU; - hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU; - headersize += 6; - } - /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */ - for(loopcounter = 0; loopcounter < headersize; loopcounter++) - { - hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter]; - } - /* Check if the header size is modulo 16 */ - if ((headersize % 16) != 0) - { - /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */ - for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++) - { - hcryp->Init.pScratch[loopcounter] = 0; - } - /* Set the header size to modulo 16 */ - headersize = ((headersize/16) + 1) * 16; - } - /* Set the pointer headeraddr to hcryp->Init.pScratch */ - headeraddr = (uint32_t)hcryp->Init.pScratch; - } - /*********************** Formatting the block B0 ************************/ - if(headersize != 0) - { - blockb0[0] = 0x40; - } - /* Flags byte */ - /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */ - blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3); - blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07); - - for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++) - { - blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter]; - } - for ( ; loopcounter < 13; loopcounter++) - { - blockb0[loopcounter+1] = 0; - } - - blockb0[14] = (Size >> 8); - blockb0[15] = (Size & 0xFF); - - /************************* Formatting the initial counter ***************/ - /* Byte 0: - Bits 7 and 6 are reserved and shall be set to 0 - Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter - blocks are distinct from B0 - Bits 0, 1, and 2 contain the same encoding of q as in B0 - */ - ctr[0] = blockb0[0] & 0x07; - /* byte 1 to NonceSize is the IV (Nonce) */ - for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++) - { - ctr[loopcounter] = blockb0[loopcounter]; - } - /* Set the LSB to 1 */ - ctr[15] |= 0x01; - - /* Set the key */ - CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES CCM mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT); - - /* Set the Initialization Vector */ - CRYPEx_GCMCCM_SetInitVector(hcryp, ctr); - - /* Select init phase */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - - b0addr = (uint32_t)blockb0; - /* Write the blockb0 block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(b0addr); - b0addr+=4; - hcryp->Instance->DR = *(uint32_t*)(b0addr); - b0addr+=4; - hcryp->Instance->DR = *(uint32_t*)(b0addr); - b0addr+=4; - hcryp->Instance->DR = *(uint32_t*)(b0addr); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - /***************************** Header phase *****************************/ - if(headersize != 0) - { - /* Select header phase */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - - /* Enable Crypto processor */ - __HAL_CRYP_ENABLE(hcryp); - - for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - /* Write the header block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - /* Save formatted counter into the scratch buffer pScratch */ - for(loopcounter = 0; (loopcounter < 16); loopcounter++) - { - hcryp->Init.pScratch[loopcounter] = ctr[loopcounter]; - } - /* Reset bit 0 */ - hcryp->Init.pScratch[15] &= 0xfe; - - /* Select payload phase once the header phase is performed */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Set the input and output addresses and start DMA transfer */ - CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Unlock process */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES GCM decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer. - * @param Size: Length of the cyphertext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t tickstart = 0; - uint32_t inputaddr; - uint32_t outputaddr; - - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pCypherData; - outputaddr = (uint32_t)pPlainData; - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES GCM decryption mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT); - - /* Set the Initialization Vector */ - CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect); - - /* Enable CRYP to start the init phase */ - __HAL_CRYP_ENABLE(hcryp); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - - /* Set the header phase */ - if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK) - { - return HAL_TIMEOUT; - } - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); - - /* Select payload phase once the header phase is performed */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Set the input and output addresses and start DMA transfer */ - CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Unlock process */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES CCM decryption mode using DMA - * then decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t tickstart = 0; - uint32_t inputaddr; - uint32_t outputaddr; - uint32_t headersize; - uint32_t headeraddr; - uint32_t loopcounter = 0; - uint32_t bufferidx = 0; - uint8_t blockb0[16] = {0};/* Block B0 */ - uint8_t ctr[16] = {0}; /* Counter */ - uint32_t b0addr = (uint32_t)blockb0; - - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pCypherData; - outputaddr = (uint32_t)pPlainData; - - headersize = hcryp->Init.HeaderSize; - headeraddr = (uint32_t)hcryp->Init.Header; - - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pCypherData; - hcryp->pCrypOutBuffPtr = pPlainData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /************************ Formatting the header block *******************/ - if(headersize != 0) - { - /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */ - if(headersize < 65280) - { - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU); - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU); - headersize += 2; - } - else - { - /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */ - hcryp->Init.pScratch[bufferidx++] = 0xFFU; - hcryp->Init.pScratch[bufferidx++] = 0xFEU; - hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU; - headersize += 6; - } - /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */ - for(loopcounter = 0; loopcounter < headersize; loopcounter++) - { - hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter]; - } - /* Check if the header size is modulo 16 */ - if ((headersize % 16) != 0) - { - /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */ - for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++) - { - hcryp->Init.pScratch[loopcounter] = 0; - } - /* Set the header size to modulo 16 */ - headersize = ((headersize/16) + 1) * 16; - } - /* Set the pointer headeraddr to hcryp->Init.pScratch */ - headeraddr = (uint32_t)hcryp->Init.pScratch; - } - /*********************** Formatting the block B0 ************************/ - if(headersize != 0) - { - blockb0[0] = 0x40; - } - /* Flags byte */ - /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */ - blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3); - blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07); - - for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++) - { - blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter]; - } - for ( ; loopcounter < 13; loopcounter++) - { - blockb0[loopcounter+1] = 0; - } - - blockb0[14] = (Size >> 8); - blockb0[15] = (Size & 0xFF); - - /************************* Formatting the initial counter ***************/ - /* Byte 0: - Bits 7 and 6 are reserved and shall be set to 0 - Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter - blocks are distinct from B0 - Bits 0, 1, and 2 contain the same encoding of q as in B0 - */ - ctr[0] = blockb0[0] & 0x07; - /* byte 1 to NonceSize is the IV (Nonce) */ - for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++) - { - ctr[loopcounter] = blockb0[loopcounter]; - } - /* Set the LSB to 1 */ - ctr[15] |= 0x01; - - /* Set the key */ - CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize); - - /* Set the CRYP peripheral in AES CCM mode */ - __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT); - - /* Set the Initialization Vector */ - CRYPEx_GCMCCM_SetInitVector(hcryp, ctr); - - /* Select init phase */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - - b0addr = (uint32_t)blockb0; - /* Write the blockb0 block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(b0addr); - b0addr+=4; - hcryp->Instance->DR = *(uint32_t*)(b0addr); - b0addr+=4; - hcryp->Instance->DR = *(uint32_t*)(b0addr); - b0addr+=4; - hcryp->Instance->DR = *(uint32_t*)(b0addr); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) - { - /* Check for the Timeout */ - - if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - - } - } - /***************************** Header phase *****************************/ - if(headersize != 0) - { - /* Select header phase */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - - /* Enable Crypto processor */ - __HAL_CRYP_ENABLE(hcryp); - - for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - /* Write the header block in the IN FIFO */ - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - hcryp->Instance->DR = *(uint32_t*)(headeraddr); - headeraddr+=4; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - /* Save formatted counter into the scratch buffer pScratch */ - for(loopcounter = 0; (loopcounter < 16); loopcounter++) - { - hcryp->Init.pScratch[loopcounter] = ctr[loopcounter]; - } - /* Reset bit 0 */ - hcryp->Init.pScratch[15] &= 0xfe; - /* Select payload phase once the header phase is performed */ - __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - /* Flush FIFO */ - __HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - /* Set the input and output addresses and start DMA transfer */ - CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Unlock process */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @} - */ - -/** @defgroup CRYPEx_Exported_Functions_Group2 CRYPEx IRQ handler management - * @brief CRYPEx IRQ handler. - * -@verbatim - ============================================================================== - ##### CRYPEx IRQ handler management ##### - ============================================================================== -[..] This section provides CRYPEx IRQ handler function. - -@endverbatim - * @{ - */ - -/** - * @brief This function handles CRYPEx interrupt request. - * @param hcryp: pointer to a CRYPEx_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval None - */ -void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp) -{ - switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION) - { - case CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT: - HAL_CRYPEx_AESGCM_Encrypt_IT(hcryp, NULL, 0, NULL); - break; - - case CRYP_CR_ALGOMODE_AES_GCM_DECRYPT: - HAL_CRYPEx_AESGCM_Decrypt_IT(hcryp, NULL, 0, NULL); - break; - - case CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT: - HAL_CRYPEx_AESCCM_Encrypt_IT(hcryp, NULL, 0, NULL); - break; - - case CRYP_CR_ALGOMODE_AES_CCM_DECRYPT: - HAL_CRYPEx_AESCCM_Decrypt_IT(hcryp, NULL, 0, NULL); - break; - - default: - break; - } -} - -/** - * @} - */ - -/** - * @} - */ -#endif /* HAL_CRYP_MODULE_ENABLED */ - -/** - * @} - */ -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.c deleted file mode 100644 index 5a696d5..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.c +++ /dev/null @@ -1,967 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dac.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief DAC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Digital to Analog Converter (DAC) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - * - * - @verbatim - ============================================================================== - ##### DAC Peripheral features ##### - ============================================================================== - [..] - *** DAC Channels *** - ==================== - [..] - The device integrates two 12-bit Digital Analog Converters that can - be used independently or simultaneously (dual mode): - (#) DAC channel1 with DAC_OUT1 (PA4) as output - (#) DAC channel2 with DAC_OUT2 (PA5) as output - - *** DAC Triggers *** - ==================== - [..] - Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE - and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. - [..] - Digital to Analog conversion can be triggered by: - (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_TRIGGER_EXT_IT9. - The used pin (GPIOx_Pin9) must be configured in input mode. - - (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 - (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...) - - (#) Software using DAC_TRIGGER_SOFTWARE - - *** DAC Buffer mode feature *** - =============================== - [..] - Each DAC channel integrates an output buffer that can be used to - reduce the output impedance, and to drive external loads directly - without having to add an external operational amplifier. - To enable, the output buffer use - sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; - [..] - (@) Refer to the device datasheet for more details about output - impedance value with and without output buffer. - - *** DAC wave generation feature *** - =================================== - [..] - Both DAC channels can be used to generate - (#) Noise wave using HAL_DACEx_NoiseWaveGenerate() - (#) Triangle wave using HAL_DACEx_TriangleWaveGenerate() - - *** DAC data format *** - ======================= - [..] - The DAC data format can be: - (#) 8-bit right alignment using DAC_ALIGN_8B_R - (#) 12-bit left alignment using DAC_ALIGN_12B_L - (#) 12-bit right alignment using DAC_ALIGN_12B_R - - *** DAC data value to voltage correspondence *** - ================================================ - [..] - The analog output voltage on each DAC channel pin is determined - by the following equation: - DAC_OUTx = VREF+ * DOR / 4095 - with DOR is the Data Output Register - VEF+ is the input voltage reference (refer to the device datasheet) - e.g. To set DAC_OUT1 to 0.7V, use - Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V - - *** DMA requests *** - ===================== - [..] - A DMA1 request can be generated when an external trigger (but not - a software trigger) occurs if DMA1 requests are enabled using - HAL_DAC_Start_DMA() - [..] - DMA1 requests are mapped as following: - (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be - already configured - (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be - already configured - - -@- For Dual mode and specific signal (Triangle and noise) generation please - refer to Extension Features Driver description - - - ##### How to use this driver ##### - ============================================================================== - [..] - (+) DAC APB clock must be enabled to get write access to DAC - registers using HAL_DAC_Init() - (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode. - (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function. - (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions - - *** Polling mode IO operation *** - ================================= - [..] - (+) Start the DAC peripheral using HAL_DAC_Start() - (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function. - (+) Stop the DAC peripheral using HAL_DAC_Stop() - - - *** DMA mode IO operation *** - ============================== - [..] - (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length - of data to be transferred at each end of conversion - (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2() - function is executed and user can add his own code by customization of function pointer - HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2 - (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can - add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 - (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA() - - - *** DAC HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in DAC HAL driver. - - (+) __HAL_DAC_ENABLE : Enable the DAC peripheral - (+) __HAL_DAC_DISABLE : Disable the DAC peripheral - (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags - (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status - - [..] - (@) You can refer to the DAC HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup DAC DAC - * @brief DAC driver modules - * @{ - */ - -#ifdef HAL_DAC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @addtogroup DAC_Private_Functions - * @{ - */ -/* Private function prototypes -----------------------------------------------*/ -static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); -static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); -static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup DAC_Exported_Functions DAC Exported Functions - * @{ - */ - -/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the DAC. - (+) De-initialize the DAC. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the DAC peripheral according to the specified parameters - * in the DAC_InitStruct. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) -{ - /* Check DAC handle */ - if(hdac == NULL) - { - return HAL_ERROR; - } - /* Check the parameters */ - assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); - - if(hdac->State == HAL_DAC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hdac->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ - HAL_DAC_MspInit(hdac); - } - - /* Initialize the DAC state*/ - hdac->State = HAL_DAC_STATE_BUSY; - - /* Set DAC error code to none */ - hdac->ErrorCode = HAL_DAC_ERROR_NONE; - - /* Initialize the DAC state*/ - hdac->State = HAL_DAC_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) -{ - /* Check DAC handle */ - if(hdac == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_BUSY; - - /* DeInit the low level hardware */ - HAL_DAC_MspDeInit(hdac); - - /* Set DAC error code to none */ - hdac->ErrorCode = HAL_DAC_ERROR_NONE; - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hdac); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdac); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdac); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup DAC_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Start conversion. - (+) Stop conversion. - (+) Start conversion and enable DMA transfer. - (+) Stop conversion and disable DMA transfer. - (+) Get result of conversion. - -@endverbatim - * @{ - */ - -/** - * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) -{ - uint32_t tmp1 = 0, tmp2 = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - - /* Process locked */ - __HAL_LOCK(hdac); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_BUSY; - - /* Enable the Peripheral */ - __HAL_DAC_ENABLE(hdac, Channel); - - if(Channel == DAC_CHANNEL_1) - { - tmp1 = hdac->Instance->CR & DAC_CR_TEN1; - tmp2 = hdac->Instance->CR & DAC_CR_TSEL1; - /* Check if software trigger enabled */ - if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1)) - { - /* Enable the selected DAC software conversion */ - hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1; - } - } - else - { - tmp1 = hdac->Instance->CR & DAC_CR_TEN2; - tmp2 = hdac->Instance->CR & DAC_CR_TSEL2; - /* Check if software trigger enabled */ - if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2)) - { - /* Enable the selected DAC software conversion*/ - hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2; - } - } - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdac); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - - /* Disable the Peripheral */ - __HAL_DAC_DISABLE(hdac, Channel); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param pData: The destination peripheral Buffer address. - * @param Length: The length of data to be transferred from memory to DAC peripheral - * @param Alignment: Specifies the data alignment for DAC channel. - * This parameter can be one of the following values: - * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected - * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected - * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - assert_param(IS_DAC_ALIGN(Alignment)); - - /* Process locked */ - __HAL_LOCK(hdac); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_BUSY; - - if(Channel == DAC_CHANNEL_1) - { - /* Set the DMA transfer complete callback for channel1 */ - hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; - - /* Set the DMA half transfer complete callback for channel1 */ - hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; - - /* Set the DMA error callback for channel1 */ - hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; - - /* Enable the selected DAC channel1 DMA request */ - hdac->Instance->CR |= DAC_CR_DMAEN1; - - /* Case of use of channel 1 */ - switch(Alignment) - { - case DAC_ALIGN_12B_R: - /* Get DHR12R1 address */ - tmpreg = (uint32_t)&hdac->Instance->DHR12R1; - break; - case DAC_ALIGN_12B_L: - /* Get DHR12L1 address */ - tmpreg = (uint32_t)&hdac->Instance->DHR12L1; - break; - case DAC_ALIGN_8B_R: - /* Get DHR8R1 address */ - tmpreg = (uint32_t)&hdac->Instance->DHR8R1; - break; - default: - break; - } - } - else - { - /* Set the DMA transfer complete callback for channel2 */ - hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2; - - /* Set the DMA half transfer complete callback for channel2 */ - hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2; - - /* Set the DMA error callback for channel2 */ - hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; - - /* Enable the selected DAC channel2 DMA request */ - hdac->Instance->CR |= DAC_CR_DMAEN2; - - /* Case of use of channel 2 */ - switch(Alignment) - { - case DAC_ALIGN_12B_R: - /* Get DHR12R2 address */ - tmpreg = (uint32_t)&hdac->Instance->DHR12R2; - break; - case DAC_ALIGN_12B_L: - /* Get DHR12L2 address */ - tmpreg = (uint32_t)&hdac->Instance->DHR12L2; - break; - case DAC_ALIGN_8B_R: - /* Get DHR8R2 address */ - tmpreg = (uint32_t)&hdac->Instance->DHR8R2; - break; - default: - break; - } - } - - /* Enable the DMA Stream */ - if(Channel == DAC_CHANNEL_1) - { - /* Enable the DAC DMA underrun interrupt */ - __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); - } - else - { - /* Enable the DAC DMA underrun interrupt */ - __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); - } - - /* Enable the Peripheral */ - __HAL_DAC_ENABLE(hdac, Channel); - - /* Process Unlocked */ - __HAL_UNLOCK(hdac); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - - /* Disable the selected DAC channel DMA request */ - hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel); - - /* Disable the Peripheral */ - __HAL_DAC_DISABLE(hdac, Channel); - - /* Disable the DMA Channel */ - /* Channel1 is used */ - if(Channel == DAC_CHANNEL_1) - { - status = HAL_DMA_Abort(hdac->DMA_Handle1); - } - else /* Channel2 is used for */ - { - status = HAL_DMA_Abort(hdac->DMA_Handle2); - } - - /* Check if DMA Channel effectively disabled */ - if(status != HAL_OK) - { - /* Update DAC state machine to error */ - hdac->State = HAL_DAC_STATE_ERROR; - } - else - { - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - } - - /* Return function status */ - return status; -} - -/** - * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval The selected DAC channel data output value. - */ -uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - - /* Returns the DAC channel data output register value */ - if(Channel == DAC_CHANNEL_1) - { - return hdac->Instance->DOR1; - } - else - { - return hdac->Instance->DOR2; - } -} - -/** - * @brief Handles DAC interrupt request - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) -{ - /* Check underrun channel 1 flag */ - if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) - { - /* Change DAC state to error state */ - hdac->State = HAL_DAC_STATE_ERROR; - - /* Set DAC error code to channel1 DMA underrun error */ - hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1; - - /* Clear the underrun flag */ - __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1); - - /* Disable the selected DAC channel1 DMA request */ - hdac->Instance->CR &= ~DAC_CR_DMAEN1; - - /* Error callback */ - HAL_DAC_DMAUnderrunCallbackCh1(hdac); - } - /* Check underrun channel 2 flag */ - if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) - { - /* Change DAC state to error state */ - hdac->State = HAL_DAC_STATE_ERROR; - - /* Set DAC error code to channel2 DMA underrun error */ - hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2; - - /* Clear the underrun flag */ - __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2); - - /* Disable the selected DAC channel1 DMA request */ - hdac->Instance->CR &= ~DAC_CR_DMAEN2; - - /* Error callback */ - HAL_DACEx_DMAUnderrunCallbackCh2(hdac); - } -} - -/** - * @brief Conversion complete callback in non blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdac); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_ConvCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Conversion half DMA transfer callback in non blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdac); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file - */ -} - -/** - * @brief Error DAC callback for Channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdac); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file - */ -} - -/** - * @brief DMA underrun DAC callback for channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdac); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Configure channels. - (+) Set the specified data holding register value for DAC channel. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param sConfig: DAC configuration structure. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - - /* Check the DAC parameters */ - assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); - assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); - assert_param(IS_DAC_CHANNEL(Channel)); - - /* Process locked */ - __HAL_LOCK(hdac); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_BUSY; - - /* Get the DAC CR value */ - tmpreg1 = hdac->Instance->CR; - /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel); - /* Configure for the selected DAC channel: buffer output, trigger */ - /* Set TSELx and TENx bits according to DAC_Trigger value */ - /* Set BOFFx bit according to DAC_OutputBuffer value */ - tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer); - /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << Channel; - /* Write to DAC CR */ - hdac->Instance->CR = tmpreg1; - /* Disable wave generation */ - hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdac); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Set the specified data holding register value for DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Alignment: Specifies the data alignment. - * This parameter can be one of the following values: - * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected - * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected - * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - assert_param(IS_DAC_ALIGN(Alignment)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)hdac->Instance; - if(Channel == DAC_CHANNEL_1) - { - tmp += DAC_DHR12R1_ALIGNMENT(Alignment); - } - else - { - tmp += DAC_DHR12R2_ALIGNMENT(Alignment); - } - - /* Set the DAC channel1 selected data holding register */ - *(__IO uint32_t *) tmp = Data; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Errors functions ##### - ============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the DAC state. - (+) Check the DAC Errors. - -@endverbatim - * @{ - */ - -/** - * @brief return the DAC state - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval HAL state - */ -HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac) -{ - /* Return DAC state */ - return hdac->State; -} - - -/** - * @brief Return the DAC error code - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval DAC Error Code - */ -uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) -{ - return hdac->ErrorCode; -} - -/** - * @} - */ - -/** - * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - HAL_DAC_ConvCpltCallbackCh1(hdac); - - hdac->State= HAL_DAC_STATE_READY; -} - -/** - * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Conversion complete callback */ - HAL_DAC_ConvHalfCpltCallbackCh1(hdac); -} - -/** - * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Set DAC error code to DMA error */ - hdac->ErrorCode |= HAL_DAC_ERROR_DMA; - - HAL_DAC_ErrorCallbackCh1(hdac); - - hdac->State= HAL_DAC_STATE_READY; -} - -/** - * @} - */ - -#endif /* HAL_DAC_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.c deleted file mode 100644 index 9ebc9b3..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.c +++ /dev/null @@ -1,388 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dac_ex.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Extended DAC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of DAC extension peripheral: - * + Extended features functions - * - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) : - Use HAL_DACEx_DualGetValue() to get digital data to be converted and use - HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2. - (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal. - (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup DACEx DACEx - * @brief DAC driver modules - * @{ - */ - -#ifdef HAL_DAC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup DACEx_Exported_Functions DAC Exported Functions - * @{ - */ - -/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * -@verbatim - ============================================================================== - ##### Extended features functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Start conversion. - (+) Stop conversion. - (+) Start conversion and enable DMA transfer. - (+) Stop conversion and disable DMA transfer. - (+) Get result of conversion. - (+) Get result of dual mode conversion. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval The selected DAC channel data output value. - */ -uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) -{ - uint32_t tmp = 0; - - tmp |= hdac->Instance->DOR1; - - tmp |= hdac->Instance->DOR2 << 16; - - /* Returns the DAC channel data output register value */ - return tmp; -} - -/** - * @brief Enables or disables the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Amplitude: Select max triangle amplitude. - * This parameter can be one of the following values: - * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 - * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 - * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7 - * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15 - * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31 - * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63 - * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127 - * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255 - * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511 - * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023 - * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047 - * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); - - /* Process locked */ - __HAL_LOCK(hdac); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_BUSY; - - /* Enable the selected wave generation for the selected DAC channel */ - MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdac); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Enables or disables the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. - * This parameter can be one of the following values: - * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation - * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); - - /* Process locked */ - __HAL_LOCK(hdac); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_BUSY; - - /* Enable the selected wave generation for the selected DAC channel */ - MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdac); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Set the specified data holding register value for dual DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Alignment: Specifies the data alignment for dual channel DAC. - * This parameter can be one of the following values: - * DAC_ALIGN_8B_R: 8bit right data alignment selected - * DAC_ALIGN_12B_L: 12bit left data alignment selected - * DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register. - * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register. - * @note In dual mode, a unique register access is required to write in both - * DAC channels at the same time. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) -{ - uint32_t data = 0, tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(Alignment)); - assert_param(IS_DAC_DATA(Data1)); - assert_param(IS_DAC_DATA(Data2)); - - /* Calculate and set dual DAC data holding register value */ - if (Alignment == DAC_ALIGN_8B_R) - { - data = ((uint32_t)Data2 << 8) | Data1; - } - else - { - data = ((uint32_t)Data2 << 16) | Data1; - } - - tmp = (uint32_t)hdac->Instance; - tmp += DAC_DHR12RD_ALIGNMENT(Alignment); - - /* Set the dual DAC selected data holding register */ - *(__IO uint32_t *)tmp = data; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** - * @brief Conversion complete callback in non blocking mode for Channel2 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdac); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_ConvCpltCallbackCh2 could be implemented in the user file - */ -} - -/** - * @brief Conversion half DMA transfer callback in non blocking mode for Channel2 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdac); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file - */ -} - -/** - * @brief Error DAC callback for Channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdac); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file - */ -} - -/** - * @brief DMA underrun DAC callback for channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdac); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file - */ -} - -/** - * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - HAL_DACEx_ConvCpltCallbackCh2(hdac); - - hdac->State= HAL_DAC_STATE_READY; -} - -/** - * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Conversion complete callback */ - HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); -} - -/** - * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Set DAC error code to DMA error */ - hdac->ErrorCode |= HAL_DAC_ERROR_DMA; - - HAL_DACEx_ErrorCallbackCh2(hdac); - - hdac->State= HAL_DAC_STATE_READY; -} - -/** - * @} - */ - -#endif /* HAL_DAC_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi.c deleted file mode 100644 index 17305df..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi.c +++ /dev/null @@ -1,904 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dcmi.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief DCMI HAL module driver - * This file provides firmware functions to manage the following - * functionalities of the Digital Camera Interface (DCMI) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Error functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The sequence below describes how to use this driver to capture image - from a camera module connected to the DCMI Interface. - This sequence does not take into account the configuration of the - camera module, which should be made before to configure and enable - the DCMI to capture images. - - (#) Program the required configuration through following parameters: - horizontal and vertical polarity, pixel clock polarity, Capture Rate, - Synchronization Mode, code of the frame delimiter and data width - using HAL_DCMI_Init() function. - - (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR - register to the destination memory buffer. - - (#) Program the required configuration through following parameters: - DCMI mode, destination memory Buffer address and the data length - and enable capture using HAL_DCMI_Start_DMA() function. - - (#) Optionally, configure and Enable the CROP feature to select a rectangular - window from the received image using HAL_DCMI_ConfigCrop() - and HAL_DCMI_EnableCROP() functions - - (#) The capture can be stopped using HAL_DCMI_Stop() function. - - (#) To control DCMI state you can use the function HAL_DCMI_GetState(). - - *** DCMI HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in DCMI HAL driver. - - (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral. - (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral. - (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags. - (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags. - (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts. - (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts. - (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not. - - [..] - (@) You can refer to the DCMI HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -/** @defgroup DCMI DCMI - * @brief DCMI HAL module driver - * @{ - */ - -#ifdef HAL_DCMI_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* Set timeout to 1s */ - -#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE) /*!< Required left shift to set crop window vertical line count */ -#define DCMI_POSITION_CWSTRT_VST (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST) /*!< Required left shift to set crop window vertical start line count */ - -#define DCMI_POSITION_ESCR_LSC (uint32_t)POSITION_VAL(DCMI_ESCR_LSC) /*!< Required left shift to set line start delimiter */ -#define DCMI_POSITION_ESCR_LEC (uint32_t)POSITION_VAL(DCMI_ESCR_LEC) /*!< Required left shift to set line end delimiter */ -#define DCMI_POSITION_ESCR_FEC (uint32_t)POSITION_VAL(DCMI_ESCR_FEC) /*!< Required left shift to set frame end delimiter */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma); -static void DCMI_DMAError(DMA_HandleTypeDef *hdma); - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup DCMI_Exported_Functions DCMI Exported Functions - * @{ - */ - -/** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the DCMI - (+) De-initialize the DCMI - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the DCMI according to the specified - * parameters in the DCMI_InitTypeDef and create the associated handle. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) -{ - /* Check the DCMI peripheral state */ - if(hdcmi == NULL) - { - return HAL_ERROR; - } - - /* Check function parameters */ - assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance)); - assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity)); - assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity)); - assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity)); - assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode)); - assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate)); - assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode)); - assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode)); - - assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode)); - assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart)); - assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode)); - assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart)); - - if(hdcmi->State == HAL_DCMI_STATE_RESET) - { - /* Init the low level hardware */ - HAL_DCMI_MspInit(hdcmi); - } - - /* Change the DCMI state */ - hdcmi->State = HAL_DCMI_STATE_BUSY; - /* Configures the HS, VS, DE and PC polarity */ - hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |\ - DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |\ - DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\ - DCMI_CR_LSM | DCMI_CR_OELS); - - hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\ - hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity |\ - hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\ - hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode |\ - hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\ - hdcmi->Init.LineSelectStart); - - if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED) - { - hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) |\ - ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_POSITION_ESCR_LSC)|\ - ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_POSITION_ESCR_LEC) |\ - ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_POSITION_ESCR_FEC)); - - } - - /* Enable the Line, Vsync, Error and Overrun interrupts */ - __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR); - - /* Update error code */ - hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE; - - /* Initialize the DCMI state*/ - hdcmi->State = HAL_DCMI_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Deinitializes the DCMI peripheral registers to their default reset - * values. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi) -{ - /* DeInit the low level hardware */ - HAL_DCMI_MspDeInit(hdcmi); - - /* Update error code */ - hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE; - - /* Initialize the DCMI state*/ - hdcmi->State = HAL_DCMI_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hdcmi); - - return HAL_OK; -} - -/** - * @brief Initializes the DCMI MSP. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval None - */ -__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdcmi); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DCMI_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the DCMI MSP. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval None - */ -__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdcmi); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DCMI_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ -/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure destination address and data length and - Enables DCMI DMA request and enables DCMI capture - (+) Stop the DCMI capture. - (+) Handles DCMI interrupt request. - -@endverbatim - * @{ - */ - -/** - * @brief Enables DCMI DMA request and enables DCMI capture - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @param DCMI_Mode: DCMI capture mode snapshot or continuous grab. - * @param pData: The destination memory Buffer address (LCD Frame buffer). - * @param Length: The length of capture to be transferred. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length) -{ - /* Initialize the second memory address */ - uint32_t SecondMemAddress = 0; - - /* Check function parameters */ - assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode)); - - /* Process Locked */ - __HAL_LOCK(hdcmi); - - /* Lock the DCMI peripheral state */ - hdcmi->State = HAL_DCMI_STATE_BUSY; - - /* Enable DCMI by setting DCMIEN bit */ - __HAL_DCMI_ENABLE(hdcmi); - - /* Configure the DCMI Mode */ - hdcmi->Instance->CR &= ~(DCMI_CR_CM); - hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode); - - /* Set the DMA memory0 conversion complete callback */ - hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt; - - /* Set the DMA error callback */ - hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError; - - /* Set the dma abort callback */ - hdcmi->DMA_Handle->XferAbortCallback = NULL; - - /* Reset transfer counters value */ - hdcmi->XferCount = 0; - hdcmi->XferTransferNumber = 0; - - if(Length <= 0xFFFF) - { - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length); - } - else /* DCMI_DOUBLE_BUFFER Mode */ - { - /* Set the DMA memory1 conversion complete callback */ - hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAXferCplt; - - /* Initialize transfer parameters */ - hdcmi->XferCount = 1; - hdcmi->XferSize = Length; - hdcmi->pBuffPtr = pData; - - /* Get the number of buffer */ - while(hdcmi->XferSize > 0xFFFF) - { - hdcmi->XferSize = (hdcmi->XferSize/2); - hdcmi->XferCount = hdcmi->XferCount*2; - } - - /* Update DCMI counter and transfer number*/ - hdcmi->XferCount = (hdcmi->XferCount - 2); - hdcmi->XferTransferNumber = hdcmi->XferCount; - - /* Update second memory address */ - SecondMemAddress = (uint32_t)(pData + (4*hdcmi->XferSize)); - - /* Start DMA multi buffer transfer */ - HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize); - } - - /* Enable Capture */ - hdcmi->Instance->CR |= DCMI_CR_CAPTURE; - - /* Release Lock */ - __HAL_UNLOCK(hdcmi); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Disable DCMI DMA request and Disable DCMI capture - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) -{ - register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000); - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdcmi); - - /* Lock the DCMI peripheral state */ - hdcmi->State = HAL_DCMI_STATE_BUSY; - - /* Disable Capture */ - hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE); - - /* Check if the DCMI capture effectively disabled */ - do - { - if (count-- == 0) - { - /* Update error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT; - - status = HAL_TIMEOUT; - break; - } - } - while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0); - - /* Disable the DCMI */ - __HAL_DCMI_DISABLE(hdcmi); - - /* Disable the DMA */ - HAL_DMA_Abort(hdcmi->DMA_Handle); - - /* Update error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE; - - /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - - /* Return function status */ - return status; -} - -/** - * @brief Suspend DCMI capture - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi) -{ - register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000); - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdcmi); - - if(hdcmi->State == HAL_DCMI_STATE_BUSY) - { - /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_SUSPENDED; - - /* Disable Capture */ - hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE); - - /* Check if the DCMI capture effectively disabled */ - do - { - if (count-- == 0) - { - /* Update error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT; - - /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_READY; - - status = HAL_TIMEOUT; - break; - } - } - while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0); - } - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - - /* Return function status */ - return status; -} - -/** - * @brief Resume DCMI capture - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi) -{ - /* Process locked */ - __HAL_LOCK(hdcmi); - - if(hdcmi->State == HAL_DCMI_STATE_SUSPENDED) - { - /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_BUSY; - - /* Disable Capture */ - hdcmi->Instance->CR |= DCMI_CR_CAPTURE; - } - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Handles DCMI interrupt request. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for the DCMI. - * @retval None - */ -void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) -{ - uint32_t isr_value = READ_REG(hdcmi->Instance->MISR); - - /* Synchronization error interrupt management *******************************/ - if((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI) - { - /* Clear the Synchronization error flag */ - __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI); - - /* Update error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC; - - /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_ERROR; - - /* Set the synchronization error callback */ - hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError; - - /* Abort the DMA Transfer */ - HAL_DMA_Abort_IT(hdcmi->DMA_Handle); - } - /* Overflow interrupt management ********************************************/ - if((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI) - { - /* Clear the Overflow flag */ - __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI); - - /* Update error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR; - - /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_ERROR; - - /* Set the overflow callback */ - hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError; - - /* Abort the DMA Transfer */ - HAL_DMA_Abort_IT(hdcmi->DMA_Handle); - } - /* Line Interrupt management ************************************************/ - if((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI) - { - /* Clear the Line interrupt flag */ - __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI); - - /* Line interrupt Callback */ - HAL_DCMI_LineEventCallback(hdcmi); - } - /* VSYNC interrupt management ***********************************************/ - if((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI) - { - /* Clear the VSYNC flag */ - __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI); - - /* VSYNC Callback */ - HAL_DCMI_VsyncEventCallback(hdcmi); - } - /* FRAME interrupt management ***********************************************/ - if((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI) - { - /* When snapshot mode, disable Vsync, Error and Overrun interrupts */ - if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT) - { - /* Disable the Line, Vsync, Error and Overrun interrupts */ - __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR); - } - - /* Disable the Frame interrupt */ - __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME); - - /* Clear the End of Frame flag */ - __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI); - - /* Frame Callback */ - HAL_DCMI_FrameEventCallback(hdcmi); - } -} - -/** - * @brief Error DCMI callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval None - */ -__weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdcmi); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DCMI_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief Line Event callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval None - */ -__weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DCMI_LineEventCallback could be implemented in the user file - */ -} - -/** - * @brief VSYNC Event callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval None - */ -__weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdcmi); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DCMI_VsyncEventCallback could be implemented in the user file - */ -} - -/** - * @brief Frame Event callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval None - */ -__weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdcmi); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DCMI_FrameEventCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== -[..] This section provides functions allowing to: - (+) Configure the CROP feature. - (+) Enable/Disable the CROP feature. - (+) Set embedded synchronization delimiters unmasks. - -@endverbatim - * @{ - */ - -/** - * @brief Configure the DCMI CROP coordinate. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @param YSize: DCMI Line number - * @param XSize: DCMI Pixel per line - * @param X0: DCMI window X offset - * @param Y0: DCMI window Y offset - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize) -{ - /* Process Locked */ - __HAL_LOCK(hdcmi); - - /* Lock the DCMI peripheral state */ - hdcmi->State = HAL_DCMI_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_DCMI_WINDOW_COORDINATE(X0)); - assert_param(IS_DCMI_WINDOW_HEIGHT(Y0)); - assert_param(IS_DCMI_WINDOW_COORDINATE(XSize)); - assert_param(IS_DCMI_WINDOW_COORDINATE(YSize)); - - /* Configure CROP */ - hdcmi->Instance->CWSIZER = (XSize | (YSize << DCMI_POSITION_CWSIZE_VLINE)); - hdcmi->Instance->CWSTRTR = (X0 | (Y0 << DCMI_POSITION_CWSTRT_VST)); - - /* Initialize the DCMI state*/ - hdcmi->State = HAL_DCMI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - - return HAL_OK; -} - -/** - * @brief Disable the Crop feature. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi) -{ - /* Process Locked */ - __HAL_LOCK(hdcmi); - - /* Lock the DCMI peripheral state */ - hdcmi->State = HAL_DCMI_STATE_BUSY; - - /* Disable DCMI Crop feature */ - hdcmi->Instance->CR &= ~(uint32_t)DCMI_CR_CROP; - - /* Change the DCMI state*/ - hdcmi->State = HAL_DCMI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - - return HAL_OK; -} - -/** - * @brief Enable the Crop feature. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi) -{ - /* Process Locked */ - __HAL_LOCK(hdcmi); - - /* Lock the DCMI peripheral state */ - hdcmi->State = HAL_DCMI_STATE_BUSY; - - /* Enable DCMI Crop feature */ - hdcmi->Instance->CR |= (uint32_t)DCMI_CR_CROP; - - /* Change the DCMI state*/ - hdcmi->State = HAL_DCMI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the DCMI state. - (+) Get the specific DCMI error flag. - -@endverbatim - * @{ - */ - -/** - * @brief Return the DCMI state - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL state - */ -HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi) -{ - return hdcmi->State; -} - -/** -* @brief Return the DCMI error code -* @param hdcmi : pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. -* @retval DCMI Error Code -*/ -uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi) -{ - return hdcmi->ErrorCode; -} - -/** - * @} - */ -/* Private functions ---------------------------------------------------------*/ -/** @defgroup DCMI_Private_Functions DCMI Private Functions - * @{ - */ - /** - * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma) -{ - uint32_t tmp = 0; - - DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - if(hdcmi->XferCount != 0) - { - /* Update memory 0 address location */ - tmp = ((hdcmi->DMA_Handle->Instance->CR) & DMA_SxCR_CT); - if(((hdcmi->XferCount % 2) == 0) && (tmp != 0)) - { - tmp = hdcmi->DMA_Handle->Instance->M0AR; - HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY0); - hdcmi->XferCount--; - } - /* Update memory 1 address location */ - else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0) - { - tmp = hdcmi->DMA_Handle->Instance->M1AR; - HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY1); - hdcmi->XferCount--; - } - } - /* Update memory 0 address location */ - else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) != 0) - { - hdcmi->DMA_Handle->Instance->M0AR = hdcmi->pBuffPtr; - } - /* Update memory 1 address location */ - else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0) - { - tmp = hdcmi->pBuffPtr; - hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4*hdcmi->XferSize)); - hdcmi->XferCount = hdcmi->XferTransferNumber; - } - - /* Check if the frame is transferred */ - if(hdcmi->XferCount == hdcmi->XferTransferNumber) - { - /* Enable the Frame interrupt */ - __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME); - - /* When snapshot mode, set dcmi state to ready */ - if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT) - { - hdcmi->State= HAL_DCMI_STATE_READY; - } - } -} - -/** - * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void DCMI_DMAError(DMA_HandleTypeDef *hdma) -{ - DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - if(hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE) - { - /* Initialize the DCMI state*/ - hdcmi->State = HAL_DCMI_STATE_READY; - - /* Set DCMI Error Code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA; - } - - /* DCMI error Callback */ - HAL_DCMI_ErrorCallback(hdcmi); -} - -/** - * @} - */ - -/** - * @} - */ -#endif /* HAL_DCMI_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi_ex.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi_ex.c deleted file mode 100644 index 52c2cd6..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi_ex.c +++ /dev/null @@ -1,52 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dcmi_ex.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Empty file; This file is no longer used to handle the Black&White - * feature. Its content is now moved to common files - * (stm32f7xx_hal_dcmi.c/.h) as there's no device's dependency within F7 - * family. It's just kept for compatibility reasons. - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dfsdm.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dfsdm.c deleted file mode 100644 index 819dc7b..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dfsdm.c +++ /dev/null @@ -1,3018 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dfsdm.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the Digital Filter for Sigma-Delta Modulators - * (DFSDM) peripherals: - * + Initialization and configuration of channels and filters - * + Regular channels configuration - * + Injected channels configuration - * + Regular/Injected Channels DMA Configuration - * + Interrupts and flags management - * + Analog watchdog feature - * + Short-circuit detector feature - * + Extremes detector feature - * + Clock absence detector feature - * + Break generation on analog watchdog or short-circuit event - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - *** Channel initialization *** - ============================== - [..] - (#) User has first to initialize channels (before filters initialization). - (#) As prerequisite, fill in the HAL_DFSDM_ChannelMspInit() : - (++) Enable DFSDMz clock interface with __HAL_RCC_DFSDMz_CLK_ENABLE(). - (++) Enable the clocks for the DFSDMz GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). - (++) Configure these DFSDMz pins in alternate mode using HAL_GPIO_Init(). - (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global - interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). - (#) Configure the output clock, input, serial interface, analog watchdog, - offset and data right bit shift parameters for this channel using the - HAL_DFSDM_ChannelInit() function. - - *** Channel clock absence detector *** - ====================================== - [..] - (#) Start clock absence detector using HAL_DFSDM_ChannelCkabStart() or - HAL_DFSDM_ChannelCkabStart_IT(). - (#) In polling mode, use HAL_DFSDM_ChannelPollForCkab() to detect the clock - absence. - (#) In interrupt mode, HAL_DFSDM_ChannelCkabCallback() will be called if - clock absence is detected. - (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or - HAL_DFSDM_ChannelCkabStop_IT(). - (#) Please note that the same mode (polling or interrupt) has to be used - for all channels because the channels are sharing the same interrupt. - (#) Please note also that in interrupt mode, if clock absence detector is - stopped for one channel, interrupt will be disabled for all channels. - - *** Channel short circuit detector *** - ====================================== - [..] - (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or - or HAL_DFSDM_ChannelScdStart_IT(). - (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short - circuit. - (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if - short circuit is detected. - (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or - or HAL_DFSDM_ChannelScdStop_IT(). - (#) Please note that the same mode (polling or interrupt) has to be used - for all channels because the channels are sharing the same interrupt. - (#) Please note also that in interrupt mode, if short circuit detector is - stopped for one channel, interrupt will be disabled for all channels. - - *** Channel analog watchdog value *** - ===================================== - [..] - (#) Get analog watchdog filter value of a channel using - HAL_DFSDM_ChannelGetAwdValue(). - - *** Channel offset value *** - ===================================== - [..] - (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset(). - - *** Filter initialization *** - ============================= - [..] - (#) After channel initialization, user has to init filters. - (#) As prerequisite, fill in the HAL_DFSDM_FilterMspInit() : - (++) If interrupt mode is used , enable and configure DFSDMz_FLTx global - interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). - Please note that DFSDMz_FLT0 global interrupt could be already - enabled if interrupt is used for channel. - (++) If DMA mode is used, configure DMA with HAL_DMA_Init() and link it - with DFSDMz filter handle using __HAL_LINKDMA(). - (#) Configure the regular conversion, injected conversion and filter - parameters for this filter using the HAL_DFSDM_FilterInit() function. - - *** Filter regular channel conversion *** - ========================================= - [..] - (#) Select regular channel and enable/disable continuous mode using - HAL_DFSDM_FilterConfigRegChannel(). - (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(), - HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or - HAL_DFSDM_FilterRegularMsbStart_DMA(). - (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect - the end of regular conversion. - (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called - at the end of regular conversion. - (#) Get value of regular conversion and corresponding channel using - HAL_DFSDM_FilterGetRegularValue(). - (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and - HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the - half transfer and at the transfer complete. Please note that - HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA - circular mode. - (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(), - HAL_DFSDM_FilterRegularStop_IT() or HAL_DFSDM_FilterRegularStop_DMA(). - - *** Filter injected channels conversion *** - =========================================== - [..] - (#) Select injected channels using HAL_DFSDM_FilterConfigInjChannel(). - (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(), - HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or - HAL_DFSDM_FilterInjectedMsbStart_DMA(). - (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect - the end of injected conversion. - (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called - at the end of injected conversion. - (#) Get value of injected conversion and corresponding channel using - HAL_DFSDM_FilterGetInjectedValue(). - (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and - HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the - half transfer and at the transfer complete. Please note that - HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA - circular mode. - (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(), - HAL_DFSDM_FilterInjectedStop_IT() or HAL_DFSDM_FilterInjectedStop_DMA(). - - *** Filter analog watchdog *** - ============================== - [..] - (#) Start filter analog watchdog using HAL_DFSDM_FilterAwdStart_IT(). - (#) HAL_DFSDM_FilterAwdCallback() will be called if analog watchdog occurs. - (#) Stop filter analog watchdog using HAL_DFSDM_FilterAwdStop_IT(). - - *** Filter extreme detector *** - =============================== - [..] - (#) Start filter extreme detector using HAL_DFSDM_FilterExdStart(). - (#) Get extreme detector maximum value using HAL_DFSDM_FilterGetExdMaxValue(). - (#) Get extreme detector minimum value using HAL_DFSDM_FilterGetExdMinValue(). - (#) Start filter extreme detector using HAL_DFSDM_FilterExdStop(). - - *** Filter conversion time *** - ============================== - [..] - (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue(). - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -#ifdef HAL_DFSDM_MODULE_ENABLED -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -/** @defgroup DFSDM DFSDM - * @brief DFSDM HAL driver module - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup DFSDM_Private_Define DFSDM Private Define - * @{ - */ -#define DFSDM_CHCFGR1_CLK_DIV_OFFSET POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV) -#define DFSDM_CHAWSCDR_BKSCD_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_BKSCD) -#define DFSDM_CHAWSCDR_FOSR_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR) -#define DFSDM_CHCFGR2_OFFSET_OFFSET POSITION_VAL(DFSDM_CHCFGR2_OFFSET) -#define DFSDM_CHCFGR2_DTRBS_OFFSET POSITION_VAL(DFSDM_CHCFGR2_DTRBS) -#define DFSDM_FLTFCR_FOSR_OFFSET POSITION_VAL(DFSDM_FLTFCR_FOSR) -#define DFSDM_FLTCR1_MSB_RCH_OFFSET 8 -#define DFSDM_FLTCR2_EXCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_EXCH) -#define DFSDM_FLTCR2_AWDCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_AWDCH) -#define DFSDM_FLTISR_CKABF_OFFSET POSITION_VAL(DFSDM_FLTISR_CKABF) -#define DFSDM_FLTISR_SCDF_OFFSET POSITION_VAL(DFSDM_FLTISR_SCDF) -#define DFSDM_FLTICR_CLRCKABF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRCKABF) -#define DFSDM_FLTICR_CLRSCDF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRSCSDF) -#define DFSDM_FLTRDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTRDATAR_RDATA) -#define DFSDM_FLTJDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTJDATAR_JDATA) -#define DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT) -#define DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT) -#define DFSDM_FLTEXMAX_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMAX_EXMAX) -#define DFSDM_FLTEXMIN_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMIN_EXMIN) -#define DFSDM_FLTCNVTIMR_DATA_OFFSET POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT) -#define DFSDM_FLTAWSR_HIGH_OFFSET POSITION_VAL(DFSDM_FLTAWSR_AWHTF) -#define DFSDM_MSB_MASK 0xFFFF0000U -#define DFSDM_LSB_MASK 0x0000FFFFU -#define DFSDM_CKAB_TIMEOUT 5000U -#define DFSDM1_CHANNEL_NUMBER 8U -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup DFSDM_Private_Variables DFSDM Private Variables - * @{ - */ -__IO uint32_t v_dfsdm1ChannelCounter = 0; -DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL}; -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup DFSDM_Private_Functions DFSDM Private Functions - * @{ - */ -static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels); -static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance); -static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); -static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); -static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); -static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma); -static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma); -static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma); -static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma); -static void DFSDM_DMAError(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup DFSDM_Exported_Functions DFSDM Exported Functions - * @{ - */ - -/** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions - * @brief Channel initialization and de-initialization functions - * -@verbatim - ============================================================================== - ##### Channel initialization and de-initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the DFSDM channel. - (+) De-initialize the DFSDM channel. -@endverbatim - * @{ - */ - -/** - * @brief Initialize the DFSDM channel according to the specified parameters - * in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle. - * @param hdfsdm_channel : DFSDM channel handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - /* Check DFSDM Channel handle */ - if(hdfsdm_channel == NULL) - { - return HAL_ERROR; - } - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation)); - assert_param(IS_DFSDM_CHANNEL_INPUT(hdfsdm_channel->Init.Input.Multiplexer)); - assert_param(IS_DFSDM_CHANNEL_DATA_PACKING(hdfsdm_channel->Init.Input.DataPacking)); - assert_param(IS_DFSDM_CHANNEL_INPUT_PINS(hdfsdm_channel->Init.Input.Pins)); - assert_param(IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(hdfsdm_channel->Init.SerialInterface.Type)); - assert_param(IS_DFSDM_CHANNEL_SPI_CLOCK(hdfsdm_channel->Init.SerialInterface.SpiClock)); - assert_param(IS_DFSDM_CHANNEL_FILTER_ORDER(hdfsdm_channel->Init.Awd.FilterOrder)); - assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling)); - assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset)); - assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift)); - - /* Check that channel has not been already initialized */ - if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL) - { - return HAL_ERROR; - } - - /* Call MSP init function */ - HAL_DFSDM_ChannelMspInit(hdfsdm_channel); - - /* Update the channel counter */ - v_dfsdm1ChannelCounter++; - - /* Configure output serial clock and enable global DFSDM interface only for first channel */ - if(v_dfsdm1ChannelCounter == 1) - { - assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection)); - /* Set the output serial clock source */ - DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC); - DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection; - - /* Reset clock divider */ - DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV); - if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE) - { - assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider)); - /* Set the output clock divider */ - DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1) << - DFSDM_CHCFGR1_CLK_DIV_OFFSET); - } - - /* enable the DFSDM global interface */ - DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN; - } - - /* Set channel input parameters */ - hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX | - DFSDM_CHCFGR1_CHINSEL); - hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer | - hdfsdm_channel->Init.Input.DataPacking | - hdfsdm_channel->Init.Input.Pins); - - /* Set serial interface parameters */ - hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL); - hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type | - hdfsdm_channel->Init.SerialInterface.SpiClock); - - /* Set analog watchdog parameters */ - hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR); - hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | - ((hdfsdm_channel->Init.Awd.Oversampling - 1) << DFSDM_CHAWSCDR_FOSR_OFFSET)); - - /* Set channel offset and right bit shift */ - hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS); - hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_OFFSET) | - (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_OFFSET)); - - /* Enable DFSDM channel */ - hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN; - - /* Set DFSDM Channel to ready state */ - hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY; - - /* Store channel handle in DFSDM channel handle table */ - a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel; - - return HAL_OK; -} - -/** - * @brief De-initialize the DFSDM channel. - * @param hdfsdm_channel : DFSDM channel handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - /* Check DFSDM Channel handle */ - if(hdfsdm_channel == NULL) - { - return HAL_ERROR; - } - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - - /* Check that channel has not been already deinitialized */ - if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL) - { - return HAL_ERROR; - } - - /* Disable the DFSDM channel */ - hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN); - - /* Update the channel counter */ - v_dfsdm1ChannelCounter--; - - /* Disable global DFSDM at deinit of last channel */ - if(v_dfsdm1ChannelCounter == 0) - { - DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN); - } - - /* Call MSP deinit function */ - HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel); - - /* Set DFSDM Channel in reset state */ - hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET; - - /* Reset channel handle in DFSDM channel handle table */ - a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = (DFSDM_Channel_HandleTypeDef *) NULL; - - return HAL_OK; -} - -/** - * @brief Initialize the DFSDM channel MSP. - * @param hdfsdm_channel : DFSDM channel handle. - * @retval None - */ -__weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_channel); - - /* NOTE : This function should not be modified, when the function is needed, - the HAL_DFSDM_ChannelMspInit could be implemented in the user file. - */ -} - -/** - * @brief De-initialize the DFSDM channel MSP. - * @param hdfsdm_channel : DFSDM channel handle. - * @retval None - */ -__weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_channel); - - /* NOTE : This function should not be modified, when the function is needed, - the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions - * @brief Channel operation functions - * -@verbatim - ============================================================================== - ##### Channel operation functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Manage clock absence detector feature. - (+) Manage short circuit detector feature. - (+) Get analog watchdog value. - (+) Modify offset value. -@endverbatim - * @{ - */ - -/** - * @brief This function allows to start clock absence detection in polling mode. - * @note Same mode has to be used for all channels. - * @note If clock is not available on this channel during 5 seconds, - * clock absence detection will not be activated and function - * will return HAL_TIMEOUT error. - * @param hdfsdm_channel : DFSDM channel handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t channel; - uint32_t tickstart; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Get channel number from channel instance */ - channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Clear clock absence flag */ - while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0) - { - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); - - /* Check the Timeout */ - if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) - { - /* Set timeout status */ - status = HAL_TIMEOUT; - break; - } - } - - if(status == HAL_OK) - { - /* Start clock absence detection */ - hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN; - } - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to poll for the clock absence detection. - * @param hdfsdm_channel : DFSDM channel handle. - * @param Timeout : Timeout value in milliseconds. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, - uint32_t Timeout) -{ - uint32_t tickstart; - uint32_t channel; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - return HAL_ERROR; - } - else - { - /* Get channel number from channel instance */ - channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait clock absence detection */ - while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) == 0) - { - /* Check the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - /* Return timeout status */ - return HAL_TIMEOUT; - } - } - } - - /* Clear clock absence detection flag */ - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); - - /* Return function status */ - return HAL_OK; - } -} - -/** - * @brief This function allows to stop clock absence detection in polling mode. - * @param hdfsdm_channel : DFSDM channel handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t channel; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Stop clock absence detection */ - hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN); - - /* Clear clock absence flag */ - channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start clock absence detection in interrupt mode. - * @note Same mode has to be used for all channels. - * @note If clock is not available on this channel during 5 seconds, - * clock absence detection will not be activated and function - * will return HAL_TIMEOUT error. - * @param hdfsdm_channel : DFSDM channel handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t channel; - uint32_t tickstart; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Get channel number from channel instance */ - channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Clear clock absence flag */ - while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0) - { - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); - - /* Check the Timeout */ - if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) - { - /* Set timeout status */ - status = HAL_TIMEOUT; - break; - } - } - - if(status == HAL_OK) - { - /* Activate clock absence detection interrupt */ - DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_CKABIE; - - /* Start clock absence detection */ - hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN; - } - } - /* Return function status */ - return status; -} - -/** - * @brief Clock absence detection callback. - * @param hdfsdm_channel : DFSDM channel handle. - * @retval None - */ -__weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_channel); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file - */ -} - -/** - * @brief This function allows to stop clock absence detection in interrupt mode. - * @note Interrupt will be disabled for all channels - * @param hdfsdm_channel : DFSDM channel handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t channel; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Stop clock absence detection */ - hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN); - - /* Clear clock absence flag */ - channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); - - /* Disable clock absence detection interrupt */ - DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start short circuit detection in polling mode. - * @note Same mode has to be used for all channels - * @param hdfsdm_channel : DFSDM channel handle. - * @param Threshold : Short circuit detector threshold. - * This parameter must be a number between Min_Data = 0 and Max_Data = 255. - * @param BreakSignal : Break signals assigned to short circuit event. - * This parameter can be a values combination of @ref DFSDM_BreakSignals. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, - uint32_t Threshold, - uint32_t BreakSignal) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold)); - assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Configure threshold and break signals */ - hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT); - hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \ - Threshold); - - /* Start short circuit detection */ - hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN; - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to poll for the short circuit detection. - * @param hdfsdm_channel : DFSDM channel handle. - * @param Timeout : Timeout value in milliseconds. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, - uint32_t Timeout) -{ - uint32_t tickstart; - uint32_t channel; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - return HAL_ERROR; - } - else - { - /* Get channel number from channel instance */ - channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait short circuit detection */ - while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_OFFSET + channel)) == 0) - { - /* Check the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - /* Return timeout status */ - return HAL_TIMEOUT; - } - } - } - - /* Clear short circuit detection flag */ - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); - - /* Return function status */ - return HAL_OK; - } -} - -/** - * @brief This function allows to stop short circuit detection in polling mode. - * @param hdfsdm_channel : DFSDM channel handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t channel; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Stop short circuit detection */ - hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN); - - /* Clear short circuit detection flag */ - channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start short circuit detection in interrupt mode. - * @note Same mode has to be used for all channels - * @param hdfsdm_channel : DFSDM channel handle. - * @param Threshold : Short circuit detector threshold. - * This parameter must be a number between Min_Data = 0 and Max_Data = 255. - * @param BreakSignal : Break signals assigned to short circuit event. - * This parameter can be a values combination of @ref DFSDM_BreakSignals. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, - uint32_t Threshold, - uint32_t BreakSignal) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold)); - assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Activate short circuit detection interrupt */ - DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_SCDIE; - - /* Configure threshold and break signals */ - hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT); - hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \ - Threshold); - - /* Start short circuit detection */ - hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN; - } - /* Return function status */ - return status; -} - -/** - * @brief Short circuit detection callback. - * @param hdfsdm_channel : DFSDM channel handle. - * @retval None - */ -__weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_channel); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DFSDM_ChannelScdCallback could be implemented in the user file - */ -} - -/** - * @brief This function allows to stop short circuit detection in interrupt mode. - * @note Interrupt will be disabled for all channels - * @param hdfsdm_channel : DFSDM channel handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t channel; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Stop short circuit detection */ - hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN); - - /* Clear short circuit detection flag */ - channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); - - /* Disable short circuit detection interrupt */ - DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to get channel analog watchdog value. - * @param hdfsdm_channel : DFSDM channel handle. - * @retval Channel analog watchdog value. - */ -int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - return (int16_t) hdfsdm_channel->Instance->CHWDATAR; -} - -/** - * @brief This function allows to modify channel offset value. - * @param hdfsdm_channel : DFSDM channel handle. - * @param Offset : DFSDM channel offset. - * This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, - int32_t Offset) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Modify channel offset */ - hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET); - hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_OFFSET); - } - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function - * @brief Channel state function - * -@verbatim - ============================================================================== - ##### Channel state function ##### - ============================================================================== - [..] This section provides function allowing to: - (+) Get channel handle state. -@endverbatim - * @{ - */ - -/** - * @brief This function allows to get the current DFSDM channel handle state. - * @param hdfsdm_channel : DFSDM channel handle. - * @retval DFSDM channel state. - */ -HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - /* Return DFSDM channel handle state */ - return hdfsdm_channel->State; -} - -/** - * @} - */ - -/** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions - * @brief Filter initialization and de-initialization functions - * -@verbatim - ============================================================================== - ##### Filter initialization and de-initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the DFSDM filter. - (+) De-initialize the DFSDM filter. -@endverbatim - * @{ - */ - -/** - * @brief Initialize the DFSDM filter according to the specified parameters - * in the DFSDM_FilterInitTypeDef structure and initialize the associated handle. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Check DFSDM Channel handle */ - if(hdfsdm_filter == NULL) - { - return HAL_ERROR; - } - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(IS_DFSDM_FILTER_REG_TRIGGER(hdfsdm_filter->Init.RegularParam.Trigger)); - assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.FastMode)); - assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.DmaMode)); - assert_param(IS_DFSDM_FILTER_INJ_TRIGGER(hdfsdm_filter->Init.InjectedParam.Trigger)); - assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.ScanMode)); - assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.DmaMode)); - assert_param(IS_DFSDM_FILTER_SINC_ORDER(hdfsdm_filter->Init.FilterParam.SincOrder)); - assert_param(IS_DFSDM_FILTER_OVS_RATIO(hdfsdm_filter->Init.FilterParam.Oversampling)); - assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling)); - - /* Check parameters compatibility */ - if((hdfsdm_filter->Instance == DFSDM1_Filter0) && - ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) || - (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER))) - { - return HAL_ERROR; - } - - /* Initialize DFSDM filter variables with default values */ - hdfsdm_filter->RegularContMode = DFSDM_CONTINUOUS_CONV_OFF; - hdfsdm_filter->InjectedChannelsNbr = 1; - hdfsdm_filter->InjConvRemaining = 1; - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_NONE; - - /* Call MSP init function */ - HAL_DFSDM_FilterMspInit(hdfsdm_filter); - - /* Set regular parameters */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC); - if(hdfsdm_filter->Init.RegularParam.FastMode == ENABLE) - { - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST; - } - else - { - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST); - } - - if(hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE) - { - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN; - } - else - { - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RDMAEN); - } - - /* Set injected parameters */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL); - if(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER) - { - assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger)); - assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge)); - hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger); - } - - if(hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE) - { - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN; - } - else - { - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN); - } - - if(hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE) - { - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN; - } - else - { - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN); - } - - /* Set filter parameters */ - hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR); - hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder | - ((hdfsdm_filter->Init.FilterParam.Oversampling - 1) << DFSDM_FLTFCR_FOSR_OFFSET) | - (hdfsdm_filter->Init.FilterParam.IntOversampling - 1)); - - /* Store regular and injected triggers and injected scan mode*/ - hdfsdm_filter->RegularTrigger = hdfsdm_filter->Init.RegularParam.Trigger; - hdfsdm_filter->InjectedTrigger = hdfsdm_filter->Init.InjectedParam.Trigger; - hdfsdm_filter->ExtTriggerEdge = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge; - hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode; - - /* Enable DFSDM filter */ - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; - - /* Set DFSDM filter to ready state */ - hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY; - - return HAL_OK; -} - -/** - * @brief De-initializes the DFSDM filter. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Check DFSDM filter handle */ - if(hdfsdm_filter == NULL) - { - return HAL_ERROR; - } - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Disable the DFSDM filter */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); - - /* Call MSP deinit function */ - HAL_DFSDM_FilterMspDeInit(hdfsdm_filter); - - /* Set DFSDM filter in reset state */ - hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET; - - return HAL_OK; -} - -/** - * @brief Initializes the DFSDM filter MSP. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval None - */ -__weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_filter); - - /* NOTE : This function should not be modified, when the function is needed, - the HAL_DFSDM_FilterMspInit could be implemented in the user file. - */ -} - -/** - * @brief De-initializes the DFSDM filter MSP. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval None - */ -__weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_filter); - - /* NOTE : This function should not be modified, when the function is needed, - the HAL_DFSDM_FilterMspDeInit could be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup DFSDM_Exported_Functions_Group2_Filter Filter control functions - * @brief Filter control functions - * -@verbatim - ============================================================================== - ##### Filter control functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Select channel and enable/disable continuous mode for regular conversion. - (+) Select channels for injected conversion. -@endverbatim - * @{ - */ - -/** - * @brief This function allows to select channel and to enable/disable - * continuous mode for regular conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Channel for regular conversion. - * This parameter can be a value of @ref DFSDM_Channel_Selection. - * @param ContinuousMode : Enable/disable continuous mode for regular conversion. - * This parameter can be a value of @ref DFSDM_ContinuousMode. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t Channel, - uint32_t ContinuousMode) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel)); - assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR)) - { - /* Configure channel and continuous mode for regular conversion */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT); - if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON) - { - hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) | - DFSDM_FLTCR1_RCONT); - } - else - { - hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) ((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET); - } - /* Store continuous mode information */ - hdfsdm_filter->RegularContMode = ContinuousMode; - } - else - { - status = HAL_ERROR; - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to select channels for injected conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Channels for injected conversion. - * This parameter can be a values combination of @ref DFSDM_Channel_Selection. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR)) - { - /* Configure channel for injected conversion */ - hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK); - /* Store number of injected channels */ - hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel); - /* Update number of injected channels remaining */ - hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; - } - else - { - status = HAL_ERROR; - } - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions - * @brief Filter operation functions - * -@verbatim - ============================================================================== - ##### Filter operation functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Start conversion of regular/injected channel. - (+) Poll for the end of regular/injected conversion. - (+) Stop conversion of regular/injected channel. - (+) Start conversion of regular/injected channel and enable interrupt. - (+) Call the callback functions at the end of regular/injected conversions. - (+) Stop conversion of regular/injected channel and disable interrupt. - (+) Start conversion of regular/injected channel and enable DMA transfer. - (+) Stop conversion of regular/injected channel and disable DMA transfer. - (+) Start analog watchdog and enable interrupt. - (+) Call the callback function when analog watchdog occurs. - (+) Stop analog watchdog and disable interrupt. - (+) Start extreme detector. - (+) Stop extreme detector. - (+) Get result of regular channel conversion. - (+) Get result of injected channel conversion. - (+) Get extreme detector maximum and minimum values. - (+) Get conversion time. - (+) Handle DFSDM interrupt request. -@endverbatim - * @{ - */ - -/** - * @brief This function allows to start regular conversion in polling mode. - * @note This function should be called only when DFSDM filter instance is - * in idle state or if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) - { - /* Start regular conversion */ - DFSDM_RegConvStart(hdfsdm_filter); - } - else - { - status = HAL_ERROR; - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to poll for the end of regular conversion. - * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Timeout : Timeout value in milliseconds. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t Timeout) -{ - uint32_t tickstart; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) - { - /* Return error status */ - return HAL_ERROR; - } - else - { - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait end of regular conversion */ - while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF) - { - /* Check the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - /* Return timeout status */ - return HAL_TIMEOUT; - } - } - } - /* Check if overrun occurs */ - if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF) - { - /* Update error code and call error callback */ - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN; - HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); - - /* Clear regular overrun flag */ - hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF; - } - /* Update DFSDM filter state only if not continuous conversion and SW trigger */ - if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) - { - hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \ - HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ; - } - /* Return function status */ - return HAL_OK; - } -} - -/** - * @brief This function allows to stop regular conversion in polling mode. - * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Stop regular conversion */ - DFSDM_RegConvStop(hdfsdm_filter); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start regular conversion in interrupt mode. - * @note This function should be called only when DFSDM filter instance is - * in idle state or if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) - { - /* Enable interrupts for regular conversions */ - hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE); - - /* Start regular conversion */ - DFSDM_RegConvStart(hdfsdm_filter); - } - else - { - status = HAL_ERROR; - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to stop regular conversion in interrupt mode. - * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Disable interrupts for regular conversions */ - hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE); - - /* Stop regular conversion */ - DFSDM_RegConvStop(hdfsdm_filter); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start regular conversion in DMA mode. - * @note This function should be called only when DFSDM filter instance is - * in idle state or if injected conversion is ongoing. - * Please note that data on buffer will contain signed regular conversion - * value on 24 most significant bits and corresponding channel on 3 least - * significant bits. - * @param hdfsdm_filter : DFSDM filter handle. - * @param pData : The destination buffer address. - * @param Length : The length of data to be transferred from DFSDM filter to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - int32_t *pData, - uint32_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check destination address and length */ - if((pData == NULL) || (Length == 0)) - { - status = HAL_ERROR; - } - /* Check that DMA is enabled for regular conversion */ - else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN) - { - status = HAL_ERROR; - } - /* Check parameters compatibility */ - else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \ - (Length != 1)) - { - status = HAL_ERROR; - } - else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR)) - { - status = HAL_ERROR; - } - /* Check DFSDM filter state */ - else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) - { - /* Set callbacks on DMA handler */ - hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt; - hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError; - hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\ - DFSDM_DMARegularHalfConvCplt : NULL; - - /* Start DMA in interrupt mode */ - if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \ - (uint32_t) pData, Length) != HAL_OK) - { - /* Set DFSDM filter in error state */ - hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; - status = HAL_ERROR; - } - else - { - /* Start regular conversion */ - DFSDM_RegConvStart(hdfsdm_filter); - } - } - else - { - status = HAL_ERROR; - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start regular conversion in DMA mode and to get - * only the 16 most significant bits of conversion. - * @note This function should be called only when DFSDM filter instance is - * in idle state or if injected conversion is ongoing. - * Please note that data on buffer will contain signed 16 most significant - * bits of regular conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @param pData : The destination buffer address. - * @param Length : The length of data to be transferred from DFSDM filter to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - int16_t *pData, - uint32_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check destination address and length */ - if((pData == NULL) || (Length == 0)) - { - status = HAL_ERROR; - } - /* Check that DMA is enabled for regular conversion */ - else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN) - { - status = HAL_ERROR; - } - /* Check parameters compatibility */ - else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \ - (Length != 1)) - { - status = HAL_ERROR; - } - else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR)) - { - status = HAL_ERROR; - } - /* Check DFSDM filter state */ - else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) - { - /* Set callbacks on DMA handler */ - hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt; - hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError; - hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\ - DFSDM_DMARegularHalfConvCplt : NULL; - - /* Start DMA in interrupt mode */ - if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2, \ - (uint32_t) pData, Length) != HAL_OK) - { - /* Set DFSDM filter in error state */ - hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; - status = HAL_ERROR; - } - else - { - /* Start regular conversion */ - DFSDM_RegConvStart(hdfsdm_filter); - } - } - else - { - status = HAL_ERROR; - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to stop regular conversion in DMA mode. - * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Stop current DMA transfer */ - if(HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK) - { - /* Set DFSDM filter in error state */ - hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; - status = HAL_ERROR; - } - else - { - /* Stop regular conversion */ - DFSDM_RegConvStop(hdfsdm_filter); - } - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to get regular conversion value. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel of regular conversion. - * @retval Regular conversion value - */ -int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t *Channel) -{ - uint32_t reg = 0; - int32_t value = 0; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(Channel != NULL); - - /* Get value of data register for regular channel */ - reg = hdfsdm_filter->Instance->FLTRDATAR; - - /* Extract channel and regular conversion value */ - *Channel = (reg & DFSDM_FLTRDATAR_RDATACH); - value = ((reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_DATA_OFFSET); - - /* return regular conversion value */ - return value; -} - -/** - * @brief This function allows to start injected conversion in polling mode. - * @note This function should be called only when DFSDM filter instance is - * in idle state or if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) - { - /* Start injected conversion */ - DFSDM_InjConvStart(hdfsdm_filter); - } - else - { - status = HAL_ERROR; - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to poll for the end of injected conversion. - * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Timeout : Timeout value in milliseconds. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t Timeout) -{ - uint32_t tickstart; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) - { - /* Return error status */ - return HAL_ERROR; - } - else - { - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait end of injected conversions */ - while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF) - { - /* Check the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - /* Return timeout status */ - return HAL_TIMEOUT; - } - } - } - /* Check if overrun occurs */ - if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF) - { - /* Update error code and call error callback */ - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN; - HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); - - /* Clear injected overrun flag */ - hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF; - } - - /* Update remaining injected conversions */ - hdfsdm_filter->InjConvRemaining--; - if(hdfsdm_filter->InjConvRemaining == 0) - { - /* Update DFSDM filter state only if trigger is software */ - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) - { - hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \ - HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG; - } - - /* end of injected sequence, reset the value */ - hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; - } - - /* Return function status */ - return HAL_OK; - } -} - -/** - * @brief This function allows to stop injected conversion in polling mode. - * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Stop injected conversion */ - DFSDM_InjConvStop(hdfsdm_filter); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start injected conversion in interrupt mode. - * @note This function should be called only when DFSDM filter instance is - * in idle state or if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) - { - /* Enable interrupts for injected conversions */ - hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE); - - /* Start injected conversion */ - DFSDM_InjConvStart(hdfsdm_filter); - } - else - { - status = HAL_ERROR; - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to stop injected conversion in interrupt mode. - * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Disable interrupts for injected conversions */ - hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE); - - /* Stop injected conversion */ - DFSDM_InjConvStop(hdfsdm_filter); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start injected conversion in DMA mode. - * @note This function should be called only when DFSDM filter instance is - * in idle state or if regular conversion is ongoing. - * Please note that data on buffer will contain signed injected conversion - * value on 24 most significant bits and corresponding channel on 3 least - * significant bits. - * @param hdfsdm_filter : DFSDM filter handle. - * @param pData : The destination buffer address. - * @param Length : The length of data to be transferred from DFSDM filter to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - int32_t *pData, - uint32_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check destination address and length */ - if((pData == NULL) || (Length == 0)) - { - status = HAL_ERROR; - } - /* Check that DMA is enabled for injected conversion */ - else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN) - { - status = HAL_ERROR; - } - /* Check parameters compatibility */ - else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \ - (Length > hdfsdm_filter->InjConvRemaining)) - { - status = HAL_ERROR; - } - else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR)) - { - status = HAL_ERROR; - } - /* Check DFSDM filter state */ - else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) - { - /* Set callbacks on DMA handler */ - hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt; - hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError; - hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\ - DFSDM_DMAInjectedHalfConvCplt : NULL; - - /* Start DMA in interrupt mode */ - if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \ - (uint32_t) pData, Length) != HAL_OK) - { - /* Set DFSDM filter in error state */ - hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; - status = HAL_ERROR; - } - else - { - /* Start injected conversion */ - DFSDM_InjConvStart(hdfsdm_filter); - } - } - else - { - status = HAL_ERROR; - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start injected conversion in DMA mode and to get - * only the 16 most significant bits of conversion. - * @note This function should be called only when DFSDM filter instance is - * in idle state or if regular conversion is ongoing. - * Please note that data on buffer will contain signed 16 most significant - * bits of injected conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @param pData : The destination buffer address. - * @param Length : The length of data to be transferred from DFSDM filter to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - int16_t *pData, - uint32_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check destination address and length */ - if((pData == NULL) || (Length == 0)) - { - status = HAL_ERROR; - } - /* Check that DMA is enabled for injected conversion */ - else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN) - { - status = HAL_ERROR; - } - /* Check parameters compatibility */ - else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \ - (Length > hdfsdm_filter->InjConvRemaining)) - { - status = HAL_ERROR; - } - else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR)) - { - status = HAL_ERROR; - } - /* Check DFSDM filter state */ - else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) - { - /* Set callbacks on DMA handler */ - hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt; - hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError; - hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\ - DFSDM_DMAInjectedHalfConvCplt : NULL; - - /* Start DMA in interrupt mode */ - if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2, \ - (uint32_t) pData, Length) != HAL_OK) - { - /* Set DFSDM filter in error state */ - hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; - status = HAL_ERROR; - } - else - { - /* Start injected conversion */ - DFSDM_InjConvStart(hdfsdm_filter); - } - } - else - { - status = HAL_ERROR; - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to stop injected conversion in DMA mode. - * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Stop current DMA transfer */ - if(HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK) - { - /* Set DFSDM filter in error state */ - hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; - status = HAL_ERROR; - } - else - { - /* Stop regular conversion */ - DFSDM_InjConvStop(hdfsdm_filter); - } - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to get injected conversion value. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel of injected conversion. - * @retval Injected conversion value - */ -int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t *Channel) -{ - uint32_t reg = 0; - int32_t value = 0; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(Channel != NULL); - - /* Get value of data register for injected channel */ - reg = hdfsdm_filter->Instance->FLTJDATAR; - - /* Extract channel and injected conversion value */ - *Channel = (reg & DFSDM_FLTJDATAR_JDATACH); - value = ((reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_DATA_OFFSET); - - /* return regular conversion value */ - return value; -} - -/** - * @brief This function allows to start filter analog watchdog in interrupt mode. - * @param hdfsdm_filter : DFSDM filter handle. - * @param awdParam : DFSDM filter analog watchdog parameters. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - DFSDM_Filter_AwdParamTypeDef *awdParam) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(IS_DFSDM_FILTER_AWD_DATA_SOURCE(awdParam->DataSource)); - assert_param(IS_DFSDM_INJECTED_CHANNEL(awdParam->Channel)); - assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->HighThreshold)); - assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold)); - assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal)); - assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Set analog watchdog data source */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL); - hdfsdm_filter->Instance->FLTCR1 |= awdParam->DataSource; - - /* Set thresholds and break signals */ - hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH); - hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_THRESHOLD_OFFSET) | \ - awdParam->HighBreakSignal); - hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL); - hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_THRESHOLD_OFFSET) | \ - awdParam->LowBreakSignal); - - /* Set channels and interrupt for analog watchdog */ - hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH); - hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_OFFSET) | \ - DFSDM_FLTCR2_AWDIE); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to stop filter analog watchdog in interrupt mode. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Reset channels for analog watchdog and deactivate interrupt */ - hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH | DFSDM_FLTCR2_AWDIE); - - /* Clear all analog watchdog flags */ - hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF); - - /* Reset thresholds and break signals */ - hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH); - hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL); - - /* Reset analog watchdog data source */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start extreme detector feature. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Channels where extreme detector is enabled. - * This parameter can be a values combination of @ref DFSDM_Channel_Selection. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Set channels for extreme detector */ - hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH); - hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_OFFSET); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to stop extreme detector feature. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - __IO uint32_t reg1; - __IO uint32_t reg2; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Reset channels for extreme detector */ - hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH); - - /* Clear extreme detector values */ - reg1 = hdfsdm_filter->Instance->FLTEXMAX; - reg2 = hdfsdm_filter->Instance->FLTEXMIN; - UNUSED(reg1); /* To avoid GCC warning */ - UNUSED(reg2); /* To avoid GCC warning */ - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to get extreme detector maximum value. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel. - * @retval Extreme detector maximum value - * This value is between Min_Data = -8388608 and Max_Data = 8388607. - */ -int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t *Channel) -{ - uint32_t reg = 0; - int32_t value = 0; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(Channel != NULL); - - /* Get value of extreme detector maximum register */ - reg = hdfsdm_filter->Instance->FLTEXMAX; - - /* Extract channel and extreme detector maximum value */ - *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH); - value = ((reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_DATA_OFFSET); - - /* return extreme detector maximum value */ - return value; -} - -/** - * @brief This function allows to get extreme detector minimum value. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel. - * @retval Extreme detector minimum value - * This value is between Min_Data = -8388608 and Max_Data = 8388607. - */ -int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t *Channel) -{ - uint32_t reg = 0; - int32_t value = 0; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(Channel != NULL); - - /* Get value of extreme detector minimum register */ - reg = hdfsdm_filter->Instance->FLTEXMIN; - - /* Extract channel and extreme detector minimum value */ - *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH); - value = ((reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_DATA_OFFSET); - - /* return extreme detector minimum value */ - return value; -} - -/** - * @brief This function allows to get conversion time value. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval Conversion time value - * @note To get time in second, this value has to be divided by DFSDM clock frequency. - */ -uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - uint32_t reg = 0; - uint32_t value = 0; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Get value of conversion timer register */ - reg = hdfsdm_filter->Instance->FLTCNVTIMR; - - /* Extract conversion time value */ - value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_DATA_OFFSET); - - /* return extreme detector minimum value */ - return value; -} - -/** - * @brief This function handles the DFSDM interrupts. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval None - */ -void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Check if overrun occurs during regular conversion */ - if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_ROVRIE) != 0)) - { - /* Clear regular overrun flag */ - hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF; - - /* Update error code */ - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN; - - /* Call error callback */ - HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); - } - /* Check if overrun occurs during injected conversion */ - else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JOVRIE) != 0)) - { - /* Clear injected overrun flag */ - hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF; - - /* Update error code */ - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN; - - /* Call error callback */ - HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); - } - /* Check if end of regular conversion */ - else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0)) - { - /* Call regular conversion complete callback */ - HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter); - - /* End of conversion if mode is not continuous and software trigger */ - if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) - { - /* Disable interrupts for regular conversions */ - hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE); - - /* Update DFSDM filter state */ - hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \ - HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ; - } - } - /* Check if end of injected conversion */ - else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0)) - { - /* Call injected conversion complete callback */ - HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter); - - /* Update remaining injected conversions */ - hdfsdm_filter->InjConvRemaining--; - if(hdfsdm_filter->InjConvRemaining == 0) - { - /* End of conversion if trigger is software */ - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) - { - /* Disable interrupts for injected conversions */ - hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE); - - /* Update DFSDM filter state */ - hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \ - HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG; - } - /* end of injected sequence, reset the value */ - hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; - } - } - /* Check if analog watchdog occurs */ - else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_AWDF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_AWDIE) != 0)) - { - uint32_t reg = 0; - uint32_t threshold = 0; - uint32_t channel = 0; - - /* Get channel and threshold */ - reg = hdfsdm_filter->Instance->FLTAWSR; - threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD; - if(threshold == DFSDM_AWD_HIGH_THRESHOLD) - { - reg = reg >> DFSDM_FLTAWSR_HIGH_OFFSET; - } - while((reg & 1) == 0) - { - channel++; - reg = reg >> 1; - } - /* Clear analog watchdog flag */ - hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \ - (1 << (DFSDM_FLTAWSR_HIGH_OFFSET + channel)) : \ - (1 << channel); - - /* Call analog watchdog callback */ - HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold); - } - /* Check if clock absence occurs */ - else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \ - ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0)) - { - uint32_t reg = 0; - uint32_t channel = 0; - - reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_OFFSET); - - while(channel < DFSDM1_CHANNEL_NUMBER) - { - /* Check if flag is set and corresponding channel is enabled */ - if(((reg & 1) != 0) && (a_dfsdm1ChannelHandle[channel] != NULL)) - { - /* Check clock absence has been enabled for this channel */ - if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0) - { - /* Clear clock absence flag */ - hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); - - /* Call clock absence callback */ - HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]); - } - } - channel++; - reg = reg >> 1; - } - } - /* Check if short circuit detection occurs */ - else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \ - ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0)) - { - uint32_t reg = 0; - uint32_t channel = 0; - - /* Get channel */ - reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_OFFSET); - while((reg & 1) == 0) - { - channel++; - reg = reg >> 1; - } - - /* Clear short circuit detection flag */ - hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); - - /* Call short circuit detection callback */ - HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]); - } -} - -/** - * @brief Regular conversion complete callback. - * @note In interrupt mode, user has to read conversion value in this function - * using HAL_DFSDM_FilterGetRegularValue. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval None - */ -__weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_filter); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file. - */ -} - -/** - * @brief Half regular conversion complete callback. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval None - */ -__weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_filter); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file. - */ -} - -/** - * @brief Injected conversion complete callback. - * @note In interrupt mode, user has to read conversion value in this function - * using HAL_DFSDM_FilterGetInjectedValue. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval None - */ -__weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_filter); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file. - */ -} - -/** - * @brief Half injected conversion complete callback. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval None - */ -__weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_filter); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file. - */ -} - -/** - * @brief Filter analog watchdog callback. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel. - * @param Threshold : Low or high threshold has been reached. - * @retval None - */ -__weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t Channel, uint32_t Threshold) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_filter); - UNUSED(Channel); - UNUSED(Threshold); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DFSDM_FilterAwdCallback could be implemented in the user file. - */ -} - -/** - * @brief Error callback. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval None - */ -__weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_filter); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DFSDM_FilterErrorCallback could be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions - * @brief Filter state functions - * -@verbatim - ============================================================================== - ##### Filter state functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Get the DFSDM filter state. - (+) Get the DFSDM filter error. -@endverbatim - * @{ - */ - -/** - * @brief This function allows to get the current DFSDM filter handle state. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval DFSDM filter state. - */ -HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Return DFSDM filter handle state */ - return hdfsdm_filter->State; -} - -/** - * @brief This function allows to get the current DFSDM filter error. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval DFSDM filter error code. - */ -uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - return hdfsdm_filter->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ -/* End of exported functions -------------------------------------------------*/ - -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup DFSDM_Private_Functions DFSDM Private Functions - * @{ - */ - -/** - * @brief DMA half transfer complete callback for regular conversion. - * @param hdma : DMA handle. - * @retval None - */ -static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Get DFSDM filter handle */ - DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; - - /* Call regular half conversion complete callback */ - HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter); -} - -/** - * @brief DMA transfer complete callback for regular conversion. - * @param hdma : DMA handle. - * @retval None - */ -static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Get DFSDM filter handle */ - DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; - - /* Call regular conversion complete callback */ - HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter); -} - -/** - * @brief DMA half transfer complete callback for injected conversion. - * @param hdma : DMA handle. - * @retval None - */ -static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Get DFSDM filter handle */ - DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; - - /* Call injected half conversion complete callback */ - HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter); -} - -/** - * @brief DMA transfer complete callback for injected conversion. - * @param hdma : DMA handle. - * @retval None - */ -static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Get DFSDM filter handle */ - DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; - - /* Call injected conversion complete callback */ - HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter); -} - -/** - * @brief DMA error callback. - * @param hdma : DMA handle. - * @retval None - */ -static void DFSDM_DMAError(DMA_HandleTypeDef *hdma) -{ - /* Get DFSDM filter handle */ - DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; - - /* Update error code */ - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA; - - /* Call error callback */ - HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); -} - -/** - * @brief This function allows to get the number of injected channels. - * @param Channels : bitfield of injected channels. - * @retval Number of injected channels. - */ -static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels) -{ - uint32_t nbChannels = 0; - uint32_t tmp; - - /* Get the number of channels from bitfield */ - tmp = (uint32_t) (Channels & DFSDM_LSB_MASK); - while(tmp != 0) - { - if((tmp & 1) != 0) - { - nbChannels++; - } - tmp = (uint32_t) (tmp >> 1); - } - return nbChannels; -} - -/** - * @brief This function allows to get the channel number from channel instance. - * @param Instance : DFSDM channel instance. - * @retval Channel number. - */ -static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) -{ - uint32_t channel = 0xFF; - - /* Get channel from instance */ - if(Instance == DFSDM1_Channel0) - { - channel = 0; - } - else if(Instance == DFSDM1_Channel1) - { - channel = 1; - } - else if(Instance == DFSDM1_Channel2) - { - channel = 2; - } - else if(Instance == DFSDM1_Channel3) - { - channel = 3; - } - else if(Instance == DFSDM1_Channel4) - { - channel = 4; - } - else if(Instance == DFSDM1_Channel5) - { - channel = 5; - } - else if(Instance == DFSDM1_Channel6) - { - channel = 6; - } - else if(Instance == DFSDM1_Channel7) - { - channel = 7; - } - - return channel; -} - -/** - * @brief This function allows to really start regular conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval None - */ -static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) -{ - /* Check regular trigger */ - if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) - { - /* Software start of regular conversion */ - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART; - } - else /* synchronous trigger */ - { - /* Disable DFSDM filter */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); - - /* Set RSYNC bit in DFSDM_FLTCR1 register */ - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC; - - /* Enable DFSDM filter */ - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; - - /* If injected conversion was in progress, restart it */ - if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) - { - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) - { - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART; - } - /* Update remaining injected conversions */ - hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; - } - } - /* Update DFSDM filter state */ - hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \ - HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ; -} - -/** - * @brief This function allows to really stop regular conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval None - */ -static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) -{ - /* Disable DFSDM filter */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); - - /* If regular trigger was synchronous, reset RSYNC bit in DFSDM_FLTCR1 register */ - if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER) - { - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC); - } - - /* Enable DFSDM filter */ - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; - - /* If injected conversion was in progress, restart it */ - if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) - { - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) - { - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART; - } - /* Update remaining injected conversions */ - hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; - } - - /* Update DFSDM filter state */ - hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \ - HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ; -} - -/** - * @brief This function allows to really start injected conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval None - */ -static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) -{ - /* Check injected trigger */ - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) - { - /* Software start of injected conversion */ - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART; - } - else /* external or synchronous trigger */ - { - /* Disable DFSDM filter */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); - - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER) - { - /* Set JSYNC bit in DFSDM_FLTCR1 register */ - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC; - } - else /* external trigger */ - { - /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */ - hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge; - } - - /* Enable DFSDM filter */ - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; - - /* If regular conversion was in progress, restart it */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \ - (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) - { - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART; - } - } - /* Update DFSDM filter state */ - hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \ - HAL_DFSDM_FILTER_STATE_INJ : HAL_DFSDM_FILTER_STATE_REG_INJ; -} - -/** - * @brief This function allows to really stop injected conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @retval None - */ -static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) -{ - /* Disable DFSDM filter */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); - - /* If injected trigger was synchronous, reset JSYNC bit in DFSDM_FLTCR1 register */ - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER) - { - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC); - } - else if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER) - { - /* Reset JEXTEN[1:0] bits in DFSDM_FLTCR1 register */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN); - } - - /* Enable DFSDM filter */ - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; - - /* If regular conversion was in progress, restart it */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \ - (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) - { - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART; - } - - /* Update remaining injected conversions */ - hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; - - /* Update DFSDM filter state */ - hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \ - HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG; -} - -/** - * @} - */ -/* End of private functions --------------------------------------------------*/ - -/** - * @} - */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#endif /* HAL_DFSDM_MODULE_ENABLED */ -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c deleted file mode 100644 index 2f3abc5..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c +++ /dev/null @@ -1,1305 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dma.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief DMA HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access (DMA) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and errors functions - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable and configure the peripheral to be connected to the DMA Stream - (except for internal SRAM/FLASH memories: no initialization is - necessary) please refer to Reference manual for connection between peripherals - and DMA requests . - - (#) For a given Stream, program the required configuration through the following parameters: - Transfer Direction, Source and Destination data formats, - Circular, Normal or peripheral flow control mode, Stream Priority level, - Source and Destination Increment mode, FIFO mode and its Threshold (if needed), - Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function. - - *** Polling mode IO operation *** - ================================= - [..] - (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source - address and destination address and the Length of data to be transferred - (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this - case a fixed Timeout can be configured by User depending from his application. - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() - (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() - (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of - Source address and destination address and the Length of data to be transferred. In this - case the DMA interrupt is configured - (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine - (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback and - XferErrorCallback (i.e a member of DMA handle structure). - [..] - (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error - detection. - - (#) Use HAL_DMA_Abort() function to abort the current transfer - - -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. - - -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is - possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set - Half-Word data size for the peripheral to access its data register and set Word data size - for the Memory to gain in access time. Each two half words will be packed and written in - a single access to a Word in the Memory). - - -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source - and Destination. In this case the Peripheral Data Size will be applied to both Source - and Destination. - - *** DMA HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in DMA HAL driver. - - (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream. - (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream. - (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level. - (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts. - (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts. - (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. - - [..] - (@) You can refer to the DMA HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup DMA DMA - * @brief DMA HAL module driver - * @{ - */ - -#ifdef HAL_DMA_MODULE_ENABLED - -/* Private types -------------------------------------------------------------*/ -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register */ - __IO uint32_t Reserved0; - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */ -} DMA_Base_Registers; - -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup DMA_Private_Constants - * @{ - */ - #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)5) /* 5 ms */ -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup DMA_Private_Functions - * @{ - */ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); - -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ -/** @addtogroup DMA_Exported_Functions - * @{ - */ - -/** @addtogroup DMA_Exported_Functions_Group1 - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to initialize the DMA Stream source - and destination addresses, incrementation and data sizes, transfer direction, - circular/normal mode selection, memory-to-memory mode selection and Stream priority value. - [..] - The HAL_DMA_Init() function follows the DMA configuration procedures as described in - reference manual. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the DMA according to the specified - * parameters in the DMA_InitTypeDef and create the associated handle. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) -{ - uint32_t tmp = 0U; - uint32_t tickstart = HAL_GetTick(); - DMA_Base_Registers *regs; - - /* Check the DMA peripheral state */ - if(hdma == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); - assert_param(IS_DMA_CHANNEL(hdma->Init.Channel)); - assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); - assert_param(IS_DMA_MODE(hdma->Init.Mode)); - assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); - assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); - /* Check the memory burst, peripheral burst and FIFO threshold parameters only - when FIFO mode is enabled */ - if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) - { - assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); - assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); - assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); - } - - /* Allocate lock resource */ - __HAL_UNLOCK(hdma); - - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); - - /* Check if the DMA Stream is effectively disabled */ - while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) - { - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - - /* Get the CR register value */ - tmp = hdma->Instance->CR; - - /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ - tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ - DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ - DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ - DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); - - /* Prepare the DMA Stream configuration */ - tmp |= hdma->Init.Channel | hdma->Init.Direction | - hdma->Init.PeriphInc | hdma->Init.MemInc | - hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | - hdma->Init.Mode | hdma->Init.Priority; - - /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ - if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) - { - /* Get memory burst and peripheral burst */ - tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; - } - - /* Write to DMA Stream CR register */ - hdma->Instance->CR = tmp; - - /* Get the FCR register value */ - tmp = hdma->Instance->FCR; - - /* Clear Direct mode and FIFO threshold bits */ - tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); - - /* Prepare the DMA Stream FIFO configuration */ - tmp |= hdma->Init.FIFOMode; - - /* the FIFO threshold is not used when the FIFO mode is disabled */ - if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) - { - /* Get the FIFO threshold */ - tmp |= hdma->Init.FIFOThreshold; - - if (DMA_CheckFifoParam(hdma) != HAL_OK) - { - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_PARAM; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - return HAL_ERROR; - } - } - - /* Write to DMA Stream FCR */ - hdma->Instance->FCR = tmp; - - /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate - DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ - regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); - - /* Clear all interrupt flags */ - regs->IFCR = 0x3FU << hdma->StreamIndex; - - /* Initialize the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Initialize the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the DMA peripheral - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) -{ - DMA_Base_Registers *regs; - - /* Check the DMA peripheral state */ - if(hdma == NULL) - { - return HAL_ERROR; - } - - /* Check the DMA peripheral state */ - if(hdma->State == HAL_DMA_STATE_BUSY) - { - /* Return error status */ - return HAL_BUSY; - } - - /* Disable the selected DMA Streamx */ - __HAL_DMA_DISABLE(hdma); - - /* Reset DMA Streamx control register */ - hdma->Instance->CR = 0U; - - /* Reset DMA Streamx number of data to transfer register */ - hdma->Instance->NDTR = 0U; - - /* Reset DMA Streamx peripheral address register */ - hdma->Instance->PAR = 0U; - - /* Reset DMA Streamx memory 0 address register */ - hdma->Instance->M0AR = 0U; - - /* Reset DMA Streamx memory 1 address register */ - hdma->Instance->M1AR = 0U; - - /* Reset DMA Streamx FIFO control register */ - hdma->Instance->FCR = (uint32_t)0x00000021U; - - /* Get DMA steam Base Address */ - regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); - - /* Clear all interrupt flags at correct offset within the register */ - regs->IFCR = 0x3FU << hdma->StreamIndex; - - /* Initialize the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Initialize the DMA state */ - hdma->State = HAL_DMA_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return HAL_OK; -} - -/** - * @} - */ - -/** @addtogroup DMA_Exported_Functions_Group2 - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the source, destination address and data length and Start DMA transfer - (+) Configure the source, destination address and data length and - Start DMA transfer with interrupt - (+) Abort DMA transfer - (+) Poll for transfer complete - (+) Handle DMA interrupt request - -@endverbatim - * @{ - */ - -/** - * @brief Starts the DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Initialize the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Configure the source, destination address and the data length */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - /* Return error status */ - status = HAL_BUSY; - } - return status; -} - -/** - * @brief Start the DMA Transfer with interrupt enabled. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* calculate DMA base and stream number */ - DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Initialize the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Configure the source, destination address and the data length */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Clear all interrupt flags at correct offset within the register */ - regs->IFCR = 0x3FU << hdma->StreamIndex; - - /* Enable Common interrupts*/ - hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; - hdma->Instance->FCR |= DMA_IT_FE; - - if(hdma->XferHalfCpltCallback != NULL) - { - hdma->Instance->CR |= DMA_IT_HT; - } - - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - /* Return error status */ - status = HAL_BUSY; - } - - return status; -} - -/** - * @brief Aborts the DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * - * @note After disabling a DMA Stream, a check for wait until the DMA Stream is - * effectively disabled is added. If a Stream is disabled - * while a data transfer is ongoing, the current data will be transferred - * and the Stream will be effectively disabled only after the transfer of - * this single data is finished. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) -{ - /* calculate DMA base and stream number */ - DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; - - uint32_t tickstart = HAL_GetTick(); - - if(hdma->State != HAL_DMA_STATE_BUSY) - { - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - else - { - /* Disable all the transfer interrupts */ - hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); - hdma->Instance->FCR &= ~(DMA_IT_FE); - - if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) - { - hdma->Instance->CR &= ~(DMA_IT_HT); - } - - /* Disable the stream */ - __HAL_DMA_DISABLE(hdma); - - /* Check if the DMA Stream is effectively disabled */ - while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) - { - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - - /* Clear all interrupt flags at correct offset within the register */ - regs->IFCR = 0x3FU << hdma->StreamIndex; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Change the DMA state*/ - hdma->State = HAL_DMA_STATE_READY; - } - return HAL_OK; -} - -/** - * @brief Aborts the DMA Transfer in Interrupt mode. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) -{ - if(hdma->State != HAL_DMA_STATE_BUSY) - { - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - return HAL_ERROR; - } - else - { - /* Set Abort State */ - hdma->State = HAL_DMA_STATE_ABORT; - - /* Disable the stream */ - __HAL_DMA_DISABLE(hdma); - } - - return HAL_OK; -} - -/** - * @brief Polling for transfer complete. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param CompleteLevel: Specifies the DMA level complete. - * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead. - * This model could be used for debug purpose. - * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). - * @param Timeout: Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t temp; - uint32_t tickstart = HAL_GetTick(); - uint32_t tmpisr; - - /* calculate DMA base and stream number */ - DMA_Base_Registers *regs; - - /* Polling mode not supported in circular mode and double buffering mode */ - if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET) - { - hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; - return HAL_ERROR; - } - - /* Get the level transfer complete flag */ - if(CompleteLevel == HAL_DMA_FULL_TRANSFER) - { - /* Transfer Complete flag */ - temp = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; - } - else - { - /* Half Transfer Complete flag */ - temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; - } - - regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; - tmpisr = regs->ISR; - - while((tmpisr & temp) == RESET ) - { - /* Check for the Timeout (Not applicable in circular mode)*/ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - return HAL_TIMEOUT; - } - } - - if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) - { - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_TE; - - /* Clear the transfer error flag */ - regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; - } - - if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) - { - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_FE; - - /* Clear the FIFO error flag */ - regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; - } - - if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) - { - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_DME; - - /* Clear the Direct Mode error flag */ - regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; - } - } - - if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) - { - if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) - { - HAL_DMA_Abort(hdma); - - /* Clear the half transfer and transfer complete flags */ - regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Change the DMA state */ - hdma->State= HAL_DMA_STATE_READY; - - return HAL_ERROR; - } - - status = HAL_ERROR; - } - - /* Get the level transfer complete flag */ - if(CompleteLevel == HAL_DMA_FULL_TRANSFER) - { - /* Clear the half transfer and transfer complete flags */ - regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - hdma->State = HAL_DMA_STATE_READY; - } - else - { - /* Clear the half transfer and transfer complete flags */ - regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex; - } - - return status; -} - -/** - * @brief Handles DMA interrupt request. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval None - */ -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) -{ - uint32_t tmpisr; - __IO uint32_t count = 0; - uint32_t timeout = SystemCoreClock / 9600; - - /* calculate DMA base and stream number */ - DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; - - tmpisr = regs->ISR; - - /* Transfer Error Interrupt management ***************************************/ - if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) - { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) - { - /* Disable the transfer error interrupt */ - hdma->Instance->CR &= ~(DMA_IT_TE); - - /* Clear the transfer error flag */ - regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; - - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_TE; - } - } - /* FIFO Error Interrupt management ******************************************/ - if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) - { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) - { - /* Clear the FIFO error flag */ - regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; - - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_FE; - } - } - /* Direct Mode Error Interrupt management ***********************************/ - if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) - { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) - { - /* Clear the direct mode error flag */ - regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; - - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_DME; - } - } - /* Half Transfer Complete Interrupt management ******************************/ - if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) - { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) - { - /* Clear the half transfer complete flag */ - regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; - - /* Multi_Buffering mode enabled */ - if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) - { - /* Current memory buffer used is Memory 0 */ - if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) - { - if(hdma->XferHalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferHalfCpltCallback(hdma); - } - } - /* Current memory buffer used is Memory 1 */ - else - { - if(hdma->XferM1HalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferM1HalfCpltCallback(hdma); - } - } - } - else - { - /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) - { - /* Disable the half transfer interrupt */ - hdma->Instance->CR &= ~(DMA_IT_HT); - } - - if(hdma->XferHalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferHalfCpltCallback(hdma); - } - } - } - } - /* Transfer Complete Interrupt management ***********************************/ - if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) - { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) - { - /* Clear the transfer complete flag */ - regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; - - if(HAL_DMA_STATE_ABORT == hdma->State) - { - /* Disable all the transfer interrupts */ - hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); - hdma->Instance->FCR &= ~(DMA_IT_FE); - - if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) - { - hdma->Instance->CR &= ~(DMA_IT_HT); - } - - /* Clear all interrupt flags at correct offset within the register */ - regs->IFCR = 0x3FU << hdma->StreamIndex; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - if(hdma->XferAbortCallback != NULL) - { - hdma->XferAbortCallback(hdma); - } - return; - } - - if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) - { - /* Current memory buffer used is Memory 0 */ - if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) - { - if(hdma->XferM1CpltCallback != NULL) - { - /* Transfer complete Callback for memory1 */ - hdma->XferM1CpltCallback(hdma); - } - } - /* Current memory buffer used is Memory 1 */ - else - { - if(hdma->XferCpltCallback != NULL) - { - /* Transfer complete Callback for memory0 */ - hdma->XferCpltCallback(hdma); - } - } - } - /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ - else - { - if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) - { - /* Disable the transfer complete interrupt */ - hdma->Instance->CR &= ~(DMA_IT_TC); - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - } - - if(hdma->XferCpltCallback != NULL) - { - /* Transfer complete callback */ - hdma->XferCpltCallback(hdma); - } - } - } - } - - /* manage error case */ - if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) - { - if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) - { - hdma->State = HAL_DMA_STATE_ABORT; - - /* Disable the stream */ - __HAL_DMA_DISABLE(hdma); - - do - { - if (++count > timeout) - { - break; - } - } - while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - } - - if(hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } - } -} - -/** - * @brief Register callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param CallbackID: User Callback identifer - * a DMA_HandleTypeDef structure as parameter. - * @param pCallback: pointer to private callbacsk function which has pointer to - * a DMA_HandleTypeDef structure as parameter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)) -{ - - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - switch (CallbackID) - { - case HAL_DMA_XFER_CPLT_CB_ID: - hdma->XferCpltCallback = pCallback; - break; - - case HAL_DMA_XFER_HALFCPLT_CB_ID: - hdma->XferHalfCpltCallback = pCallback; - break; - - case HAL_DMA_XFER_M1CPLT_CB_ID: - hdma->XferM1CpltCallback = pCallback; - break; - - case HAL_DMA_XFER_M1HALFCPLT_CB_ID: - hdma->XferM1HalfCpltCallback = pCallback; - break; - - case HAL_DMA_XFER_ERROR_CB_ID: - hdma->XferErrorCallback = pCallback; - break; - - case HAL_DMA_XFER_ABORT_CB_ID: - hdma->XferAbortCallback = pCallback; - break; - - default: - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return status; -} - -/** - * @brief UnRegister callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param CallbackID: User Callback identifer - * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - switch (CallbackID) - { - case HAL_DMA_XFER_CPLT_CB_ID: - hdma->XferCpltCallback = NULL; - break; - - case HAL_DMA_XFER_HALFCPLT_CB_ID: - hdma->XferHalfCpltCallback = NULL; - break; - - case HAL_DMA_XFER_M1CPLT_CB_ID: - hdma->XferM1CpltCallback = NULL; - break; - - case HAL_DMA_XFER_M1HALFCPLT_CB_ID: - hdma->XferM1HalfCpltCallback = NULL; - break; - - case HAL_DMA_XFER_ERROR_CB_ID: - hdma->XferErrorCallback = NULL; - break; - - case HAL_DMA_XFER_ABORT_CB_ID: - hdma->XferAbortCallback = NULL; - break; - - case HAL_DMA_XFER_ALL_CB_ID: - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferM1CpltCallback = NULL; - hdma->XferM1HalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - break; - - default: - status = HAL_ERROR; - break; - } - } - else - { - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return status; -} - -/** - * @} - */ - -/** @addtogroup DMA_Exported_Functions_Group3 - * -@verbatim - =============================================================================== - ##### State and Errors functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the DMA state - (+) Get error code - -@endverbatim - * @{ - */ - -/** - * @brief Returns the DMA state. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval HAL state - */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) -{ - return hdma->State; -} - -/** - * @brief Return the DMA error code - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval DMA Error Code - */ -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) -{ - return hdma->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup DMA_Private_Functions - * @{ - */ - -/** - * @brief Sets the DMA Transfer parameter. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status - */ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - /* Clear DBM bit */ - hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); - - /* Configure DMA Stream data length */ - hdma->Instance->NDTR = DataLength; - - /* Peripheral to Memory */ - if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - { - /* Configure DMA Stream destination address */ - hdma->Instance->PAR = DstAddress; - - /* Configure DMA Stream source address */ - hdma->Instance->M0AR = SrcAddress; - } - /* Memory to Peripheral */ - else - { - /* Configure DMA Stream source address */ - hdma->Instance->PAR = SrcAddress; - - /* Configure DMA Stream destination address */ - hdma->Instance->M0AR = DstAddress; - } -} - -/** - * @brief Returns the DMA Stream base address depending on stream number - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval Stream base address - */ -static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) -{ - uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; - - /* lookup table for necessary bitshift of flags within status registers */ - static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; - hdma->StreamIndex = flagBitshiftOffset[stream_number]; - - if (stream_number > 3U) - { - /* return pointer to HISR and HIFCR */ - hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); - } - else - { - /* return pointer to LISR and LIFCR */ - hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); - } - - return hdma->StreamBaseAddress; -} - -/** - * @brief Check compatibility between FIFO threshold level and size of the memory burst - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval HAL status - */ -static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmp = hdma->Init.FIFOThreshold; - - /* Memory Data size equal to Byte */ - if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) - { - switch (tmp) - { - case DMA_FIFO_THRESHOLD_1QUARTERFULL: - if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) - { - status = HAL_ERROR; - } - break; - case DMA_FIFO_THRESHOLD_HALFFULL: - if (hdma->Init.MemBurst == DMA_MBURST_INC16) - { - status = HAL_ERROR; - } - break; - case DMA_FIFO_THRESHOLD_3QUARTERSFULL: - if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) - { - status = HAL_ERROR; - } - break; - case DMA_FIFO_THRESHOLD_FULL: - break; - default: - break; - } - } - - /* Memory Data size equal to Half-Word */ - else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) - { - switch (tmp) - { - case DMA_FIFO_THRESHOLD_1QUARTERFULL: - status = HAL_ERROR; - break; - case DMA_FIFO_THRESHOLD_HALFFULL: - if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) - { - status = HAL_ERROR; - } - break; - case DMA_FIFO_THRESHOLD_3QUARTERSFULL: - status = HAL_ERROR; - break; - case DMA_FIFO_THRESHOLD_FULL: - if (hdma->Init.MemBurst == DMA_MBURST_INC16) - { - status = HAL_ERROR; - } - break; - default: - break; - } - } - - /* Memory Data size equal to Word */ - else - { - switch (tmp) - { - case DMA_FIFO_THRESHOLD_1QUARTERFULL: - case DMA_FIFO_THRESHOLD_HALFFULL: - case DMA_FIFO_THRESHOLD_3QUARTERSFULL: - status = HAL_ERROR; - break; - case DMA_FIFO_THRESHOLD_FULL: - if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) - { - status = HAL_ERROR; - } - break; - default: - break; - } - } - - return status; -} - -/** - * @} - */ - -#endif /* HAL_DMA_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c deleted file mode 100644 index 2aa550a..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c +++ /dev/null @@ -1,1762 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dma2d.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief DMA2D HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the DMA2D peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Program the required configuration through the following parameters: - the transfer mode, the output color mode and the output offset using - HAL_DMA2D_Init() function. - - (#) Program the required configuration through the following parameters: - the input color mode, the input color, the input alpha value, the alpha mode, - the red/blue swap mode, the inverted alpha mode and the input offset using - HAL_DMA2D_ConfigLayer() function for foreground or/and background layer. - - *** Polling mode IO operation *** - ================================= - [..] - (#) Configure pdata parameter (explained hereafter), destination and data length - and enable the transfer using HAL_DMA2D_Start(). - (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage - user can specify the value of timeout according to his end application. - - *** Interrupt mode IO operation *** - =================================== - [..] - (#) Configure pdata parameter, destination and data length and enable - the transfer using HAL_DMA2D_Start_IT(). - (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine. - (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback (member - of DMA2D handle structure). - (#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback - XferErrorCallback. - - -@- In Register-to-Memory transfer mode, pdata parameter is the register - color, in Memory-to-memory or Memory-to-Memory with pixel format - conversion pdata is the source address. - - -@- Configure the foreground source address, the background source address, - the destination and data length then Enable the transfer using - HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT() - in interrupt mode. - - -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions - are used if the memory to memory with blending transfer mode is selected. - - (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling - mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode. - - (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent() - - (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two - consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime() - and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or - HAL_DMA2D_DisableDeadTime(). - - (#) The transfer can be suspended, resumed and aborted using the following - functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort(). - - (#) The CLUT loading can be suspended, resumed and aborted using the following - functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(), - HAL_DMA2D_CLUTLoading_Abort(). - - (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState(). - - (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError(). - - *** DMA2D HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in DMA2D HAL driver : - - (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral. - (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags. - (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags. - (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts. - (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts. - (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not. - - [..] - (@) You can refer to the DMA2D HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup DMA2D DMA2D - * @brief DMA2D HAL module driver - * @{ - */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - -/* Private types -------------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup DMA2D_Private_Constants DMA2D Private Constants - * @{ - */ - -/** @defgroup DMA2D_TimeOut DMA2D Time Out - * @{ - */ -#define DMA2D_TIMEOUT_ABORT ((uint32_t)1000) /*!< 1s */ -#define DMA2D_TIMEOUT_SUSPEND ((uint32_t)1000) /*!< 1s */ -/** - * @} - */ - -/** @defgroup DMA2D_Shifts DMA2D Shifts - * @{ - */ -#define DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS) /*!< Required left shift to set foreground CLUT size */ -#define DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS) /*!< Required left shift to set background CLUT size */ - -#define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM) /*!< Required left shift to set foreground CLUT color mode */ -#define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM) /*!< Required left shift to set background CLUT color mode */ - -#define DMA2D_POSITION_OPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_OPFCCR_AI) /*!< Required left shift to set output alpha inversion */ -#define DMA2D_POSITION_FGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AI) /*!< Required left shift to set foreground alpha inversion */ -#define DMA2D_POSITION_BGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AI) /*!< Required left shift to set background alpha inversion */ - -#define DMA2D_POSITION_OPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_OPFCCR_RBS) /*!< Required left shift to set output Red/Blue swap */ -#define DMA2D_POSITION_FGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_RBS) /*!< Required left shift to set foreground Red/Blue swap */ -#define DMA2D_POSITION_BGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_RBS) /*!< Required left shift to set background Red/Blue swap */ - -#define DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT) /*!< Required left shift to set deadtime value */ - -#define DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM) /*!< Required left shift to set foreground alpha mode */ -#define DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM) /*!< Required left shift to set background alpha mode */ - -#define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /*!< Required left shift to set foreground alpha value */ -#define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /*!< Required left shift to set background alpha value */ - -#define DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL) /*!< Required left shift to set pixels per lines value */ -/** - * @} - */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup DMA2D_Private_Functions_Prototypes - * @{ - */ -static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions - * @{ - */ - -/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the DMA2D - (+) De-initialize the DMA2D - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the DMA2D according to the specified - * parameters in the DMA2D_InitTypeDef and create the associated handle. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) -{ - /* Check the DMA2D peripheral state */ - if(hdma2d == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance)); - assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode)); - assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode)); - assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset)); - - if(hdma2d->State == HAL_DMA2D_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hdma2d->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ - HAL_DMA2D_MspInit(hdma2d); - } - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* DMA2D CR register configuration -------------------------------------------*/ - MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode); - - /* DMA2D OPFCCR register configuration ---------------------------------------*/ - MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode); - - /* DMA2D OOR register configuration ------------------------------------------*/ - MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); - -#if defined (DMA2D_OPFCCR_AI) - /* DMA2D OPFCCR AI fields setting (Output Alpha Inversion)*/ - MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_AI, (hdma2d->Init.AlphaInverted << DMA2D_POSITION_OPFCCR_AI)); -#endif /* DMA2D_OPFCCR_AI */ - -#if defined (DMA2D_OPFCCR_RBS) - MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_RBS,(hdma2d->Init.RedBlueSwap << DMA2D_POSITION_OPFCCR_RBS)); -#endif /* DMA2D_OPFCCR_RBS */ - - - /* Update error code */ - hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; - - /* Initialize the DMA2D state*/ - hdma2d->State = HAL_DMA2D_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Deinitializes the DMA2D peripheral registers to their default reset - * values. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval None - */ - -HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) -{ - - /* Check the DMA2D peripheral state */ - if(hdma2d == NULL) - { - return HAL_ERROR; - } - - /* Before aborting any DMA2D transfer or CLUT loading, check - first whether or not DMA2D clock is enabled */ - if (__HAL_RCC_DMA2D_IS_CLK_ENABLED()) - { - /* Abort DMA2D transfer if any */ - if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START) - { - if (HAL_DMA2D_Abort(hdma2d) != HAL_OK) - { - /* Issue when aborting DMA2D transfer */ - return HAL_ERROR; - } - } - else - { - /* Abort background CLUT loading if any */ - if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START) - { - if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0) != HAL_OK) - { - /* Issue when aborting background CLUT loading */ - return HAL_ERROR; - } - } - else - { - /* Abort foreground CLUT loading if any */ - if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START) - { - if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1) != HAL_OK) - { - /* Issue when aborting foreground CLUT loading */ - return HAL_ERROR; - } - } - } - } - } - - - /* Carry on with de-initialization of low level hardware */ - HAL_DMA2D_MspDeInit(hdma2d); - - /* Reset DMA2D control registers*/ - hdma2d->Instance->CR = 0; - hdma2d->Instance->FGOR = 0; - hdma2d->Instance->BGOR = 0; - hdma2d->Instance->FGPFCCR = 0; - hdma2d->Instance->BGPFCCR = 0; - hdma2d->Instance->OPFCCR = 0; - - /* Update error code */ - hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; - - /* Initialize the DMA2D state*/ - hdma2d->State = HAL_DMA2D_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hdma2d); - - return HAL_OK; -} - -/** - * @brief Initializes the DMA2D MSP. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval None - */ -__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma2d); - - /* NOTE : This function should not be modified; when the callback is needed, - the HAL_DMA2D_MspInit can be implemented in the user file. - */ -} - -/** - * @brief DeInitializes the DMA2D MSP. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval None - */ -__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma2d); - - /* NOTE : This function should not be modified; when the callback is needed, - the HAL_DMA2D_MspDeInit can be implemented in the user file. - */ -} - -/** - * @} - */ - - -/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the pdata, destination address and data size then - start the DMA2D transfer. - (+) Configure the source for foreground and background, destination address - and data size then start a MultiBuffer DMA2D transfer. - (+) Configure the pdata, destination address and data size then - start the DMA2D transfer with interrupt. - (+) Configure the source for foreground and background, destination address - and data size then start a MultiBuffer DMA2D transfer with interrupt. - (+) Abort DMA2D transfer. - (+) Suspend DMA2D transfer. - (+) Resume DMA2D transfer. - (+) Enable CLUT transfer. - (+) Configure CLUT loading then start transfer in polling mode. - (+) Configure CLUT loading then start transfer in interrupt mode. - (+) Abort DMA2D CLUT loading. - (+) Suspend DMA2D CLUT loading. - (+) Resume DMA2D CLUT loading. - (+) Poll for transfer complete. - (+) handle DMA2D interrupt request. - (+) Transfer watermark callback. - (+) CLUT Transfer Complete callback. - - -@endverbatim - * @{ - */ - -/** - * @brief Start the DMA2D Transfer. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param pdata: Configure the source memory Buffer address if - * Memory-to-Memory or Memory-to-Memory with pixel format - * conversion mode is selected, or configure - * the color value if Register-to-Memory mode is selected. - * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). - * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_LINE(Height)); - assert_param(IS_DMA2D_PIXEL(Width)); - - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Configure the source, destination address and the data size */ - DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); - - /* Enable the Peripheral */ - __HAL_DMA2D_ENABLE(hdma2d); - - return HAL_OK; -} - -/** - * @brief Start the DMA2D Transfer with interrupt enabled. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param pdata: Configure the source memory Buffer address if - * the Memory-to-Memory or Memory-to-Memory with pixel format - * conversion mode is selected, or configure - * the color value if Register-to-Memory mode is selected. - * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). - * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_LINE(Height)); - assert_param(IS_DMA2D_PIXEL(Width)); - - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Configure the source, destination address and the data size */ - DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); - - /* Enable the transfer complete, transfer error and configuration error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); - - /* Enable the Peripheral */ - __HAL_DMA2D_ENABLE(hdma2d); - - return HAL_OK; -} - -/** - * @brief Start the multi-source DMA2D Transfer. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param SrcAddress1: The source memory Buffer address for the foreground layer. - * @param SrcAddress2: The source memory Buffer address for the background layer. - * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). - * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_LINE(Height)); - assert_param(IS_DMA2D_PIXEL(Width)); - - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Configure DMA2D Stream source2 address */ - WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); - - /* Configure the source, destination address and the data size */ - DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); - - /* Enable the Peripheral */ - __HAL_DMA2D_ENABLE(hdma2d); - - return HAL_OK; -} - -/** - * @brief Start the multi-source DMA2D Transfer with interrupt enabled. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param SrcAddress1: The source memory Buffer address for the foreground layer. - * @param SrcAddress2: The source memory Buffer address for the background layer. - * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). - * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_LINE(Height)); - assert_param(IS_DMA2D_PIXEL(Width)); - - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Configure DMA2D Stream source2 address */ - WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); - - /* Configure the source, destination address and the data size */ - DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); - - /* Enable the transfer complete, transfer error and configuration error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); - - /* Enable the Peripheral */ - __HAL_DMA2D_ENABLE(hdma2d); - - return HAL_OK; -} - -/** - * @brief Abort the DMA2D Transfer. - * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) -{ - uint32_t tickstart = 0; - - /* Abort the DMA2D transfer */ - /* START bit is reset to make sure not to set it again, in the event the HW clears it - between the register read and the register write by the CPU (writing ‘0’ has no - effect on START bitvalue). */ - MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check if the DMA2D is effectively disabled */ - while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET) - { - if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT) - { - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - - /* Change the DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_TIMEOUT; - } - } - - /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); - - /* Change the DMA2D state*/ - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_OK; -} - -/** - * @brief Suspend the DMA2D Transfer. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) -{ - uint32_t tickstart = 0; - - /* Suspend the DMA2D transfer */ - /* START bit is reset to make sure not to set it again, in the event the HW clears it - between the register read and the register write by the CPU (writing ‘0’ has no - effect on START bitvalue). */ - MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check if the DMA2D is effectively suspended */ - while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \ - && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)) - { - if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND) - { - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - - /* Change the DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - - /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ - if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET) - { - hdma2d->State = HAL_DMA2D_STATE_SUSPEND; - } - else - { - /* Make sure SUSP bit is cleared since it is meaningless - when no tranfer is on-going */ - CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); - } - - return HAL_OK; -} - -/** - * @brief Resume the DMA2D Transfer. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) -{ - /* Check the SUSP and START bits */ - if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START)) - { - /* Ongoing transfer is suspended: change the DMA2D state before resuming */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - } - - /* Resume the DMA2D transfer */ - /* START bit is reset to make sure not to set it again, in the event the HW clears it - between the register read and the register write by the CPU (writing ‘0’ has no - effect on START bitvalue). */ - CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START)); - - return HAL_OK; -} - - -/** - * @brief Enable the DMA2D CLUT Transfer. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. - * This parameter can be one of the following values: - * 0(background) / 1(foreground) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); - - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - if(LayerIdx == 0) - { - /* Enable the background CLUT loading */ - SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); - } - else - { - /* Enable the foreground CLUT loading */ - SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); - } - - return HAL_OK; -} - - -/** - * @brief Start DMA2D CLUT Loading. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains - * the configuration information for the color look up table. - * @param LayerIdx: DMA2D Layer index. - * This parameter can be one of the following values: - * 0(background) / 1(foreground) - * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT(). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); - assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); - assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); - - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Configure the CLUT of the background DMA2D layer */ - if(LayerIdx == 0) - { - /* Write background CLUT memory address */ - WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); - - /* Write background CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM))); - - /* Enable the CLUT loading for the background */ - SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); - } - /* Configure the CLUT of the foreground DMA2D layer */ - else - { - /* Write foreground CLUT memory address */ - WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); - - /* Write foreground CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM))); - - /* Enable the CLUT loading for the foreground */ - SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); - } - - return HAL_OK; -} - -/** - * @brief Start DMA2D CLUT Loading with interrupt enabled. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains - * the configuration information for the color look up table. - * @param LayerIdx: DMA2D Layer index. - * This parameter can be one of the following values: - * 0(background) / 1(foreground) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); - assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); - assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); - - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Configure the CLUT of the background DMA2D layer */ - if(LayerIdx == 0) - { - /* Write background CLUT memory address */ - WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); - - /* Write background CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM))); - - /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); - - /* Enable the CLUT loading for the background */ - SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); - } - /* Configure the CLUT of the foreground DMA2D layer */ - else - { - /* Write foreground CLUT memory address */ - WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); - - /* Write foreground CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM))); - - /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); - - /* Enable the CLUT loading for the foreground */ - SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); - } - - return HAL_OK; -} - -/** - * @brief Abort the DMA2D CLUT loading. - * @param hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. - * This parameter can be one of the following values: - * 0(background) / 1(foreground) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) -{ - uint32_t tickstart = 0; - __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ - - /* Abort the CLUT loading */ - SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT); - - /* If foreground CLUT loading is considered, update local variables */ - if(LayerIdx == 1) - { - reg = &(hdma2d->Instance->FGPFCCR); - } - - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check if the CLUT loading is aborted */ - while((*reg & DMA2D_BGPFCCR_START) != RESET) - { - if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT) - { - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - - /* Change the DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_TIMEOUT; - } - } - - /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); - - /* Change the DMA2D state*/ - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_OK; -} - -/** - * @brief Suspend the DMA2D CLUT loading. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. - * This parameter can be one of the following values: - * 0(background) / 1(foreground) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) -{ - uint32_t tickstart = 0; - __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ - - /* Suspend the CLUT loading */ - SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); - - /* If foreground CLUT loading is considered, update local variables */ - if(LayerIdx == 1) - { - reg = &(hdma2d->Instance->FGPFCCR); - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check if the CLUT loading is suspended */ - while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \ - && ((*reg & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)) - { - if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND) - { - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - - /* Change the DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - - /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ - if ((*reg & DMA2D_BGPFCCR_START) != RESET) - { - hdma2d->State = HAL_DMA2D_STATE_SUSPEND; - } - else - { - /* Make sure SUSP bit is cleared since it is meaningless - when no tranfer is on-going */ - CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); - } - - return HAL_OK; -} - -/** - * @brief Resume the DMA2D CLUT loading. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. - * This parameter can be one of the following values: - * 0(background) / 1(foreground) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) -{ - /* Check the SUSP and START bits for background or foreground CLUT loading */ - if(LayerIdx == 0) - { - /* Background CLUT loading suspension check */ - if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) - && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)) - { - /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - } - } - else - { - /* Foreground CLUT loading suspension check */ - if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) - && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)) - { - /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - } - } - - /* Resume the CLUT loading */ - CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); - - return HAL_OK; -} - - -/** - - * @brief Polling for transfer complete or CLUT loading. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout) -{ - uint32_t tickstart = 0; - __IO uint32_t isrflags = 0x0; - - /* Polling for DMA2D transfer */ - if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET) - { - isrflags = READ_REG(hdma2d->Instance->ISR); - if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET) - { - if ((isrflags & DMA2D_FLAG_CE) != RESET) - { - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; - } - if ((isrflags & DMA2D_FLAG_TE) != RESET) - { - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; - } - /* Clear the transfer and configuration error flags */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE); - - /* Change DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_ERROR; - } - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - - /* Change the DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; - - /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_TIMEOUT; - } - } - } - } - /* Polling for CLUT loading (foreground or background) */ - if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET) || - ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET)) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET) - { - isrflags = READ_REG(hdma2d->Instance->ISR); - if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET) - { - if ((isrflags & DMA2D_FLAG_CAE) != RESET) - { - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; - } - if ((isrflags & DMA2D_FLAG_CE) != RESET) - { - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; - } - if ((isrflags & DMA2D_FLAG_TE) != RESET) - { - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; - } - /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE); - - /* Change DMA2D state */ - hdma2d->State= HAL_DMA2D_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_ERROR; - } - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - - /* Change the DMA2D state */ - hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; - - /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_TIMEOUT; - } - } - } - } - - /* Clear the transfer complete and CLUT loading flags */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC); - - /* Change DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_OK; -} -/** - * @brief Handle DMA2D interrupt request. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval HAL status - */ -void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) -{ - uint32_t isrflags = READ_REG(hdma2d->Instance->ISR); - uint32_t crflags = READ_REG(hdma2d->Instance->CR); - - /* Transfer Error Interrupt management ***************************************/ - if ((isrflags & DMA2D_FLAG_TE) != RESET) - { - if ((crflags & DMA2D_IT_TE) != RESET) - { - /* Disable the transfer Error interrupt */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE); - - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; - - /* Clear the transfer error flag */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE); - - /* Change DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - if(hdma2d->XferErrorCallback != NULL) - { - /* Transfer error Callback */ - hdma2d->XferErrorCallback(hdma2d); - } - } - } - /* Configuration Error Interrupt management **********************************/ - if ((isrflags & DMA2D_FLAG_CE) != RESET) - { - if ((crflags & DMA2D_IT_CE) != RESET) - { - /* Disable the Configuration Error interrupt */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE); - - /* Clear the Configuration error flag */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE); - - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; - - /* Change DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - if(hdma2d->XferErrorCallback != NULL) - { - /* Transfer error Callback */ - hdma2d->XferErrorCallback(hdma2d); - } - } - } - /* CLUT access Error Interrupt management ***********************************/ - if ((isrflags & DMA2D_FLAG_CAE) != RESET) - { - if ((crflags & DMA2D_IT_CAE) != RESET) - { - /* Disable the CLUT access error interrupt */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE); - - /* Clear the CLUT access error flag */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE); - - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; - - /* Change DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - if(hdma2d->XferErrorCallback != NULL) - { - /* Transfer error Callback */ - hdma2d->XferErrorCallback(hdma2d); - } - } - } - /* Transfer watermark Interrupt management **********************************/ - if ((isrflags & DMA2D_FLAG_TW) != RESET) - { - if ((crflags & DMA2D_IT_TW) != RESET) - { - /* Disable the transfer watermark interrupt */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW); - - /* Clear the transfer watermark flag */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW); - - /* Transfer watermark Callback */ - HAL_DMA2D_LineEventCallback(hdma2d); - } - } - /* Transfer Complete Interrupt management ************************************/ - if ((isrflags & DMA2D_FLAG_TC) != RESET) - { - if ((crflags & DMA2D_IT_TC) != RESET) - { - /* Disable the transfer complete interrupt */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC); - - /* Clear the transfer complete flag */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC); - - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; - - /* Change DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - if(hdma2d->XferCpltCallback != NULL) - { - /* Transfer complete Callback */ - hdma2d->XferCpltCallback(hdma2d); - } - } - } - /* CLUT Transfer Complete Interrupt management ******************************/ - if ((isrflags & DMA2D_FLAG_CTC) != RESET) - { - if ((crflags & DMA2D_IT_CTC) != RESET) - { - /* Disable the CLUT transfer complete interrupt */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC); - - /* Clear the CLUT transfer complete flag */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC); - - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; - - /* Change DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - /* CLUT Transfer complete Callback */ - HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d); - } - } - -} - -/** - * @brief Transfer watermark callback. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval None - */ -__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma2d); - - /* NOTE : This function should not be modified; when the callback is needed, - the HAL_DMA2D_LineEventCallback can be implemented in the user file. - */ -} - -/** - * @brief CLUT Transfer Complete callback. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval None - */ -__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma2d); - - /* NOTE : This function should not be modified; when the callback is needed, - the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the DMA2D foreground or background layer parameters. - (+) Configure the DMA2D CLUT transfer. - (+) Configure the line watermark - (+) Configure the dead time value. - (+) Enable or disable the dead time value functionality. - - -@endverbatim - * @{ - */ - -/** - * @brief Configure the DMA2D Layer according to the specified - * parameters in the DMA2D_InitTypeDef and create the associated handle. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. - * This parameter can be one of the following values: - * 0(background) / 1(foreground) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) -{ - DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx]; - - uint32_t regMask = 0, regValue = 0; - - /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); - assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset)); - if(hdma2d->Init.Mode != DMA2D_R2M) - { - assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode)); - if(hdma2d->Init.Mode != DMA2D_M2M) - { - assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode)); - } - } - - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* DMA2D BGPFCR register configuration -----------------------------------*/ - /* Prepare the value to be written to the BGPFCCR register */ - - regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM); - regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA; - -#if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI) - regValue |= (pLayerCfg->AlphaInverted << DMA2D_POSITION_BGPFCCR_AI); - regMask |= DMA2D_BGPFCCR_AI; -#endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI) */ - -#if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS) - regValue |= (pLayerCfg->RedBlueSwap << DMA2D_POSITION_BGPFCCR_RBS); - regMask |= DMA2D_BGPFCCR_RBS; -#endif - - if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) - { - regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA); - } - else - { - regValue |= (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA); - } - - /* Configure the background DMA2D layer */ - if(LayerIdx == 0) - { - /* Write DMA2D BGPFCCR register */ - MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue); - - /* DMA2D BGOR register configuration -------------------------------------*/ - WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset); - - /* DMA2D BGCOLR register configuration -------------------------------------*/ - if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) - { - WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED)); - } - } - /* Configure the foreground DMA2D layer */ - else - { - /* Write DMA2D FGPFCCR register */ - MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue); - - /* DMA2D FGOR register configuration -------------------------------------*/ - WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset); - - /* DMA2D FGCOLR register configuration -------------------------------------*/ - if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) - { - WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED)); - } - } - /* Initialize the DMA2D state*/ - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_OK; -} - -/** - * @brief Configure the DMA2D CLUT Transfer. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains - * the configuration information for the color look up table. - * @param LayerIdx: DMA2D Layer index. - * This parameter can be one of the following values: - * 0(background) / 1(foreground) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); - assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); - assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); - - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Configure the CLUT of the background DMA2D layer */ - if(LayerIdx == 0) - { - /* Write background CLUT memory address */ - WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); - - /* Write background CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM))); - } - /* Configure the CLUT of the foreground DMA2D layer */ - else - { - /* Write foreground CLUT memory address */ - WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); - - /* Write foreground CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM))); - } - - /* Set the DMA2D state to Ready*/ - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_OK; -} - - -/** - * @brief Configure the line watermark. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param Line: Line Watermark configuration (maximum 16-bit long value expected). - * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt. - * @note The transfer watermark interrupt is disabled once it has occurred. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_LINEWATERMARK(Line)); - - if (Line > DMA2D_LWR_LW) - { - return HAL_ERROR; - } - else - { - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Sets the Line watermark configuration */ - WRITE_REG(hdma2d->Instance->LWR, Line); - - /* Enable the Line interrupt */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW); - - /* Initialize the DMA2D state*/ - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_OK; - } -} - -/** - * @brief Enable DMA2D dead time feature. - * @param hdma2d: DMA2D handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d) -{ - /* Process Locked */ - __HAL_LOCK(hdma2d); - - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Set DMA2D_AMTCR EN bit */ - SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); - - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_OK; -} - -/** - * @brief Disable DMA2D dead time feature. - * @param hdma2d: DMA2D handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d) -{ - /* Process Locked */ - __HAL_LOCK(hdma2d); - - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Clear DMA2D_AMTCR EN bit */ - CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); - - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_OK; -} - -/** - * @brief Configure dead time. - * @note The dead time value represents the guaranteed minimum number of cycles between - * two consecutive transactions on the AHB bus. - * @param hdma2d: DMA2D handle. - * @param DeadTime: dead time value. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime) -{ - /* Process Locked */ - __HAL_LOCK(hdma2d); - - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Set DMA2D_AMTCR DT field */ - MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT)); - - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_OK; -} - -/** - * @} - */ - - -/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to : - (+) Get the DMA2D state - (+) Get the DMA2D error code - -@endverbatim - * @{ - */ - -/** - * @brief Return the DMA2D state - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval HAL state - */ -HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d) -{ - return hdma2d->State; -} - -/** - * @brief Return the DMA2D error code - * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for DMA2D. - * @retval DMA2D Error Code - */ -uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d) -{ - return hdma2d->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup DMA2D_Private_Functions DMA2D Private Functions - * @{ - */ - -/** - * @brief Set the DMA2D transfer parameters. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the specified DMA2D. - * @param pdata: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param Width: The width of data to be transferred from source to destination. - * @param Height: The height of data to be transferred from source to destination. - * @retval HAL status - */ -static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) -{ - uint32_t tmp = 0; - uint32_t tmp1 = 0; - uint32_t tmp2 = 0; - uint32_t tmp3 = 0; - uint32_t tmp4 = 0; - - /* Configure DMA2D data size */ - MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL))); - - /* Configure DMA2D destination address */ - WRITE_REG(hdma2d->Instance->OMAR, DstAddress); - - /* Register to memory DMA2D mode selected */ - if (hdma2d->Init.Mode == DMA2D_R2M) - { - tmp1 = pdata & DMA2D_OCOLR_ALPHA_1; - tmp2 = pdata & DMA2D_OCOLR_RED_1; - tmp3 = pdata & DMA2D_OCOLR_GREEN_1; - tmp4 = pdata & DMA2D_OCOLR_BLUE_1; - - /* Prepare the value to be written to the OCOLR register according to the color mode */ - if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888) - { - tmp = (tmp3 | tmp2 | tmp1| tmp4); - } - else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888) - { - tmp = (tmp3 | tmp2 | tmp4); - } - else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565) - { - tmp2 = (tmp2 >> 19); - tmp3 = (tmp3 >> 10); - tmp4 = (tmp4 >> 3 ); - tmp = ((tmp3 << 5) | (tmp2 << 11) | tmp4); - } - else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555) - { - tmp1 = (tmp1 >> 31); - tmp2 = (tmp2 >> 19); - tmp3 = (tmp3 >> 11); - tmp4 = (tmp4 >> 3 ); - tmp = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4); - } - else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */ - { - tmp1 = (tmp1 >> 28); - tmp2 = (tmp2 >> 20); - tmp3 = (tmp3 >> 12); - tmp4 = (tmp4 >> 4 ); - tmp = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4); - } - /* Write to DMA2D OCOLR register */ - WRITE_REG(hdma2d->Instance->OCOLR, tmp); - } - else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */ - { - /* Configure DMA2D source address */ - WRITE_REG(hdma2d->Instance->FGMAR, pdata); - } -} - -/** - * @} - */ -#endif /* HAL_DMA2D_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c deleted file mode 100644 index 5a953b7..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c +++ /dev/null @@ -1,328 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dma_ex.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief DMA Extension HAL module driver - * This file provides firmware functions to manage the following - * functionalities of the DMA Extension peripheral: - * + Extended features functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The DMA Extension HAL driver can be used as follows: - (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function - for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode. - - -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed. - -@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default. - -@- In Multi (Double) buffer mode, it is possible to update the base address for - the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup DMAEx DMAEx - * @brief DMA Extended HAL module driver - * @{ - */ - -#ifdef HAL_DMA_MODULE_ENABLED - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private Constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup DMAEx_Private_Functions - * @{ - */ - -static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); - -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @addtogroup DMAEx_Exported_Functions - * @{ - */ - - -/** @addtogroup DMAEx_Exported_Functions_Group1 - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the source, destination address and data length and - Start MultiBuffer DMA transfer - (+) Configure the source, destination address and data length and - Start MultiBuffer DMA transfer with interrupt - (+) Change on the fly the memory0 or memory1 address. - -@endverbatim - * @{ - */ - - -/** - * @brief Starts the multi_buffer DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer - * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Memory-to-memory transfer not supported in double buffering mode */ - if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) - { - hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; - status = HAL_ERROR; - } - else - { - /* Process Locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Enable the double buffer mode */ - hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; - - /* Configure DMA Stream destination address */ - hdma->Instance->M1AR = SecondMemAddress; - - /* Configure the source, destination address and the data length */ - DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the peripheral */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Return error status */ - status = HAL_BUSY; - } - } - return status; -} - -/** - * @brief Starts the multi_buffer DMA Transfer with interrupt enabled. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer - * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Memory-to-memory transfer not supported in double buffering mode */ - if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) - { - hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Initialize the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Enable the Double buffer mode */ - hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; - - /* Configure DMA Stream destination address */ - hdma->Instance->M1AR = SecondMemAddress; - - /* Configure the source, destination address and the data length */ - DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Clear all flags */ - __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); - - /* Enable Common interrupts*/ - hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; - hdma->Instance->FCR |= DMA_IT_FE; - - if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) - { - hdma->Instance->CR |= DMA_IT_HT; - } - - /* Enable the peripheral */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - /* Return error status */ - status = HAL_BUSY; - } - return status; -} - -/** - * @brief Change the memory0 or memory1 address on the fly. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param Address: The new address - * @param memory: the memory to be changed, This parameter can be one of - * the following values: - * MEMORY0 / - * MEMORY1 - * @note The MEMORY0 address can be changed only when the current transfer use - * MEMORY1 and the MEMORY1 address can be changed only when the current - * transfer use MEMORY0. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory) -{ - if(memory == MEMORY0) - { - /* change the memory0 address */ - hdma->Instance->M0AR = Address; - } - else - { - /* change the memory1 address */ - hdma->Instance->M1AR = Address; - } - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup DMAEx_Private_Functions - * @{ - */ - -/** - * @brief Set the DMA Transfer parameter. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status - */ -static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - /* Configure DMA Stream data length */ - hdma->Instance->NDTR = DataLength; - - /* Peripheral to Memory */ - if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - { - /* Configure DMA Stream destination address */ - hdma->Instance->PAR = DstAddress; - - /* Configure DMA Stream source address */ - hdma->Instance->M0AR = SrcAddress; - } - /* Memory to Peripheral */ - else - { - /* Configure DMA Stream source address */ - hdma->Instance->PAR = SrcAddress; - - /* Configure DMA Stream destination address */ - hdma->Instance->M0AR = DstAddress; - } -} - -/** - * @} - */ - -#endif /* HAL_DMA_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c deleted file mode 100644 index d8b889b..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c +++ /dev/null @@ -1,2266 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dsi.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief DSI HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the DSI peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -/** @addtogroup DSI - * @{ - */ - -#ifdef HAL_DSI_MODULE_ENABLED - -#if defined (STM32F769xx) || defined (STM32F779xx) - -/* Private types -------------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/** @addtogroup DSI_Private_Constants - * @{ - */ -#define DSI_TIMEOUT_VALUE ((uint32_t)1000) /* 1s */ - -#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \ - DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \ - DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \ - DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15) -#define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4) -#define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX -#define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX -#define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME) -#define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE -#define DSI_ERROR_PSE_MASK DSI_ISR1_PSE -#define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE -#define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE -#define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE) -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1); - -/* Private functions ---------------------------------------------------------*/ -/** - * @brief Generic DSI packet header configuration - * @param DSIx: Pointer to DSI register base - * @param ChannelID: Virtual channel ID of the header packet - * @param DataType: Packet data type of the header packet - * This parameter can be any value of : - * @ref DSI_SHORT_WRITE_PKT_Data_Type - * or @ref DSI_LONG_WRITE_PKT_Data_Type - * or @ref DSI_SHORT_READ_PKT_Data_Type - * or DSI_MAX_RETURN_PKT_SIZE - * @param Data0: Word count LSB - * @param Data1: Word count MSB - * @retval None - */ -static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, - uint32_t ChannelID, - uint32_t DataType, - uint32_t Data0, - uint32_t Data1) -{ - /* Update the DSI packet header with new information */ - DSIx->GHCR = (DataType | (ChannelID<<6) | (Data0<<8) | (Data1<<16)); -} - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup DSI_Exported_Functions - * @{ - */ - -/** @defgroup DSI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the DSI - (+) De-initialize the DSI - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the DSI according to the specified - * parameters in the DSI_InitTypeDef and create the associated handle. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains - * the PLL Clock structure definition for the DSI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit) -{ - uint32_t tickstart = 0; - uint32_t unitIntervalx4 = 0; - uint32_t tempIDF = 0; - - /* Check the DSI handle allocation */ - if(hdsi == NULL) - { - return HAL_ERROR; - } - - /* Check function parameters */ - assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV)); - assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF)); - assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF)); - assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl)); - assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes)); - - if(hdsi->State == HAL_DSI_STATE_RESET) - { - /* Initialize the low level hardware */ - HAL_DSI_MspInit(hdsi); - } - - /* Change DSI peripheral state */ - hdsi->State = HAL_DSI_STATE_BUSY; - - /**************** Turn on the regulator and enable the DSI PLL ****************/ - - /* Enable the regulator */ - __HAL_DSI_REG_ENABLE(hdsi); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until the regulator is ready */ - while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Set the PLL division factors */ - hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); - hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2) | ((PLLInit->PLLIDF)<<11) | ((PLLInit->PLLODF)<<16)); - - /* Enable the DSI PLL */ - __HAL_DSI_PLL_ENABLE(hdsi); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for the lock of the PLL */ - while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /*************************** Set the PHY parameters ***************************/ - - /* D-PHY clock and digital enable*/ - hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN); - - /* Clock lane configuration */ - hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR); - hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl); - - /* Configure the number of active data lanes */ - hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; - hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; - - /************************ Set the DSI clock parameters ************************/ - - /* Set the TX escape clock division factor */ - hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; - hdsi->Instance->CCR = hdsi->Init.TXEscapeCkdiv; - - /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */ - /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */ - /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */ - tempIDF = (PLLInit->PLLIDF > 0) ? PLLInit->PLLIDF : 1; - unitIntervalx4 = (4000000 * tempIDF * (1 << PLLInit->PLLODF)) / ((HSE_VALUE/1000) * PLLInit->PLLNDIV); - - /* Set the bit period in high-speed mode */ - hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_UIX4; - hdsi->Instance->WPCR[0] |= unitIntervalx4; - - /****************************** Error management *****************************/ - - /* Disable all error interrupts and reset the Error Mask */ - hdsi->Instance->IER[0] = 0; - hdsi->Instance->IER[1] = 0; - hdsi->ErrorMsk = 0; - - /* Initialise the error code */ - hdsi->ErrorCode = HAL_DSI_ERROR_NONE; - - /* Initialize the DSI state*/ - hdsi->State = HAL_DSI_STATE_READY; - - return HAL_OK; -} - -/** - * @brief De-initializes the DSI peripheral registers to their default reset - * values. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi) -{ - /* Check the DSI handle allocation */ - if(hdsi == NULL) - { - return HAL_ERROR; - } - - /* Change DSI peripheral state */ - hdsi->State = HAL_DSI_STATE_BUSY; - - /* Disable the DSI wrapper */ - __HAL_DSI_WRAPPER_DISABLE(hdsi); - - /* Disable the DSI host */ - __HAL_DSI_DISABLE(hdsi); - - /* D-PHY clock and digital disable */ - hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN); - - /* Turn off the DSI PLL */ - __HAL_DSI_PLL_DISABLE(hdsi); - - /* Disable the regulator */ - __HAL_DSI_REG_DISABLE(hdsi); - - /* DeInit the low level hardware */ - HAL_DSI_MspDeInit(hdsi); - - /* Initialise the error code */ - hdsi->ErrorCode = HAL_DSI_ERROR_NONE; - - /* Initialize the DSI state*/ - hdsi->State = HAL_DSI_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Return the DSI error code - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval DSI Error Code - */ -uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi) -{ - /* Get the error code */ - return hdsi->ErrorCode; -} - -/** - * @brief Enable the error monitor flags - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param ActiveErrors: indicates which error interrupts will be enabled. - * This parameter can be any combination of @ref DSI_Error_Data_Type. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - hdsi->Instance->IER[0] = 0; - hdsi->Instance->IER[1] = 0; - - /* Store active errors to the handle */ - hdsi->ErrorMsk = ActiveErrors; - - if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET) - { - /* Enable the interrupt generation on selected errors */ - hdsi->Instance->IER[0] |= DSI_ERROR_ACK_MASK; - } - - if((ActiveErrors & HAL_DSI_ERROR_PHY ) != RESET) - { - /* Enable the interrupt generation on selected errors */ - hdsi->Instance->IER[0] |= DSI_ERROR_PHY_MASK; - } - - if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET) - { - /* Enable the interrupt generation on selected errors */ - hdsi->Instance->IER[1] |= DSI_ERROR_TX_MASK; - } - - if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET) - { - /* Enable the interrupt generation on selected errors */ - hdsi->Instance->IER[1] |= DSI_ERROR_RX_MASK; - } - - if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET) - { - /* Enable the interrupt generation on selected errors */ - hdsi->Instance->IER[1] |= DSI_ERROR_ECC_MASK; - } - - if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET) - { - /* Enable the interrupt generation on selected errors */ - hdsi->Instance->IER[1] |= DSI_ERROR_CRC_MASK; - } - - if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET) - { - /* Enable the interrupt generation on selected errors */ - hdsi->Instance->IER[1] |= DSI_ERROR_PSE_MASK; - } - - if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET) - { - /* Enable the interrupt generation on selected errors */ - hdsi->Instance->IER[1] |= DSI_ERROR_EOT_MASK; - } - - if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET) - { - /* Enable the interrupt generation on selected errors */ - hdsi->Instance->IER[1] |= DSI_ERROR_OVF_MASK; - } - - if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET) - { - /* Enable the interrupt generation on selected errors */ - hdsi->Instance->IER[1] |= DSI_ERROR_GEN_MASK; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Initializes the DSI MSP. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval None - */ -__weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdsi); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DSI_MspInit could be implemented in the user file - */ -} - -/** - * @brief De-initializes the DSI MSP. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval None - */ -__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdsi); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DSI_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup DSI_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides function allowing to: - (+) Handle DSI interrupt request - -@endverbatim - * @{ - */ -/** - * @brief Handles DSI interrupt request. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL status - */ -void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) -{ - uint32_t ErrorStatus0, ErrorStatus1; - - /* Tearing Effect Interrupt management ***************************************/ - if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET) - { - if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET) - { - /* Clear the Tearing Effect Interrupt Flag */ - __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE); - - /* Tearing Effect Callback */ - HAL_DSI_TearingEffectCallback(hdsi); - } - } - - /* End of Refresh Interrupt management ***************************************/ - if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET) - { - if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET) - { - /* Clear the End of Refresh Interrupt Flag */ - __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER); - - /* End of Refresh Callback */ - HAL_DSI_EndOfRefreshCallback(hdsi); - } - } - - /* Error Interrupts management ***********************************************/ - if(hdsi->ErrorMsk != 0) - { - ErrorStatus0 = hdsi->Instance->ISR[0]; - ErrorStatus0 &= hdsi->Instance->IER[0]; - ErrorStatus1 = hdsi->Instance->ISR[1]; - ErrorStatus1 &= hdsi->Instance->IER[1]; - - if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET) - { - hdsi->ErrorCode |= HAL_DSI_ERROR_ACK; - } - - if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET) - { - hdsi->ErrorCode |= HAL_DSI_ERROR_PHY; - } - - if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET) - { - hdsi->ErrorCode |= HAL_DSI_ERROR_TX; - } - - if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET) - { - hdsi->ErrorCode |= HAL_DSI_ERROR_RX; - } - - if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET) - { - hdsi->ErrorCode |= HAL_DSI_ERROR_ECC; - } - - if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET) - { - hdsi->ErrorCode |= HAL_DSI_ERROR_CRC; - } - - if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET) - { - hdsi->ErrorCode |= HAL_DSI_ERROR_PSE; - } - - if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET) - { - hdsi->ErrorCode |= HAL_DSI_ERROR_EOT; - } - - if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET) - { - hdsi->ErrorCode |= HAL_DSI_ERROR_OVF; - } - - if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET) - { - hdsi->ErrorCode |= HAL_DSI_ERROR_GEN; - } - - /* Check only selected errors */ - if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE) - { - /* DSI error interrupt user callback */ - HAL_DSI_ErrorCallback(hdsi); - } - } -} - -/** - * @brief Tearing Effect DSI callback. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval None - */ -__weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdsi); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DSI_TearingEffectCallback could be implemented in the user file - */ -} - -/** - * @brief End of Refresh DSI callback. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval None - */ -__weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdsi); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DSI_EndOfRefreshCallback could be implemented in the user file - */ -} - -/** - * @brief Operation Error DSI callback. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval None - */ -__weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdsi); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DSI_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup DSI_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) - (+) - (+) - -@endverbatim - * @{ - */ - -/** - * @brief Configure the Generic interface read-back Virtual Channel ID. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param VirtualChannelID: Virtual channel ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Update the GVCID register */ - hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID; - hdsi->Instance->GVCIDR |= VirtualChannelID; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Select video mode and configure the corresponding parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains - * the DSI video mode configuration parameters - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check the parameters */ - assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding)); - assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode)); - assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable)); - assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable)); - assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable)); - assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable)); - assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable)); - assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable)); - assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable)); - assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable)); - assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity)); - assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity)); - assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity)); - /* Check the LooselyPacked variant only in 18-bit mode */ - if(VidCfg->ColorCoding == DSI_RGB666) - { - assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked)); - } - - /* Select video mode by resetting CMDM and DSIM bits */ - hdsi->Instance->MCR &= ~DSI_MCR_CMDM; - hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; - - /* Configure the video mode transmission type */ - hdsi->Instance->VMCR &= ~DSI_VMCR_VMT; - hdsi->Instance->VMCR |= VidCfg->Mode; - - /* Configure the video packet size */ - hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE; - hdsi->Instance->VPCR |= VidCfg->PacketSize; - - /* Set the chunks number to be transmitted through the DSI link */ - hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC; - hdsi->Instance->VCCR |= VidCfg->NumberOfChunks; - - /* Set the size of the null packet */ - hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE; - hdsi->Instance->VNPCR |= VidCfg->NullPacketSize; - - /* Select the virtual channel for the LTDC interface traffic */ - hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; - hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID; - - /* Configure the polarity of control signals */ - hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); - hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity); - - /* Select the color coding for the host */ - hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; - hdsi->Instance->LCOLCR |= VidCfg->ColorCoding; - - /* Select the color coding for the wrapper */ - hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; - hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1); - - /* Enable/disable the loosely packed variant to 18-bit configuration */ - if(VidCfg->ColorCoding == DSI_RGB666) - { - hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE; - hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked; - } - - /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */ - hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA; - hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive; - - /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */ - hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP; - hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch; - - /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */ - hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE; - hdsi->Instance->VLCR |= VidCfg->HorizontalLine; - - /* Set the Vertical Synchronization Active (VSA) */ - hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA; - hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive; - - /* Set the Vertical Back Porch (VBP)*/ - hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP; - hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch; - - /* Set the Vertical Front Porch (VFP)*/ - hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP; - hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch; - - /* Set the Vertical Active period*/ - hdsi->Instance->VVACR &= ~DSI_VVACR_VA; - hdsi->Instance->VVACR |= VidCfg->VerticalActive; - - /* Configure the command transmission mode */ - hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE; - hdsi->Instance->VMCR |= VidCfg->LPCommandEnable; - - /* Low power largest packet size */ - hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE; - hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16); - - /* Low power VACT largest packet size */ - hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE; - hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize; - - /* Enable LP transition in HFP period */ - hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE; - hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable; - - /* Enable LP transition in HBP period */ - hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE; - hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable; - - /* Enable LP transition in VACT period */ - hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE; - hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable; - - /* Enable LP transition in VFP period */ - hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE; - hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable; - - /* Enable LP transition in VBP period */ - hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE; - hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable; - - /* Enable LP transition in vertical sync period */ - hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE; - hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable; - - /* Enable the request for an acknowledge response at the end of a frame */ - hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE; - hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Select adapted command mode and configure the corresponding parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains - * the DSI command mode configuration parameters - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check the parameters */ - assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding)); - assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource)); - assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity)); - assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh)); - assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol)); - assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest)); - assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity)); - assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity)); - assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity)); - - /* Select command mode by setting CMDM and DSIM bits */ - hdsi->Instance->MCR |= DSI_MCR_CMDM; - hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; - hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM; - - /* Select the virtual channel for the LTDC interface traffic */ - hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; - hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID; - - /* Configure the polarity of control signals */ - hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); - hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity); - - /* Select the color coding for the host */ - hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; - hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding; - - /* Select the color coding for the wrapper */ - hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; - hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1); - - /* Configure the maximum allowed size for write memory command */ - hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE; - hdsi->Instance->LCCR |= CmdCfg->CommandSize; - - /* Configure the tearing effect source and polarity and select the refresh mode */ - hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL); - hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol); - - /* Configure the tearing effect acknowledge request */ - hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE; - hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest; - - /* Enable the Tearing Effect interrupt */ - __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE); - - /* Enable the End of Refresh interrupt */ - __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Configure command transmission mode: High-speed or Low-power - * and enable/disable acknowledge request after packet transmission - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains - * the DSI command transmission mode configuration parameters - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP)); - assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP)); - assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP)); - assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP)); - assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP)); - assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP)); - assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite)); - assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP)); - assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP)); - assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP)); - assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite)); - assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket)); - assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest)); - - /* Select High-speed or Low-power for command transmission */ - hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\ - DSI_CMCR_GSW1TX |\ - DSI_CMCR_GSW2TX |\ - DSI_CMCR_GSR0TX |\ - DSI_CMCR_GSR1TX |\ - DSI_CMCR_GSR2TX |\ - DSI_CMCR_GLWTX |\ - DSI_CMCR_DSW0TX |\ - DSI_CMCR_DSW1TX |\ - DSI_CMCR_DSR0TX |\ - DSI_CMCR_DLWTX |\ - DSI_CMCR_MRDPS); - hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP |\ - LPCmd->LPGenShortWriteOneP |\ - LPCmd->LPGenShortWriteTwoP |\ - LPCmd->LPGenShortReadNoP |\ - LPCmd->LPGenShortReadOneP |\ - LPCmd->LPGenShortReadTwoP |\ - LPCmd->LPGenLongWrite |\ - LPCmd->LPDcsShortWriteNoP |\ - LPCmd->LPDcsShortWriteOneP |\ - LPCmd->LPDcsShortReadNoP |\ - LPCmd->LPDcsLongWrite |\ - LPCmd->LPMaxReadPacket); - - /* Configure the acknowledge request after each packet transmission */ - hdsi->Instance->CMCR &= ~DSI_CMCR_ARE; - hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Configure the flow control parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param FlowControl: flow control feature(s) to be enabled. - * This parameter can be any combination of @ref DSI_FlowControl. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check the parameters */ - assert_param(IS_DSI_FLOW_CONTROL(FlowControl)); - - /* Set the DSI Host Protocol Configuration Register */ - hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL; - hdsi->Instance->PCR |= FlowControl; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Configure the DSI PHY timer parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param PhyTimers: DSI_PHY_TimerTypeDef structure that contains - * the DSI PHY timing parameters - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers) -{ - uint32_t maxTime; - /* Process locked */ - __HAL_LOCK(hdsi); - - maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime; - - /* Clock lane timer configuration */ - - /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two - High-Speed transmission. - To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed - to Low-Power and from Low-Power to High-Speed. - This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR). - But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME. - - Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME. - */ - hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME); - hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16)); - - /* Data lane timer configuration */ - hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME); - hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16) | ((PhyTimers->DataLaneHS2LPTime)<<24)); - - /* Configure the wait period to request HS transmission after a stop state */ - hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME; - hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Configure the DSI HOST timeout parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains - * the DSI host timeout parameters - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Set the timeout clock division factor */ - hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV; - hdsi->Instance->CCR = ((HostTimeouts->TimeoutCkdiv)<<8); - - /* High-speed transmission timeout */ - hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_HSTX_TOCNT; - hdsi->Instance->TCCR[0] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16); - - /* Low-power reception timeout */ - hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_LPRX_TOCNT; - hdsi->Instance->TCCR[0] |= HostTimeouts->LowPowerReceptionTimeout; - - /* High-speed read timeout */ - hdsi->Instance->TCCR[1] &= ~DSI_TCCR1_HSRD_TOCNT; - hdsi->Instance->TCCR[1] |= HostTimeouts->HighSpeedReadTimeout; - - /* Low-power read timeout */ - hdsi->Instance->TCCR[2] &= ~DSI_TCCR2_LPRD_TOCNT; - hdsi->Instance->TCCR[2] |= HostTimeouts->LowPowerReadTimeout; - - /* High-speed write timeout */ - hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_HSWR_TOCNT; - hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWriteTimeout; - - /* High-speed write presp mode */ - hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_PM; - hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWritePrespMode; - - /* Low-speed write timeout */ - hdsi->Instance->TCCR[4] &= ~DSI_TCCR4_LPWR_TOCNT; - hdsi->Instance->TCCR[4] |= HostTimeouts->LowPowerWriteTimeout; - - /* BTA timeout */ - hdsi->Instance->TCCR[5] &= ~DSI_TCCR5_BTA_TOCNT; - hdsi->Instance->TCCR[5] |= HostTimeouts->BTATimeout; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Start the DSI module - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Enable the DSI host */ - __HAL_DSI_ENABLE(hdsi); - - /* Enable the DSI wrapper */ - __HAL_DSI_WRAPPER_ENABLE(hdsi); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Stop the DSI module - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Disable the DSI host */ - __HAL_DSI_DISABLE(hdsi); - - /* Disable the DSI wrapper */ - __HAL_DSI_WRAPPER_DISABLE(hdsi); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Refresh the display in command mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Update the display */ - hdsi->Instance->WCR |= DSI_WCR_LTDCEN; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Controls the display color mode in Video mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param ColorMode: Color mode (full or 8-colors). - * This parameter can be any value of @ref DSI_Color_Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check the parameters */ - assert_param(IS_DSI_COLOR_MODE(ColorMode)); - - /* Update the display color mode */ - hdsi->Instance->WCR &= ~DSI_WCR_COLM; - hdsi->Instance->WCR |= ColorMode; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Control the display shutdown in Video mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param Shutdown: Shut-down (Display-ON or Display-OFF). - * This parameter can be any value of @ref DSI_ShutDown - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check the parameters */ - assert_param(IS_DSI_SHUT_DOWN(Shutdown)); - - /* Update the display Shutdown */ - hdsi->Instance->WCR &= ~DSI_WCR_SHTDN; - hdsi->Instance->WCR |= Shutdown; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief DCS or Generic short write command - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param ChannelID: Virtual channel ID. - * @param Mode: DSI short packet data type. - * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type. - * @param Param1: DSC command or first generic parameter. - * This parameter can be any value of @ref DSI_DCS_Command or a - * generic command code. - * @param Param2: DSC parameter or second generic parameter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, - uint32_t ChannelID, - uint32_t Mode, - uint32_t Param1, - uint32_t Param2) -{ - uint32_t tickstart = 0; - - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check the parameters */ - assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode)); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for Command FIFO Empty */ - while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - - /* Configure the packet to send a short DCS command with 0 or 1 parameter */ - DSI_ConfigPacketHeader(hdsi->Instance, - ChannelID, - Mode, - Param1, - Param2); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief DCS or Generic long write command - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param ChannelID: Virtual channel ID. - * @param Mode: DSI long packet data type. - * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type. - * @param NbParams: Number of parameters. - * @param Param1: DSC command or first generic parameter. - * This parameter can be any value of @ref DSI_DCS_Command or a - * generic command code - * @param ParametersTable: Pointer to parameter values table. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, - uint32_t ChannelID, - uint32_t Mode, - uint32_t NbParams, - uint32_t Param1, - uint8_t* ParametersTable) -{ - uint32_t uicounter = 0; - uint32_t tickstart = 0; - - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check the parameters */ - assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode)); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for Command FIFO Empty */ - while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - - /* Set the DCS code hexadecimal on payload byte 1, and the other parameters on the write FIFO command*/ - while(uicounter < NbParams) - { - if(uicounter == 0x00) - { - hdsi->Instance->GPDR=(Param1 | \ - ((uint32_t)(*(ParametersTable + uicounter)) << 8) | \ - ((uint32_t)(*(ParametersTable + uicounter+1))<<16) | \ - ((uint32_t)(*(ParametersTable + uicounter+2))<<24)); - uicounter += 3; - } - else - { - hdsi->Instance->GPDR=((uint32_t)(*(ParametersTable + uicounter)) | \ - ((uint32_t)(*(ParametersTable + uicounter+1)) << 8) | \ - ((uint32_t)(*(ParametersTable + uicounter+2)) << 16) | \ - ((uint32_t)(*(ParametersTable + uicounter+3)) << 24)); - uicounter+=4; - } - } - - /* Configure the packet to send a long DCS command */ - DSI_ConfigPacketHeader(hdsi->Instance, - ChannelID, - Mode, - ((NbParams+1)&0x00FF), - (((NbParams+1)&0xFF00)>>8)); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Read command (DCS or generic) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param ChannelNbr: Virtual channel ID - * @param Array: pointer to a buffer to store the payload of a read back operation. - * @param Size: Data size to be read (in byte). - * @param Mode: DSI read packet data type. - * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type. - * @param DCSCmd: DCS get/read command. - * @param ParametersTable: Pointer to parameter values table. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, - uint32_t ChannelNbr, - uint8_t* Array, - uint32_t Size, - uint32_t Mode, - uint32_t DCSCmd, - uint8_t* ParametersTable) -{ - uint32_t tickstart = 0; - - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check the parameters */ - assert_param(IS_DSI_READ_PACKET_TYPE(Mode)); - - if(Size > 2) - { - /* set max return packet size */ - HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((Size)&0xFF), (((Size)>>8)&0xFF)); - } - - /* Configure the packet to read command */ - if (Mode == DSI_DCS_SHORT_PKT_READ) - { - DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0); - } - else if (Mode == DSI_GEN_SHORT_PKT_READ_P0) - { - DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0, 0); - } - else if (Mode == DSI_GEN_SHORT_PKT_READ_P1) - { - DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], 0); - } - else if (Mode == DSI_GEN_SHORT_PKT_READ_P2) - { - DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], ParametersTable[1]); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_ERROR; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check that the payload read FIFO is not empty */ - while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - - /* Get the first byte */ - *((uint32_t *)Array) = (hdsi->Instance->GPDR); - if (Size > 4) - { - Size -= 4; - Array += 4; - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Get the remaining bytes if any */ - while(((int)(Size)) > 0) - { - if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0) - { - *((uint32_t *)Array) = (hdsi->Instance->GPDR); - Size -= 4; - Array += 4; - } - - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running - * (only data lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) -{ - uint32_t tickstart = 0; - - /* Process locked */ - __HAL_LOCK(hdsi); - - /* ULPS Request on Data Lanes */ - hdsi->Instance->PUCR |= DSI_PUCR_URDL; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until the D-PHY active lanes enter into ULPM */ - if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) - { - while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - } - else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) - { - while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running - * (only data lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) -{ - uint32_t tickstart = 0; - - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Exit ULPS on Data Lanes */ - hdsi->Instance->PUCR |= DSI_PUCR_UEDL; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until all active lanes exit ULPM */ - if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) - { - while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - } - else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) - { - while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - } - - /* De-assert the ULPM requests and the ULPM exit bits */ - hdsi->Instance->PUCR = 0; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off - * (both data and clock lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) -{ - uint32_t tickstart = 0; - - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Clock lane configuration: no more HS request */ - hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC; - - /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */ - __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR); - - /* ULPS Request on Clock and Data Lanes */ - hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until all active lanes exit ULPM */ - if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) - { - while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - } - else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) - { - while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - } - - /* Turn off the DSI PLL */ - __HAL_DSI_PLL_DISABLE(hdsi); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off - * (both data and clock lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) -{ - uint32_t tickstart = 0; - - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Turn on the DSI PLL */ - __HAL_DSI_PLL_ENABLE(hdsi); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for the lock of the PLL */ - while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - - /* Exit ULPS on Clock and Data Lanes */ - hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until all active lanes exit ULPM */ - if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) - { - while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC)) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - } - else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) - { - while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - } - - /* De-assert the ULPM requests and the ULPM exit bits */ - hdsi->Instance->PUCR = 0; - - /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */ - __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY); - - /* Restore clock lane configuration to HS */ - hdsi->Instance->CLCR |= DSI_CLCR_DPCC; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Start test pattern generation - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param Mode: Pattern generator mode - * This parameter can be one of the following values: - * 0 : Color bars (horizontal or vertical) - * 1 : BER pattern (vertical only) - * @param Orientation: Pattern generator orientation - * This parameter can be one of the following values: - * 0 : Vertical color bars - * 1 : Horizontal color bars - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Configure pattern generator mode and orientation */ - hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO); - hdsi->Instance->VMCR |= ((Mode<<20) | (Orientation<<24)); - - /* Enable pattern generator by setting PGE bit */ - hdsi->Instance->VMCR |= DSI_VMCR_PGE; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Stop test pattern generation - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Disable pattern generator by clearing PGE bit */ - hdsi->Instance->VMCR &= ~DSI_VMCR_PGE; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Set Slew-Rate And Delay Tuning - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param CommDelay: Communication delay to be adjusted. - * This parameter can be any value of @ref DSI_Communication_Delay - * @param Lane: select between clock or data lanes. - * This parameter can be any value of @ref DSI_Lane_Group - * @param Value: Custom value of the slew-rate or delay - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check function parameters */ - assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay)); - assert_param(IS_DSI_LANE_GROUP(Lane)); - - switch(CommDelay) - { - case DSI_SLEW_RATE_HSTX: - if(Lane == DSI_CLOCK_LANE) - { - /* High-Speed Transmission Slew Rate Control on Clock Lane */ - hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCCL; - hdsi->Instance->WPCR[1] |= Value<<16; - } - else if(Lane == DSI_DATA_LANES) - { - /* High-Speed Transmission Slew Rate Control on Data Lanes */ - hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCDL; - hdsi->Instance->WPCR[1] |= Value<<18; - } - break; - case DSI_SLEW_RATE_LPTX: - if(Lane == DSI_CLOCK_LANE) - { - /* Low-Power transmission Slew Rate Compensation on Clock Lane */ - hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCCL; - hdsi->Instance->WPCR[1] |= Value<<6; - } - else if(Lane == DSI_DATA_LANES) - { - /* Low-Power transmission Slew Rate Compensation on Data Lanes */ - hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCDL; - hdsi->Instance->WPCR[1] |= Value<<8; - } - break; - case DSI_HS_DELAY: - if(Lane == DSI_CLOCK_LANE) - { - /* High-Speed Transmission Delay on Clock Lane */ - hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDCL; - hdsi->Instance->WPCR[1] |= Value; - } - else if(Lane == DSI_DATA_LANES) - { - /* High-Speed Transmission Delay on Data Lanes */ - hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDDL; - hdsi->Instance->WPCR[1] |= Value<<2; - } - break; - default: - break; - } - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Low-Power Reception Filter Tuning - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param Frequency: cutoff frequency of low-pass filter at the input of LPRX - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Low-Power RX low-pass Filtering Tuning */ - hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPRXFT; - hdsi->Instance->WPCR[1] |= Frequency<<25; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Activate an additional current path on all lanes to meet the SDDTx parameter - * defined in the MIPI D-PHY specification - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param State: ENABLE or DISABLE - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check function parameters */ - assert_param(IS_FUNCTIONAL_STATE(State)); - - /* Activate/Disactivate additional current path on all lanes */ - hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_SDDC; - hdsi->Instance->WPCR[1] |= ((uint32_t)State << 12); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Custom lane pins configuration - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param CustomLane: Function to be applyed on selected lane. - * This parameter can be any value of @ref DSI_CustomLane - * @param Lane: select between clock or data lane 0 or data lane 1. - * This parameter can be any value of @ref DSI_Lane_Select - * @param State: ENABLE or DISABLE - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check function parameters */ - assert_param(IS_DSI_CUSTOM_LANE(CustomLane)); - assert_param(IS_DSI_LANE(Lane)); - assert_param(IS_FUNCTIONAL_STATE(State)); - - switch(CustomLane) - { - case DSI_SWAP_LANE_PINS: - if(Lane == DSI_CLOCK_LANE) - { - /* Swap pins on clock lane */ - hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWCL; - hdsi->Instance->WPCR[0] |= ((uint32_t)State << 6); - } - else if(Lane == DSI_DATA_LANE0) - { - /* Swap pins on data lane 0 */ - hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL0; - hdsi->Instance->WPCR[0] |= ((uint32_t)State << 7); - } - else if(Lane == DSI_DATA_LANE1) - { - /* Swap pins on data lane 1 */ - hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL1; - hdsi->Instance->WPCR[0] |= ((uint32_t)State << 8); - } - break; - case DSI_INVERT_HS_SIGNAL: - if(Lane == DSI_CLOCK_LANE) - { - /* Invert HS signal on clock lane */ - hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSICL; - hdsi->Instance->WPCR[0] |= ((uint32_t)State << 9); - } - else if(Lane == DSI_DATA_LANE0) - { - /* Invert HS signal on data lane 0 */ - hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL0; - hdsi->Instance->WPCR[0] |= ((uint32_t)State << 10); - } - else if(Lane == DSI_DATA_LANE1) - { - /* Invert HS signal on data lane 1 */ - hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL1; - hdsi->Instance->WPCR[0] |= ((uint32_t)State << 11); - } - break; - default: - break; - } - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Set custom timing for the PHY - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param Timing: PHY timing to be adjusted. - * This parameter can be any value of @ref DSI_PHY_Timing - * @param State: ENABLE or DISABLE - * @param Value: Custom value of the timing - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check function parameters */ - assert_param(IS_DSI_PHY_TIMING(Timing)); - assert_param(IS_FUNCTIONAL_STATE(State)); - - switch(Timing) - { - case DSI_TCLK_POST: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPOSTEN; - hdsi->Instance->WPCR[0] |= ((uint32_t)State << 27); - - if(State) - { - /* Set custom value */ - hdsi->Instance->WPCR[4] &= ~DSI_WPCR4_TCLKPOST; - hdsi->Instance->WPCR[4] |= Value & DSI_WPCR4_TCLKPOST; - } - - break; - case DSI_TLPX_CLK: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXCEN; - hdsi->Instance->WPCR[0] |= ((uint32_t)State << 26); - - if(State) - { - /* Set custom value */ - hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXC; - hdsi->Instance->WPCR[3] |= (Value << 24) & DSI_WPCR3_TLPXC; - } - - break; - case DSI_THS_EXIT: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSEXITEN; - hdsi->Instance->WPCR[0] |= ((uint32_t)State << 25); - - if(State) - { - /* Set custom value */ - hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSEXIT; - hdsi->Instance->WPCR[3] |= (Value << 16) & DSI_WPCR3_THSEXIT; - } - - break; - case DSI_TLPX_DATA: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXDEN; - hdsi->Instance->WPCR[0] |= ((uint32_t)State << 24); - - if(State) - { - /* Set custom value */ - hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXD; - hdsi->Instance->WPCR[3] |= (Value << 8) & DSI_WPCR3_TLPXD; - } - - break; - case DSI_THS_ZERO: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSZEROEN; - hdsi->Instance->WPCR[0] |= ((uint32_t)State << 23); - - if(State) - { - /* Set custom value */ - hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSZERO; - hdsi->Instance->WPCR[3] |= Value & DSI_WPCR3_THSZERO; - } - - break; - case DSI_THS_TRAIL: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSTRAILEN; - hdsi->Instance->WPCR[0] |= ((uint32_t)State << 22); - - if(State) - { - /* Set custom value */ - hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSTRAIL; - hdsi->Instance->WPCR[2] |= (Value << 24) & DSI_WPCR2_THSTRAIL; - } - - break; - case DSI_THS_PREPARE: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSPREPEN; - hdsi->Instance->WPCR[0] |= ((uint32_t)State << 21); - - if(State) - { - /* Set custom value */ - hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSPREP; - hdsi->Instance->WPCR[2] |= (Value << 16) & DSI_WPCR2_THSPREP; - } - - break; - case DSI_TCLK_ZERO: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKZEROEN; - hdsi->Instance->WPCR[0] |= ((uint32_t)State << 20); - - if(State) - { - /* Set custom value */ - hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKZERO; - hdsi->Instance->WPCR[2] |= (Value << 8) & DSI_WPCR2_TCLKZERO; - } - - break; - case DSI_TCLK_PREPARE: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPREPEN; - hdsi->Instance->WPCR[0] |= ((uint32_t)State << 19); - - if(State) - { - /* Set custom value */ - hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKPREP; - hdsi->Instance->WPCR[2] |= Value & DSI_WPCR2_TCLKPREP; - } - - break; - default: - break; - } - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Force the Clock/Data Lane in TX Stop Mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param Lane: select between clock or data lanes. - * This parameter can be any value of @ref DSI_Lane_Group - * @param State: ENABLE or DISABLE - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check function parameters */ - assert_param(IS_DSI_LANE_GROUP(Lane)); - assert_param(IS_FUNCTIONAL_STATE(State)); - - if(Lane == DSI_CLOCK_LANE) - { - /* Force/Unforce the Clock Lane in TX Stop Mode */ - hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMCL; - hdsi->Instance->WPCR[0] |= ((uint32_t)State << 12); - } - else if(Lane == DSI_DATA_LANES) - { - /* Force/Unforce the Data Lanes in TX Stop Mode */ - hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMDL; - hdsi->Instance->WPCR[0] |= ((uint32_t)State << 13); - } - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Forces LP Receiver in Low-Power Mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param State: ENABLE or DISABLE - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check function parameters */ - assert_param(IS_FUNCTIONAL_STATE(State)); - - /* Force/Unforce LP Receiver in Low-Power Mode */ - hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_FLPRXLPM; - hdsi->Instance->WPCR[1] |= ((uint32_t)State << 22); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Force Data Lanes in RX Mode after a BTA - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param State: ENABLE or DISABLE - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check function parameters */ - assert_param(IS_FUNCTIONAL_STATE(State)); - - /* Force Data Lanes in RX Mode */ - hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TDDL; - hdsi->Instance->WPCR[0] |= ((uint32_t)State << 16); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Enable a pull-down on the lanes to prevent from floating states when unused - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param State: ENABLE or DISABLE - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check function parameters */ - assert_param(IS_FUNCTIONAL_STATE(State)); - - /* Enable/Disable pull-down on lanes */ - hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_PDEN; - hdsi->Instance->WPCR[0] |= ((uint32_t)State << 18); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Switch off the contention detection on data lanes - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param State: ENABLE or DISABLE - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check function parameters */ - assert_param(IS_FUNCTIONAL_STATE(State)); - - /* Contention Detection on Data Lanes OFF */ - hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_CDOFFDL; - hdsi->Instance->WPCR[0] |= ((uint32_t)State << 14); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup DSI_Group4 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the DSI state. - (+) Get error code. - -@endverbatim - * @{ - */ - -/** - * @brief Return the DSI state - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL state - */ -HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi) -{ - return hdsi->State; -} - -/** - * @} - */ - -/** - * @} - */ -#endif /*STM32F769xx | STM32F779xx */ -#endif /* HAL_DSI_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c deleted file mode 100644 index 11ebd62..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c +++ /dev/null @@ -1,2043 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_eth.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief ETH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Ethernet (ETH) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#)Declare a ETH_HandleTypeDef handle structure, for example: - ETH_HandleTypeDef heth; - - (#)Fill parameters of Init structure in heth handle - - (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) - - (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API: - (##) Enable the Ethernet interface clock using - (+++) __HAL_RCC_ETHMAC_CLK_ENABLE(); - (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE(); - (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE(); - - (##) Initialize the related GPIO clocks - (##) Configure Ethernet pin-out - (##) Configure Ethernet NVIC interrupt (IT mode) - - (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers: - (##) HAL_ETH_DMATxDescListInit(); for Transmission process - (##) HAL_ETH_DMARxDescListInit(); for Reception process - - (#)Enable MAC and DMA transmission and reception: - (##) HAL_ETH_Start(); - - (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer - the frame to MAC TX FIFO: - (##) HAL_ETH_TransmitFrame(); - - (#)Poll for a received frame in ETH RX DMA Descriptors and get received - frame parameters - (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop) - - (#) Get a received frame when an ETH RX interrupt occurs: - (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only) - - (#) Communicate with external PHY device: - (##) Read a specific register from the PHY - HAL_ETH_ReadPHYRegister(); - (##) Write data to a specific RHY register: - HAL_ETH_WritePHYRegister(); - - (#) Configure the Ethernet MAC after ETH peripheral initialization - HAL_ETH_ConfigMAC(); all MAC parameters should be filled. - - (#) Configure the Ethernet DMA after ETH peripheral initialization - HAL_ETH_ConfigDMA(); all DMA parameters should be filled. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup ETH ETH - * @brief ETH HAL module driver - * @{ - */ - -#ifdef HAL_ETH_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup ETH_Private_Constants ETH Private Constants - * @{ - */ -#define ETH_TIMEOUT_SWRESET ((uint32_t)500) -#define ETH_TIMEOUT_LINKED_STATE ((uint32_t)5000) -#define ETH_TIMEOUT_AUTONEGO_COMPLETED ((uint32_t)5000) - -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup ETH_Private_Functions ETH Private Functions - * @{ - */ -static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err); -static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr); -static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth); -static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth); -static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth); -static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth); -static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth); -static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth); -static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth); -static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth); -static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth); - -/** - * @} - */ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup ETH_Exported_Functions ETH Exported Functions - * @{ - */ - -/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the Ethernet peripheral - (+) De-initialize the Ethernet peripheral - - @endverbatim - * @{ - */ - -/** - * @brief Initializes the Ethernet MAC and DMA according to default - * parameters. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) -{ - uint32_t tempreg = 0, phyreg = 0; - uint32_t hclk = 60000000; - uint32_t tickstart = 0; - uint32_t err = ETH_SUCCESS; - - /* Check the ETH peripheral state */ - if(heth == NULL) - { - return HAL_ERROR; - } - - /* Check parameters */ - assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation)); - assert_param(IS_ETH_RX_MODE(heth->Init.RxMode)); - assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode)); - assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface)); - - if(heth->State == HAL_ETH_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - heth->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK, NVIC. */ - HAL_ETH_MspInit(heth); - } - - /* Enable SYSCFG Clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - /* Select MII or RMII Mode*/ - SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL); - SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface; - - /* Ethernet Software reset */ - /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ - /* After reset all the registers holds their respective reset values */ - (heth->Instance)->DMABMR |= ETH_DMABMR_SR; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for software reset */ - while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET) - { - heth->State= HAL_ETH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are - not available, please check your external PHY or the IO configuration */ - - return HAL_TIMEOUT; - } - } - - /*-------------------------------- MAC Initialization ----------------------*/ - /* Get the ETHERNET MACMIIAR value */ - tempreg = (heth->Instance)->MACMIIAR; - /* Clear CSR Clock Range CR[2:0] bits */ - tempreg &= ETH_MACMIIAR_CR_MASK; - - /* Get hclk frequency value */ - hclk = HAL_RCC_GetHCLKFreq(); - - /* Set CR bits depending on hclk value */ - if((hclk >= 20000000)&&(hclk < 35000000)) - { - /* CSR Clock Range between 20-35 MHz */ - tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div16; - } - else if((hclk >= 35000000)&&(hclk < 60000000)) - { - /* CSR Clock Range between 35-60 MHz */ - tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; - } - else if((hclk >= 60000000)&&(hclk < 100000000)) - { - /* CSR Clock Range between 60-100 MHz */ - tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; - } - else if((hclk >= 100000000)&&(hclk < 150000000)) - { - /* CSR Clock Range between 100-150 MHz */ - tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div62; - } - else /* ((hclk >= 150000000)&&(hclk <= 216000000)) */ - { - /* CSR Clock Range between 150-216 MHz */ - tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102; - } - - /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ - (heth->Instance)->MACMIIAR = (uint32_t)tempreg; - - /*-------------------- PHY initialization and configuration ----------------*/ - /* Put the PHY in reset mode */ - if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set the ETH peripheral state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return HAL_ERROR */ - return HAL_ERROR; - } - - /* Delay to assure PHY reset */ - HAL_Delay(PHY_RESET_DELAY); - - if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* We wait for linked status */ - do - { - HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); - - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_TIMEOUT; - } - } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS)); - - - /* Enable Auto-Negotiation */ - if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set the ETH peripheral state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return HAL_ERROR */ - return HAL_ERROR; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until the auto-negotiation will be completed */ - do - { - HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); - - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_TIMEOUT; - } - - } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE)); - - /* Read the result of the auto-negotiation */ - if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set the ETH peripheral state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return HAL_ERROR */ - return HAL_ERROR; - } - - /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */ - if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET) - { - /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */ - (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; - } - else - { - /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */ - (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX; - } - /* Configure the MAC with the speed fixed by the auto-negotiation process */ - if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS) - { - /* Set Ethernet speed to 10M following the auto-negotiation */ - (heth->Init).Speed = ETH_SPEED_10M; - } - else - { - /* Set Ethernet speed to 100M following the auto-negotiation */ - (heth->Init).Speed = ETH_SPEED_100M; - } - } - else /* AutoNegotiation Disable */ - { - /* Check parameters */ - assert_param(IS_ETH_SPEED(heth->Init.Speed)); - assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); - - /* Set MAC Speed and Duplex Mode */ - if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) | - (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set the ETH peripheral state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return HAL_ERROR */ - return HAL_ERROR; - } - - /* Delay to assure PHY configuration */ - HAL_Delay(PHY_CONFIG_DELAY); - } - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set ETH HAL State to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief De-Initializes the ETH peripheral. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) -{ - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ - HAL_ETH_MspDeInit(heth); - - /* Set ETH HAL state to Disabled */ - heth->State= HAL_ETH_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the DMA Tx descriptors in chain mode. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param DMATxDescTab: Pointer to the first Tx desc list - * @param TxBuff: Pointer to the first TxBuffer list - * @param TxBuffCount: Number of the used Tx desc in the list - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount) -{ - uint32_t i = 0; - ETH_DMADescTypeDef *dmatxdesc; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ - heth->TxDesc = DMATxDescTab; - - /* Fill each DMATxDesc descriptor with the right values */ - for(i=0; i < TxBuffCount; i++) - { - /* Get the pointer on the ith member of the Tx Desc list */ - dmatxdesc = DMATxDescTab + i; - - /* Set Second Address Chained bit */ - dmatxdesc->Status = ETH_DMATXDESC_TCH; - - /* Set Buffer1 address pointer */ - dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]); - - if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) - { - /* Set the DMA Tx descriptors checksum insertion */ - dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL; - } - - /* Initialize the next descriptor with the Next Descriptor Polling Enable */ - if(i < (TxBuffCount-1)) - { - /* Set next descriptor address register with next descriptor base address */ - dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1); - } - else - { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; - } - } - - /* Set Transmit Descriptor List Address Register */ - (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab; - - /* Set ETH HAL State to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the DMA Rx descriptors in chain mode. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param DMARxDescTab: Pointer to the first Rx desc list - * @param RxBuff: Pointer to the first RxBuffer list - * @param RxBuffCount: Number of the used Rx desc in the list - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) -{ - uint32_t i = 0; - ETH_DMADescTypeDef *DMARxDesc; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */ - heth->RxDesc = DMARxDescTab; - - /* Fill each DMARxDesc descriptor with the right values */ - for(i=0; i < RxBuffCount; i++) - { - /* Get the pointer on the ith member of the Rx Desc list */ - DMARxDesc = DMARxDescTab+i; - - /* Set Own bit of the Rx descriptor Status */ - DMARxDesc->Status = ETH_DMARXDESC_OWN; - - /* Set Buffer1 size and Second Address Chained bit */ - DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE; - - /* Set Buffer1 address pointer */ - DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]); - - if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE) - { - /* Enable Ethernet DMA Rx Descriptor interrupt */ - DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC; - } - - /* Initialize the next descriptor with the Next Descriptor Polling Enable */ - if(i < (RxBuffCount-1)) - { - /* Set next descriptor address register with next descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); - } - else - { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); - } - } - - /* Set Receive Descriptor List Address Register */ - (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab; - - /* Set ETH HAL State to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the ETH MSP. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes ETH MSP. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup ETH_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * - @verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Transmit a frame - HAL_ETH_TransmitFrame(); - (+) Receive a frame - HAL_ETH_GetReceivedFrame(); - HAL_ETH_GetReceivedFrame_IT(); - (+) Read from an External PHY register - HAL_ETH_ReadPHYRegister(); - (+) Write to an External PHY register - HAL_ETH_WritePHYRegister(); - - @endverbatim - - * @{ - */ - -/** - * @brief Sends an Ethernet frame. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param FrameLength: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength) -{ - uint32_t bufcount = 0, size = 0, i = 0; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - if (FrameLength == 0) - { - /* Set ETH HAL state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_ERROR; - } - - /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ - if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET) - { - /* OWN bit set */ - heth->State = HAL_ETH_STATE_BUSY_TX; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_ERROR; - } - - /* Get the number of needed Tx buffers for the current frame */ - if (FrameLength > ETH_TX_BUF_SIZE) - { - bufcount = FrameLength/ETH_TX_BUF_SIZE; - if (FrameLength % ETH_TX_BUF_SIZE) - { - bufcount++; - } - } - else - { - bufcount = 1; - } - if (bufcount == 1) - { - /* Set LAST and FIRST segment */ - heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS; - /* Set frame size */ - heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1); - /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ - heth->TxDesc->Status |= ETH_DMATXDESC_OWN; - /* Point to next descriptor */ - heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr); - } - else - { - for (i=0; i< bufcount; i++) - { - /* Clear FIRST and LAST segment bits */ - heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS); - - if (i == 0) - { - /* Setting the first segment bit */ - heth->TxDesc->Status |= ETH_DMATXDESC_FS; - } - - /* Program size */ - heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1); - - if (i == (bufcount-1)) - { - /* Setting the last segment bit */ - heth->TxDesc->Status |= ETH_DMATXDESC_LS; - size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE; - heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1); - } - - /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ - heth->TxDesc->Status |= ETH_DMATXDESC_OWN; - /* point to next descriptor */ - heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr); - } - } - - /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ - if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) - { - /* Clear TBUS ETHERNET DMA flag */ - (heth->Instance)->DMASR = ETH_DMASR_TBUS; - /* Resume DMA transmission*/ - (heth->Instance)->DMATPDR = 0; - } - - /* Set ETH HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Checks for received frames. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) -{ - uint32_t framelength = 0; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Check the ETH state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Check if segment is not owned by DMA */ - /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */ - if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET)) - { - /* Check if last segment */ - if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) - { - /* increment segment count */ - (heth->RxFrameInfos).SegCount++; - - /* Check if last segment is first segment: one segment contains the frame */ - if ((heth->RxFrameInfos).SegCount == 1) - { - (heth->RxFrameInfos).FSRxDesc =heth->RxDesc; - } - - heth->RxFrameInfos.LSRxDesc = heth->RxDesc; - - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4; - heth->RxFrameInfos.length = framelength; - - /* Get the address of the buffer start address */ - heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr; - /* point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr); - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; - } - /* Check if first segment */ - else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) - { - (heth->RxFrameInfos).FSRxDesc = heth->RxDesc; - (heth->RxFrameInfos).LSRxDesc = NULL; - (heth->RxFrameInfos).SegCount = 1; - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - } - /* Check if intermediate segment */ - else - { - (heth->RxFrameInfos).SegCount++; - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - } - } - - /* Set ETH HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_ERROR; -} - -/** - * @brief Gets the Received frame in interrupt mode. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) -{ - uint32_t descriptorscancounter = 0; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set ETH HAL State to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Scan descriptors owned by CPU */ - while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB)) - { - /* Just for security */ - descriptorscancounter++; - - /* Check if first segment in frame */ - /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */ - if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS) - { - heth->RxFrameInfos.FSRxDesc = heth->RxDesc; - heth->RxFrameInfos.SegCount = 1; - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - } - /* Check if intermediate segment */ - /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */ - else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET) - { - /* Increment segment count */ - (heth->RxFrameInfos.SegCount)++; - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr); - } - /* Should be last segment */ - else - { - /* Last segment */ - heth->RxFrameInfos.LSRxDesc = heth->RxDesc; - - /* Increment segment count */ - (heth->RxFrameInfos.SegCount)++; - - /* Check if last segment is first segment: one segment contains the frame */ - if ((heth->RxFrameInfos.SegCount) == 1) - { - heth->RxFrameInfos.FSRxDesc = heth->RxDesc; - } - - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4; - - /* Get the address of the buffer start address */ - heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr; - - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; - } - } - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_ERROR; -} - -/** - * @brief This function handles ETH interrupt request. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) -{ - /* Frame received */ - if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R)) - { - /* Receive complete callback */ - HAL_ETH_RxCpltCallback(heth); - - /* Clear the Eth DMA Rx IT pending bits */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R); - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - } - /* Frame transmitted */ - else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T)) - { - /* Transfer complete callback */ - HAL_ETH_TxCpltCallback(heth); - - /* Clear the Eth DMA Tx IT pending bits */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T); - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - } - - /* Clear the interrupt flags */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS); - - /* ETH DMA Error */ - if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS)) - { - /* Ethernet Error callback */ - HAL_ETH_ErrorCallback(heth); - - /* Clear the interrupt flags */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS); - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - } -} - -/** - * @brief Tx Transfer completed callbacks. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callbacks. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Ethernet transfer error callbacks - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Reads a PHY register - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * PHY_BCR: Transceiver Basic Control Register, - * PHY_BSR: Transceiver Basic Status Register. - * More PHY register could be read depending on the used PHY - * @param RegValue: PHY register value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue) -{ - uint32_t tmpreg = 0; - uint32_t tickstart = 0; - - /* Check parameters */ - assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); - - /* Check the ETH peripheral state */ - if(heth->State == HAL_ETH_STATE_BUSY_RD) - { - return HAL_BUSY; - } - /* Set ETH HAL State to BUSY_RD */ - heth->State = HAL_ETH_STATE_BUSY_RD; - - /* Get the ETHERNET MACMIIAR value */ - tmpreg = heth->Instance->MACMIIAR; - - /* Keep only the CSR Clock Range CR[2:0] bits value */ - tmpreg &= ~ETH_MACMIIAR_CR_MASK; - - /* Prepare the MII address register value */ - tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ - tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ - tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */ - tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - - /* Write the result value into the MII Address register */ - heth->Instance->MACMIIAR = tmpreg; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check for the Busy flag */ - while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > PHY_READ_TO) - { - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_TIMEOUT; - } - - tmpreg = heth->Instance->MACMIIAR; - } - - /* Get MACMIIDR value */ - *RegValue = (uint16_t)(heth->Instance->MACMIIDR); - - /* Set ETH HAL State to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Writes to a PHY register. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * PHY_BCR: Transceiver Control Register. - * More PHY register could be written depending on the used PHY - * @param RegValue: the value to write - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue) -{ - uint32_t tmpreg = 0; - uint32_t tickstart = 0; - - /* Check parameters */ - assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); - - /* Check the ETH peripheral state */ - if(heth->State == HAL_ETH_STATE_BUSY_WR) - { - return HAL_BUSY; - } - /* Set ETH HAL State to BUSY_WR */ - heth->State = HAL_ETH_STATE_BUSY_WR; - - /* Get the ETHERNET MACMIIAR value */ - tmpreg = heth->Instance->MACMIIAR; - - /* Keep only the CSR Clock Range CR[2:0] bits value */ - tmpreg &= ~ETH_MACMIIAR_CR_MASK; - - /* Prepare the MII register address value */ - tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ - tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ - tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */ - tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - - /* Give the value to the MII data register */ - heth->Instance->MACMIIDR = (uint16_t)RegValue; - - /* Write the result value into the MII Address register */ - heth->Instance->MACMIIAR = tmpreg; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check for the Busy flag */ - while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO) - { - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_TIMEOUT; - } - - tmpreg = heth->Instance->MACMIIAR; - } - - /* Set ETH HAL State to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Enable MAC and DMA transmission and reception. - HAL_ETH_Start(); - (+) Disable MAC and DMA transmission and reception. - HAL_ETH_Stop(); - (+) Set the MAC configuration in runtime mode - HAL_ETH_ConfigMAC(); - (+) Set the DMA configuration in runtime mode - HAL_ETH_ConfigDMA(); - -@endverbatim - * @{ - */ - - /** - * @brief Enables Ethernet MAC and DMA reception/transmission - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) -{ - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Enable transmit state machine of the MAC for transmission on the MII */ - ETH_MACTransmissionEnable(heth); - - /* Enable receive state machine of the MAC for reception from the MII */ - ETH_MACReceptionEnable(heth); - - /* Flush Transmit FIFO */ - ETH_FlushTransmitFIFO(heth); - - /* Start DMA transmission */ - ETH_DMATransmissionEnable(heth); - - /* Start DMA reception */ - ETH_DMAReceptionEnable(heth); - - /* Set the ETH state to READY*/ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop Ethernet MAC and DMA reception/transmission - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) -{ - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Stop DMA transmission */ - ETH_DMATransmissionDisable(heth); - - /* Stop DMA reception */ - ETH_DMAReceptionDisable(heth); - - /* Disable receive state machine of the MAC for reception from the MII */ - ETH_MACReceptionDisable(heth); - - /* Flush Transmit FIFO */ - ETH_FlushTransmitFIFO(heth); - - /* Disable transmit state machine of the MAC for transmission on the MII */ - ETH_MACTransmissionDisable(heth); - - /* Set the ETH state*/ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Set ETH MAC Configuration. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param macconf: MAC Configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf) -{ - uint32_t tmpreg = 0; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State= HAL_ETH_STATE_BUSY; - - assert_param(IS_ETH_SPEED(heth->Init.Speed)); - assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); - - if (macconf != NULL) - { - /* Check the parameters */ - assert_param(IS_ETH_WATCHDOG(macconf->Watchdog)); - assert_param(IS_ETH_JABBER(macconf->Jabber)); - assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap)); - assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense)); - assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn)); - assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode)); - assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload)); - assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission)); - assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip)); - assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit)); - assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck)); - assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll)); - assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter)); - assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames)); - assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception)); - assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter)); - assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode)); - assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter)); - assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter)); - assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime)); - assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause)); - assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold)); - assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect)); - assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl)); - assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl)); - assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison)); - assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier)); - - /*------------------------ ETHERNET MACCR Configuration --------------------*/ - /* Get the ETHERNET MACCR value */ - tmpreg = (heth->Instance)->MACCR; - /* Clear WD, PCE, PS, TE and RE bits */ - tmpreg &= ETH_MACCR_CLEAR_MASK; - - tmpreg |= (uint32_t)(macconf->Watchdog | - macconf->Jabber | - macconf->InterFrameGap | - macconf->CarrierSense | - (heth->Init).Speed | - macconf->ReceiveOwn | - macconf->LoopbackMode | - (heth->Init).DuplexMode | - macconf->ChecksumOffload | - macconf->RetryTransmission | - macconf->AutomaticPadCRCStrip | - macconf->BackOffLimit | - macconf->DeferralCheck); - - /* Write to ETHERNET MACCR */ - (heth->Instance)->MACCR = (uint32_t)tmpreg; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; - - /*----------------------- ETHERNET MACFFR Configuration --------------------*/ - /* Write to ETHERNET MACFFR */ - (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll | - macconf->SourceAddrFilter | - macconf->PassControlFrames | - macconf->BroadcastFramesReception | - macconf->DestinationAddrFilter | - macconf->PromiscuousMode | - macconf->MulticastFramesFilter | - macconf->UnicastFramesFilter); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACFFR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFFR = tmpreg; - - /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ - /* Write to ETHERNET MACHTHR */ - (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh; - - /* Write to ETHERNET MACHTLR */ - (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow; - /*----------------------- ETHERNET MACFCR Configuration --------------------*/ - - /* Get the ETHERNET MACFCR value */ - tmpreg = (heth->Instance)->MACFCR; - /* Clear xx bits */ - tmpreg &= ETH_MACFCR_CLEAR_MASK; - - tmpreg |= (uint32_t)((macconf->PauseTime << 16) | - macconf->ZeroQuantaPause | - macconf->PauseLowThreshold | - macconf->UnicastPauseFrameDetect | - macconf->ReceiveFlowControl | - macconf->TransmitFlowControl); - - /* Write to ETHERNET MACFCR */ - (heth->Instance)->MACFCR = (uint32_t)tmpreg; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACFCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFCR = tmpreg; - - /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ - (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison | - macconf->VLANTagIdentifier); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACVLANTR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACVLANTR = tmpreg; - } - else /* macconf == NULL : here we just configure Speed and Duplex mode */ - { - /*------------------------ ETHERNET MACCR Configuration --------------------*/ - /* Get the ETHERNET MACCR value */ - tmpreg = (heth->Instance)->MACCR; - - /* Clear FES and DM bits */ - tmpreg &= ~((uint32_t)0x00004800); - - tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode); - - /* Write to ETHERNET MACCR */ - (heth->Instance)->MACCR = (uint32_t)tmpreg; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; - } - - /* Set the ETH state to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Sets ETH DMA Configuration. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param dmaconf: DMA Configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf) -{ - uint32_t tmpreg = 0; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State= HAL_ETH_STATE_BUSY; - - /* Check parameters */ - assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame)); - assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward)); - assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame)); - assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward)); - assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl)); - assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames)); - assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames)); - assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl)); - assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate)); - assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats)); - assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst)); - assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength)); - assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength)); - assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat)); - assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength)); - assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration)); - - /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ - /* Get the ETHERNET DMAOMR value */ - tmpreg = (heth->Instance)->DMAOMR; - /* Clear xx bits */ - tmpreg &= ETH_DMAOMR_CLEAR_MASK; - - tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | - dmaconf->ReceiveStoreForward | - dmaconf->FlushReceivedFrame | - dmaconf->TransmitStoreForward | - dmaconf->TransmitThresholdControl | - dmaconf->ForwardErrorFrames | - dmaconf->ForwardUndersizedGoodFrames | - dmaconf->ReceiveThresholdControl | - dmaconf->SecondFrameOperate); - - /* Write to ETHERNET DMAOMR */ - (heth->Instance)->DMAOMR = (uint32_t)tmpreg; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->DMAOMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMAOMR = tmpreg; - - /*----------------------- ETHERNET DMABMR Configuration --------------------*/ - (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats | - dmaconf->FixedBurst | - dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ - dmaconf->TxDMABurstLength | - dmaconf->EnhancedDescriptorFormat | - (dmaconf->DescriptorSkipLength << 2) | - dmaconf->DMAArbitration | - ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->DMABMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMABMR = tmpreg; - - /* Set the ETH state to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * - @verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - (+) Get the ETH handle state: - HAL_ETH_GetState(); - - - @endverbatim - * @{ - */ - -/** - * @brief Return the ETH HAL state - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL state - */ -HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) -{ - /* Return ETH state */ - return heth->State; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup ETH_Private_Functions - * @{ - */ - -/** - * @brief Configures Ethernet MAC and DMA with default parameters. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param err: Ethernet Init error - * @retval HAL status - */ -static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) -{ - ETH_MACInitTypeDef macinit; - ETH_DMAInitTypeDef dmainit; - uint32_t tmpreg = 0; - - if (err != ETH_SUCCESS) /* Auto-negotiation failed */ - { - /* Set Ethernet duplex mode to Full-duplex */ - (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; - - /* Set Ethernet speed to 100M */ - (heth->Init).Speed = ETH_SPEED_100M; - } - - /* Ethernet MAC default initialization **************************************/ - macinit.Watchdog = ETH_WATCHDOG_ENABLE; - macinit.Jabber = ETH_JABBER_ENABLE; - macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT; - macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE; - macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE; - macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE; - if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) - { - macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; - } - else - { - macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE; - } - macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE; - macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE; - macinit.BackOffLimit = ETH_BACKOFFLIMIT_10; - macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE; - macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE; - macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE; - macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL; - macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE; - macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL; - macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE; - macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT; - macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT; - macinit.HashTableHigh = 0x0; - macinit.HashTableLow = 0x0; - macinit.PauseTime = 0x0; - macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE; - macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4; - macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE; - macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE; - macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE; - macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT; - macinit.VLANTagIdentifier = 0x0; - - /*------------------------ ETHERNET MACCR Configuration --------------------*/ - /* Get the ETHERNET MACCR value */ - tmpreg = (heth->Instance)->MACCR; - /* Clear WD, PCE, PS, TE and RE bits */ - tmpreg &= ETH_MACCR_CLEAR_MASK; - /* Set the WD bit according to ETH Watchdog value */ - /* Set the JD: bit according to ETH Jabber value */ - /* Set the IFG bit according to ETH InterFrameGap value */ - /* Set the DCRS bit according to ETH CarrierSense value */ - /* Set the FES bit according to ETH Speed value */ - /* Set the DO bit according to ETH ReceiveOwn value */ - /* Set the LM bit according to ETH LoopbackMode value */ - /* Set the DM bit according to ETH Mode value */ - /* Set the IPCO bit according to ETH ChecksumOffload value */ - /* Set the DR bit according to ETH RetryTransmission value */ - /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */ - /* Set the BL bit according to ETH BackOffLimit value */ - /* Set the DC bit according to ETH DeferralCheck value */ - tmpreg |= (uint32_t)(macinit.Watchdog | - macinit.Jabber | - macinit.InterFrameGap | - macinit.CarrierSense | - (heth->Init).Speed | - macinit.ReceiveOwn | - macinit.LoopbackMode | - (heth->Init).DuplexMode | - macinit.ChecksumOffload | - macinit.RetryTransmission | - macinit.AutomaticPadCRCStrip | - macinit.BackOffLimit | - macinit.DeferralCheck); - - /* Write to ETHERNET MACCR */ - (heth->Instance)->MACCR = (uint32_t)tmpreg; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; - - /*----------------------- ETHERNET MACFFR Configuration --------------------*/ - /* Set the RA bit according to ETH ReceiveAll value */ - /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */ - /* Set the PCF bit according to ETH PassControlFrames value */ - /* Set the DBF bit according to ETH BroadcastFramesReception value */ - /* Set the DAIF bit according to ETH DestinationAddrFilter value */ - /* Set the PR bit according to ETH PromiscuousMode value */ - /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */ - /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */ - /* Write to ETHERNET MACFFR */ - (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll | - macinit.SourceAddrFilter | - macinit.PassControlFrames | - macinit.BroadcastFramesReception | - macinit.DestinationAddrFilter | - macinit.PromiscuousMode | - macinit.MulticastFramesFilter | - macinit.UnicastFramesFilter); - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACFFR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFFR = tmpreg; - - /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/ - /* Write to ETHERNET MACHTHR */ - (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh; - - /* Write to ETHERNET MACHTLR */ - (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow; - /*----------------------- ETHERNET MACFCR Configuration -------------------*/ - - /* Get the ETHERNET MACFCR value */ - tmpreg = (heth->Instance)->MACFCR; - /* Clear xx bits */ - tmpreg &= ETH_MACFCR_CLEAR_MASK; - - /* Set the PT bit according to ETH PauseTime value */ - /* Set the DZPQ bit according to ETH ZeroQuantaPause value */ - /* Set the PLT bit according to ETH PauseLowThreshold value */ - /* Set the UP bit according to ETH UnicastPauseFrameDetect value */ - /* Set the RFE bit according to ETH ReceiveFlowControl value */ - /* Set the TFE bit according to ETH TransmitFlowControl value */ - tmpreg |= (uint32_t)((macinit.PauseTime << 16) | - macinit.ZeroQuantaPause | - macinit.PauseLowThreshold | - macinit.UnicastPauseFrameDetect | - macinit.ReceiveFlowControl | - macinit.TransmitFlowControl); - - /* Write to ETHERNET MACFCR */ - (heth->Instance)->MACFCR = (uint32_t)tmpreg; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACFCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFCR = tmpreg; - - /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/ - /* Set the ETV bit according to ETH VLANTagComparison value */ - /* Set the VL bit according to ETH VLANTagIdentifier value */ - (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison | - macinit.VLANTagIdentifier); - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACVLANTR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACVLANTR = tmpreg; - - /* Ethernet DMA default initialization ************************************/ - dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE; - dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE; - dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE; - dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; - dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; - dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE; - dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE; - dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES; - dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE; - dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE; - dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE; - dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; - dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; - dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE; - dmainit.DescriptorSkipLength = 0x0; - dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; - - /* Get the ETHERNET DMAOMR value */ - tmpreg = (heth->Instance)->DMAOMR; - /* Clear xx bits */ - tmpreg &= ETH_DMAOMR_CLEAR_MASK; - - /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */ - /* Set the RSF bit according to ETH ReceiveStoreForward value */ - /* Set the DFF bit according to ETH FlushReceivedFrame value */ - /* Set the TSF bit according to ETH TransmitStoreForward value */ - /* Set the TTC bit according to ETH TransmitThresholdControl value */ - /* Set the FEF bit according to ETH ForwardErrorFrames value */ - /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */ - /* Set the RTC bit according to ETH ReceiveThresholdControl value */ - /* Set the OSF bit according to ETH SecondFrameOperate value */ - tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | - dmainit.ReceiveStoreForward | - dmainit.FlushReceivedFrame | - dmainit.TransmitStoreForward | - dmainit.TransmitThresholdControl | - dmainit.ForwardErrorFrames | - dmainit.ForwardUndersizedGoodFrames | - dmainit.ReceiveThresholdControl | - dmainit.SecondFrameOperate); - - /* Write to ETHERNET DMAOMR */ - (heth->Instance)->DMAOMR = (uint32_t)tmpreg; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->DMAOMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMAOMR = tmpreg; - - /*----------------------- ETHERNET DMABMR Configuration ------------------*/ - /* Set the AAL bit according to ETH AddressAlignedBeats value */ - /* Set the FB bit according to ETH FixedBurst value */ - /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */ - /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */ - /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/ - /* Set the DSL bit according to ETH DesciptorSkipLength value */ - /* Set the PR and DA bits according to ETH DMAArbitration value */ - (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats | - dmainit.FixedBurst | - dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ - dmainit.TxDMABurstLength | - dmainit.EnhancedDescriptorFormat | - (dmainit.DescriptorSkipLength << 2) | - dmainit.DMAArbitration | - ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->DMABMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMABMR = tmpreg; - - if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE) - { - /* Enable the Ethernet Rx Interrupt */ - __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R); - } - - /* Initialize MAC address in ethernet MAC */ - ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr); -} - -/** - * @brief Configures the selected MAC address. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param MacAddr: The MAC address to configure - * This parameter can be one of the following values: - * @arg ETH_MAC_Address0: MAC Address0 - * @arg ETH_MAC_Address1: MAC Address1 - * @arg ETH_MAC_Address2: MAC Address2 - * @arg ETH_MAC_Address3: MAC Address3 - * @param Addr: Pointer to MAC address buffer data (6 bytes) - * @retval HAL status - */ -static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr) -{ - uint32_t tmpreg; - - /* Check the parameters */ - assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); - - /* Calculate the selected MAC address high register */ - tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4]; - /* Load the selected MAC address high register */ - (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg; - /* Calculate the selected MAC address low register */ - tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0]; - - /* Load the selected MAC address low register */ - (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg; -} - -/** - * @brief Enables the MAC transmission. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg = 0; - - /* Enable the MAC transmission */ - (heth->Instance)->MACCR |= ETH_MACCR_TE; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; -} - -/** - * @brief Disables the MAC transmission. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg = 0; - - /* Disable the MAC transmission */ - (heth->Instance)->MACCR &= ~ETH_MACCR_TE; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; -} - -/** - * @brief Enables the MAC reception. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg = 0; - - /* Enable the MAC reception */ - (heth->Instance)->MACCR |= ETH_MACCR_RE; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; -} - -/** - * @brief Disables the MAC reception. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg = 0; - - /* Disable the MAC reception */ - (heth->Instance)->MACCR &= ~ETH_MACCR_RE; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; -} - -/** - * @brief Enables the DMA transmission. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth) -{ - /* Enable the DMA transmission */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST; -} - -/** - * @brief Disables the DMA transmission. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth) -{ - /* Disable the DMA transmission */ - (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST; -} - -/** - * @brief Enables the DMA reception. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth) -{ - /* Enable the DMA reception */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR; -} - -/** - * @brief Disables the DMA reception. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth) -{ - /* Disable the DMA reception */ - (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR; -} - -/** - * @brief Clears the ETHERNET transmit FIFO. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg = 0; - - /* Set the Flush Transmit FIFO bit */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->DMAOMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMAOMR = tmpreg; -} - -/** - * @} - */ - -#endif /* HAL_ETH_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c deleted file mode 100644 index a997ce3..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c +++ /dev/null @@ -1,821 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_flash.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief FLASH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the internal FLASH memory: - * + Program operations functions - * + Memory Control functions - * + Peripheral Errors functions - * - @verbatim - ============================================================================== - ##### FLASH peripheral features ##### - ============================================================================== - - [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses - to the Flash memory. It implements the erase and program Flash memory operations - and the read and write protection mechanisms. - - [..] The Flash memory interface accelerates code execution with a system of instruction - prefetch and cache lines. - - [..] The FLASH main features are: - (+) Flash memory read operations - (+) Flash memory program/erase operations - (+) Read / write protections - (+) Prefetch on I-Code - (+) 64 cache lines of 128 bits on I-Code - (+) 8 cache lines of 128 bits on D-Code - - ##### How to use this driver ##### - ============================================================================== - [..] - This driver provides functions and macros to configure and program the FLASH - memory of all STM32F7xx devices. - - (#) FLASH Memory IO Programming functions: - (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and - HAL_FLASH_Lock() functions - (++) Program functions: byte, half word, word and double word - (++) There Two modes of programming : - (+++) Polling mode using HAL_FLASH_Program() function - (+++) Interrupt mode using HAL_FLASH_Program_IT() function - - (#) Interrupts and flags management functions : - (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() - (++) Wait for last FLASH operation according to its status - (++) Get error flag status by calling HAL_SetErrorCode() - [..] - In addition to these functions, this driver includes a set of macros allowing - to handle the following operations: - (+) Set the latency - (+) Enable/Disable the prefetch buffer - (+) Enable/Disable the Instruction cache and the Data cache - (+) Reset the Instruction cache and the Data cache - (+) Enable/Disable the FLASH interrupts - (+) Monitor the FLASH flags status - [..] - (@) For any Flash memory program operation (erase or program), the CPU clock frequency - (HCLK) must be at least 1MHz. - (@) The contents of the Flash memory are not guaranteed if a device reset occurs during - a Flash memory operation. - (@) Any attempt to read the Flash memory while it is being written or erased, causes the - bus to stall. Read operations are processed correctly once the program operation has - completed. This means that code or data fetches cannot be performed while a write/erase - operation is ongoing. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup FLASH FLASH - * @brief FLASH HAL module driver - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup FLASH_Private_Constants - * @{ - */ -#define SECTOR_MASK ((uint32_t)0xFFFFFF07U) -#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */ -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @addtogroup FLASH_Private_Variables - * @{ - */ -/* Variable used for Erase sectors under interruption */ -FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup FLASH_Private_Functions - * @{ - */ -/* Program operations */ -static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); -static void FLASH_Program_Word(uint32_t Address, uint32_t Data); -static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); -static void FLASH_Program_Byte(uint32_t Address, uint8_t Data); -static void FLASH_SetErrorCode(void); - -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Functions FLASH Exported Functions - * @{ - */ - -/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions - * @brief Programming operation functions - * -@verbatim - =============================================================================== - ##### Programming operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the FLASH - program operations. - -@endverbatim - * @{ - */ - -/** - * @brief Program byte, halfword, word or double word at a specified address - * @param TypeProgram: Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - switch(TypeProgram) - { - case FLASH_TYPEPROGRAM_BYTE : - { - /*Program byte (8-bit) at a specified address.*/ - FLASH_Program_Byte(Address, (uint8_t) Data); - break; - } - - case FLASH_TYPEPROGRAM_HALFWORD : - { - /*Program halfword (16-bit) at a specified address.*/ - FLASH_Program_HalfWord(Address, (uint16_t) Data); - break; - } - - case FLASH_TYPEPROGRAM_WORD : - { - /*Program word (32-bit) at a specified address.*/ - FLASH_Program_Word(Address, (uint32_t) Data); - break; - } - - case FLASH_TYPEPROGRAM_DOUBLEWORD : - { - /*Program double word (64-bit) at a specified address.*/ - FLASH_Program_DoubleWord(Address, Data); - break; - } - default : - break; - } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Program byte, halfword, word or double word at a specified address with interrupt enabled. - * @param TypeProgram: Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - - /* Enable End of FLASH Operation interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); - - /* Enable Error source interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); - - /* Clear pending flags (if any) */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\ - FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR); - - pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; - pFlash.Address = Address; - - switch(TypeProgram) - { - case FLASH_TYPEPROGRAM_BYTE : - { - /*Program byte (8-bit) at a specified address.*/ - FLASH_Program_Byte(Address, (uint8_t) Data); - break; - } - - case FLASH_TYPEPROGRAM_HALFWORD : - { - /*Program halfword (16-bit) at a specified address.*/ - FLASH_Program_HalfWord(Address, (uint16_t) Data); - break; - } - - case FLASH_TYPEPROGRAM_WORD : - { - /*Program word (32-bit) at a specified address.*/ - FLASH_Program_Word(Address, (uint32_t) Data); - break; - } - - case FLASH_TYPEPROGRAM_DOUBLEWORD : - { - /*Program double word (64-bit) at a specified address.*/ - FLASH_Program_DoubleWord(Address, Data); - break; - } - default : - break; - } - return status; -} - -/** - * @brief This function handles FLASH interrupt request. - * @retval None - */ -void HAL_FLASH_IRQHandler(void) -{ - uint32_t temp = 0; - - /* If the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - - /* If the erase operation is completed, disable the SER Bit */ - FLASH->CR &= (~FLASH_CR_SER); - FLASH->CR &= SECTOR_MASK; - - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= (~FLASH_MER_BIT); - - /* Check FLASH End of Operation flag */ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) - { - switch (pFlash.ProcedureOnGoing) - { - case FLASH_PROC_SECTERASE : - { - /* Nb of sector to erased can be decreased */ - pFlash.NbSectorsToErase--; - - /* Check if there are still sectors to erase */ - if(pFlash.NbSectorsToErase != 0) - { - temp = pFlash.Sector; - /* Indicate user which sector has been erased */ - HAL_FLASH_EndOfOperationCallback(temp); - - /* Clear pending flags (if any) */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - - /* Increment sector number */ - temp = ++pFlash.Sector; - FLASH_Erase_Sector(temp, pFlash.VoltageForErase); - } - else - { - /* No more sectors to Erase, user callback can be called.*/ - /* Reset Sector and stop Erase sectors procedure */ - pFlash.Sector = temp = 0xFFFFFFFFU; - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(temp); - /* Sector Erase procedure is completed */ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - } - break; - } - - case FLASH_PROC_MASSERASE : - { - /* MassErase ended. Return the selected bank : in this product we don't have Banks */ - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(0); - /* MAss Erase procedure is completed */ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - break; - } - - case FLASH_PROC_PROGRAM : - { - /*Program ended. Return the selected address*/ - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(pFlash.Address); - /* Programming procedure is completed */ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - break; - } - default : - break; - } - } - - /* Check FLASH operation error flags */ - if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR )) != RESET) - { - switch (pFlash.ProcedureOnGoing) - { - case FLASH_PROC_SECTERASE : - { - /* return the faulty sector */ - temp = pFlash.Sector; - pFlash.Sector = 0xFFFFFFFFU; - break; - } - case FLASH_PROC_MASSERASE : - { - /* No return in case of Mass Erase */ - temp = 0; - break; - } - case FLASH_PROC_PROGRAM : - { - /*return the faulty address*/ - temp = pFlash.Address; - break; - } - default : - break; - } - /*Save the Error code*/ - FLASH_SetErrorCode(); - - /* FLASH error interrupt user callback */ - HAL_FLASH_OperationErrorCallback(temp); - /* Clear FLASH error pending bits */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR ); - - /*Stop the procedure ongoing */ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - - if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) - { - /* Disable End of FLASH Operation interrupt */ - __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP); - - /* Disable Error source interrupt */ - __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - } - -} - -/** - * @brief FLASH end of operation interrupt callback - * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure - * - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that - * all the selected sectors have been erased) - * - Program : Address which was selected for data program - * - Mass Erase : No return value expected - * @retval None - */ -__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(ReturnValue); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_FLASH_EndOfOperationCallback could be implemented in the user file - */ -} - -/** - * @brief FLASH operation error interrupt callback - * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure - * - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that - * all the selected sectors have been erased) - * - Program : Address which was selected for data program - * - Mass Erase : No return value expected - * @retval None - */ -__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(ReturnValue); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_FLASH_OperationErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the FLASH - memory operations. - -@endverbatim - * @{ - */ - -/** - * @brief Unlock the FLASH control register access - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Unlock(void) -{ - if((FLASH->CR & FLASH_CR_LOCK) != RESET) - { - /* Authorize the FLASH Registers access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Locks the FLASH control register access - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Lock(void) -{ - /* Set the LOCK Bit to lock the FLASH Registers access */ - FLASH->CR |= FLASH_CR_LOCK; - - return HAL_OK; -} - -/** - * @brief Unlock the FLASH Option Control Registers access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) -{ - if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) - { - /* Authorizes the Option Byte register programming */ - FLASH->OPTKEYR = FLASH_OPT_KEY1; - FLASH->OPTKEYR = FLASH_OPT_KEY2; - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Lock the FLASH Option Control Registers access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) -{ - /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ - FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; - - return HAL_OK; -} - -/** - * @brief Launch the option byte loading. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) -{ - /* Set the OPTSTRT bit in OPTCR register */ - FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT; - - /* Wait for last operation to be completed */ - return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral Errors functions - * -@verbatim - =============================================================================== - ##### Peripheral Errors functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time Errors of the FLASH peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Get the specific FLASH error flag. - * @retval FLASH_ErrorCode: The returned value can be: - * @arg FLASH_ERROR_ERS: FLASH Erasing Sequence error flag - * @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag - * @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag - * @arg FLASH_ERROR_WRP: FLASH Write protected error flag - * @arg FLASH_ERROR_OPERATION: FLASH operation Error flag - */ -uint32_t HAL_FLASH_GetError(void) -{ - return pFlash.ErrorCode; -} - -/** - * @} - */ - -/** - * @brief Wait for a FLASH operation to complete. - * @param Timeout: maximum flash operationtimeout - * @retval HAL Status - */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Clear Error Code */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. - Even if the FLASH operation fails, the BUSY flag will be reset and an error - flag will be set */ - /* Get tick */ - tickstart = HAL_GetTick(); - - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - return HAL_TIMEOUT; - } - } - } - - if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ - FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR )) != RESET) - { - /*Save the error code*/ - FLASH_SetErrorCode(); - return HAL_ERROR; - } - - /* If there is an error flag set */ - return HAL_OK; - -} - -/** - * @brief Program a double word (64-bit) at a specified address. - * @note This function must be used when the device voltage range is from - * 2.7V to 3.6V and an External Vpp is present. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval None - */ -static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) -{ - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* If the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint64_t*)Address = Data; - - /* Data synchronous Barrier (DSB) Just after the write operation - This will force the CPU to respect the sequence of instruction (no optimization).*/ - __DSB(); -} - - -/** - * @brief Program word (32-bit) at a specified address. - * @note This function must be used when the device voltage range is from - * 2.7V to 3.6V. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval None - */ -static void FLASH_Program_Word(uint32_t Address, uint32_t Data) -{ - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* If the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint32_t*)Address = Data; - - /* Data synchronous Barrier (DSB) Just after the write operation - This will force the CPU to respect the sequence of instruction (no optimization).*/ - __DSB(); -} - -/** - * @brief Program a half-word (16-bit) at a specified address. - * @note This function must be used when the device voltage range is from - * 2.7V to 3.6V. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval None - */ -static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* If the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_HALF_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint16_t*)Address = Data; - - /* Data synchronous Barrier (DSB) Just after the write operation - This will force the CPU to respect the sequence of instruction (no optimization).*/ - __DSB(); - -} - -/** - * @brief Program byte (8-bit) at a specified address. - * @note This function must be used when the device voltage range is from - * 2.7V to 3.6V. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval None - */ -static void FLASH_Program_Byte(uint32_t Address, uint8_t Data) -{ - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* If the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_BYTE; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint8_t*)Address = Data; - - /* Data synchronous Barrier (DSB) Just after the write operation - This will force the CPU to respect the sequence of instruction (no optimization).*/ - __DSB(); -} - -/** - * @brief Set the specific FLASH error flag. - * @retval None - */ -static void FLASH_SetErrorCode(void) -{ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ERSERR) != RESET) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION; - } -} - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c deleted file mode 100644 index 5cec4d9..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c +++ /dev/null @@ -1,1038 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_flash_ex.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Extended FLASH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the FLASH extension peripheral: - * + Extended programming operations functions - * - @verbatim - ============================================================================== - ##### Flash Extension features ##### - ============================================================================== - - [..] Comparing to other previous devices, the FLASH interface for STM32F76xx/STM32F77xx - devices contains the following additional features - - (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write - capability (RWW) - (+) Dual bank memory organization - (+) Dual boot mode - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to configure and program the FLASH memory - of all STM32F7xx devices. It includes - (#) FLASH Memory Erase functions: - (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and - HAL_FLASH_Lock() functions - (++) Erase function: Erase sector, erase all sectors - (++) There are two modes of erase : - (+++) Polling Mode using HAL_FLASHEx_Erase() - (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() - - (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to : - (++) Set/Reset the write protection - (++) Set the Read protection Level - (++) Set the BOR level - (++) Program the user Option Bytes - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup FLASHEx FLASHEx - * @brief FLASH HAL Extension module driver - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup FLASHEx_Private_Constants - * @{ - */ -#define SECTOR_MASK ((uint32_t)0xFFFFFF07) -#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @addtogroup FLASHEx_Private_Variables - * @{ - */ -extern FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup FLASHEx_Private_Functions - * @{ - */ -/* Option bytes control */ -static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector); -static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector); -static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level); -static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level); -static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address); -static uint32_t FLASH_OB_GetUser(void); -static uint32_t FLASH_OB_GetWRP(void); -static uint8_t FLASH_OB_GetRDP(void); -static uint32_t FLASH_OB_GetBOR(void); -static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption); - -#if defined (FLASH_OPTCR_nDBANK) -static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks); -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \ - uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot); -#else -static void FLASH_MassErase(uint8_t VoltageRange); -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby); -#endif /* FLASH_OPTCR_nDBANK */ - -extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions - * @{ - */ - -/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions - * @brief Extended IO operation functions - * -@verbatim - =============================================================================== - ##### Extended programming operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the Extension FLASH - programming operations Operations. - -@endverbatim - * @{ - */ -/** - * @brief Perform a mass erase or erase the specified FLASH memory sectors - * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @param[out] SectorError: pointer to variable that - * contains the configuration information on faulty sector in case of error - * (0xFFFFFFFF means that all the sectors have been correctly erased) - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError) -{ - HAL_StatusTypeDef status = HAL_ERROR; - uint32_t index = 0; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /*Initialization of SectorError variable*/ - *SectorError = 0xFFFFFFFFU; - - if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) - { - /*Mass erase to be done*/ -#if defined (FLASH_OPTCR_nDBANK) - FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); -#else - FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); -#endif /* FLASH_OPTCR_nDBANK */ - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= (~FLASH_MER_BIT); - } - else - { - /* Check the parameters */ - assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); - - /* Erase by sector by sector to be done*/ - for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++) - { - FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the SER Bit and SNB Bits */ - CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); - - if(status != HAL_OK) - { - /* In case of error, stop erase procedure and return the faulty sector*/ - *SectorError = index; - break; - } - } - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled - * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - - /* Enable End of FLASH Operation interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); - - /* Enable Error source interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); - - /* Clear pending flags (if any) */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\ - FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR); - - if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) - { - /*Mass erase to be done*/ - pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; -#if defined (FLASH_OPTCR_nDBANK) - FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); -#else - FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); -#endif /* FLASH_OPTCR_nDBANK */ - } - else - { - /* Erase by sector to be done*/ - - /* Check the parameters */ - assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); - - pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE; - pFlash.NbSectorsToErase = pEraseInit->NbSectors; - pFlash.Sector = pEraseInit->Sector; - pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange; - - /*Erase 1st sector and wait for IT*/ - FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange); - } - - return status; -} - -/** - * @brief Program option bytes - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that - * contains the configuration information for the programming. - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); - - /* Write protection configuration */ - if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) - { - assert_param(IS_WRPSTATE(pOBInit->WRPState)); - if(pOBInit->WRPState == OB_WRPSTATE_ENABLE) - { - /*Enable of Write protection on the selected Sector*/ - status = FLASH_OB_EnableWRP(pOBInit->WRPSector); - } - else - { - /*Disable of Write protection on the selected Sector*/ - status = FLASH_OB_DisableWRP(pOBInit->WRPSector); - } - } - - /* Read protection configuration */ - if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) - { - status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); - } - - /* USER configuration */ - if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) - { -#if defined (FLASH_OPTCR_nDBANK) - status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, - pOBInit->USERConfig & OB_IWDG_SW, - pOBInit->USERConfig & OB_STOP_NO_RST, - pOBInit->USERConfig & OB_STDBY_NO_RST, - pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE, - pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE, - pOBInit->USERConfig & OB_NDBANK_SINGLE_BANK, - pOBInit->USERConfig & OB_DUAL_BOOT_DISABLE); -#else - status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, - pOBInit->USERConfig & OB_IWDG_SW, - pOBInit->USERConfig & OB_STOP_NO_RST, - pOBInit->USERConfig & OB_STDBY_NO_RST, - pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE, - pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE); -#endif /* FLASH_OPTCR_nDBANK */ - } - - /* BOR Level configuration */ - if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) - { - status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel); - } - - /* Boot 0 Address configuration */ - if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_0) == OPTIONBYTE_BOOTADDR_0) - { - status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_0, pOBInit->BootAddr0); - } - - /* Boot 1 Address configuration */ - if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_1) == OPTIONBYTE_BOOTADDR_1) - { - status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1); - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Get the Option byte configuration - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that - * contains the configuration information for the programming. - * - * @retval None - */ -void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) -{ - pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ - OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1; - - /*Get WRP*/ - pOBInit->WRPSector = FLASH_OB_GetWRP(); - - /*Get RDP Level*/ - pOBInit->RDPLevel = FLASH_OB_GetRDP(); - - /*Get USER*/ - pOBInit->USERConfig = FLASH_OB_GetUser(); - - /*Get BOR Level*/ - pOBInit->BORLevel = FLASH_OB_GetBOR(); - - /*Get Boot Address when Boot pin = 0 */ - pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0); - - /*Get Boot Address when Boot pin = 1 */ - pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1); -} -/** - * @} - */ - -#if defined (FLASH_OPTCR_nDBANK) -/** - * @brief Full erase of FLASH memory sectors - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * @param Banks: Banks to be erased - * This parameter can be one of the following values: - * @arg FLASH_BANK_1: Bank1 to be erased - * @arg FLASH_BANK_2: Bank2 to be erased - * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased - * - * @retval HAL Status - */ -static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) -{ - /* Check the parameters */ - assert_param(IS_VOLTAGERANGE(VoltageRange)); - assert_param(IS_FLASH_BANK(Banks)); - - /* if the previous operation is completed, proceed to erase all sectors */ - FLASH->CR &= CR_PSIZE_MASK; - if(Banks == FLASH_BANK_BOTH) - { - /* bank1 & bank2 will be erased*/ - FLASH->CR |= FLASH_MER_BIT; - } - else if(Banks == FLASH_BANK_2) - { - /*Only bank2 will be erased*/ - FLASH->CR |= FLASH_CR_MER2; - } - else - { - /*Only bank1 will be erased*/ - FLASH->CR |= FLASH_CR_MER1; - } - FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8); - /* Data synchronous Barrier (DSB) Just after the write operation - This will force the CPU to respect the sequence of instruction (no optimization).*/ - __DSB(); -} - -/** - * @brief Erase the specified FLASH memory sector - * @param Sector: FLASH sector to erase - * The value of this parameter depend on device used within the same series - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval None - */ -void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_SECTOR(Sector)); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == FLASH_VOLTAGE_RANGE_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == FLASH_VOLTAGE_RANGE_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == FLASH_VOLTAGE_RANGE_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - - /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */ - if(Sector > FLASH_SECTOR_11) - { - Sector += 4; - } - - /* If the previous operation is completed, proceed to erase the sector */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); - FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB)); - FLASH->CR |= FLASH_CR_STRT; - - /* Data synchronous Barrier (DSB) Just after the write operation - This will force the CPU to respect the sequence of instruction (no optimization).*/ - __DSB(); -} - -/** - * @brief Return the FLASH Write Protection Option Bytes value. - * @retval uint32_t FLASH Write Protection Option Bytes value - */ -static uint32_t FLASH_OB_GetWRP(void) -{ - /* Return the FLASH write protection Register value */ - return ((uint32_t)(FLASH->OPTCR & 0x0FFF0000)); -} - -/** - * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param Wwdg: Selects the IWDG mode - * This parameter can be one of the following values: - * @arg OB_WWDG_SW: Software WWDG selected - * @arg OB_WWDG_HW: Hardware WWDG selected - * @param Iwdg: Selects the WWDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software IWDG selected - * @arg OB_IWDG_HW: Hardware IWDG selected - * @param Stop: Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NO_RST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param Stdby: Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @param Iwdgstop: Independent watchdog counter freeze in Stop mode. - * This parameter can be one of the following values: - * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP - * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP - * @param Iwdgstdby: Independent watchdog counter freeze in standby mode. - * This parameter can be one of the following values: - * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY - * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY - * @param NDBank: Flash Single Bank mode enabled. - * This parameter can be one of the following values: - * @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank) - * @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mode) - * @param NDBoot: Flash Dual boot mode disable. - * This parameter can be one of the following values: - * @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot - * @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot - - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \ - uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot) -{ - uint32_t useroptionmask = 0x00; - uint32_t useroptionvalue = 0x00; - - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_WWDG_SOURCE(Wwdg)); - assert_param(IS_OB_IWDG_SOURCE(Iwdg)); - assert_param(IS_OB_STOP_SOURCE(Stop)); - assert_param(IS_OB_STDBY_SOURCE(Stdby)); - assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop)); - assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby)); - assert_param(IS_OB_NDBANK(NDBank)); - assert_param(IS_OB_NDBOOT(NDBoot)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \ - FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \ - FLASH_OPTCR_nDBOOT | FLASH_OPTCR_nDBANK); - - useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby | NDBoot | NDBank); - - /* Update User Option Byte */ - MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue); - } - - return status; -} - -/** - * @brief Return the FLASH User Option Byte value. - * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), - * nRST_STDBY(Bit7), nDBOOT(Bit28), nDBANK(Bit29), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31). - */ -static uint32_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return ((uint32_t)(FLASH->OPTCR & 0xF00000F0U)); -} -#else - -/** - * @brief Full erase of FLASH memory sectors - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval HAL Status - */ -static void FLASH_MassErase(uint8_t VoltageRange) -{ - /* Check the parameters */ - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - /* if the previous operation is completed, proceed to erase all sectors */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_CR_MER; - FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8); - /* Data synchronous Barrier (DSB) Just after the write operation - This will force the CPU to respect the sequence of instruction (no optimization).*/ - __DSB(); -} - -/** - * @brief Erase the specified FLASH memory sector - * @param Sector: FLASH sector to erase - * The value of this parameter depend on device used within the same series - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval None - */ -void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_SECTOR(Sector)); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == FLASH_VOLTAGE_RANGE_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == FLASH_VOLTAGE_RANGE_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == FLASH_VOLTAGE_RANGE_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - - /* If the previous operation is completed, proceed to erase the sector */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR &= SECTOR_MASK; - FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB)); - FLASH->CR |= FLASH_CR_STRT; - - /* Data synchronous Barrier (DSB) Just after the write operation - This will force the CPU to respect the sequence of instruction (no optimization).*/ - __DSB(); -} - -/** - * @brief Return the FLASH Write Protection Option Bytes value. - * @retval uint32_t FLASH Write Protection Option Bytes value - */ -static uint32_t FLASH_OB_GetWRP(void) -{ - /* Return the FLASH write protection Register value */ - return ((uint32_t)(FLASH->OPTCR & 0x00FF0000)); -} - -/** - * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param Wwdg: Selects the IWDG mode - * This parameter can be one of the following values: - * @arg OB_WWDG_SW: Software WWDG selected - * @arg OB_WWDG_HW: Hardware WWDG selected - * @param Iwdg: Selects the WWDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software IWDG selected - * @arg OB_IWDG_HW: Hardware IWDG selected - * @param Stop: Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NO_RST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param Stdby: Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @param Iwdgstop: Independent watchdog counter freeze in Stop mode. - * This parameter can be one of the following values: - * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP - * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP - * @param Iwdgstdby: Independent watchdog counter freeze in standby mode. - * This parameter can be one of the following values: - * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY - * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby) -{ - uint32_t useroptionmask = 0x00; - uint32_t useroptionvalue = 0x00; - - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_WWDG_SOURCE(Wwdg)); - assert_param(IS_OB_IWDG_SOURCE(Iwdg)); - assert_param(IS_OB_STOP_SOURCE(Stop)); - assert_param(IS_OB_STDBY_SOURCE(Stdby)); - assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop)); - assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \ - FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY); - - useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby); - - /* Update User Option Byte */ - MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue); - } - - return status; - -} - -/** - * @brief Return the FLASH User Option Byte value. - * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), - * nRST_STDBY(Bit7), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31). - */ -static uint32_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return ((uint32_t)(FLASH->OPTCR & 0xC00000F0)); -} -#endif /* FLASH_OPTCR_nDBANK */ - -/** - * @brief Enable the write protection of the desired bank1 or bank2 sectors - * - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash sector i if CortexM7 - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * - * @param WRPSector: specifies the sector(s) to be write protected. - * This parameter can be one of the following values: - * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices) - * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices) - * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices) - * @arg OB_WRP_SECTOR_All - * - * @retval HAL FLASH State - */ -static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_WRP_SECTOR(WRPSector)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /*Write protection enabled on sectors */ - FLASH->OPTCR &= (~WRPSector); - } - - return status; -} - -/** - * @brief Disable the write protection of the desired bank1 or bank 2 sectors - * - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash sector i if CortexM4 - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * - * @param WRPSector: specifies the sector(s) to be write protected. - * This parameter can be one of the following values: - * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices) - * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices) - * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices) - * @arg OB_WRP_Sector_All - * - * - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_WRP_SECTOR(WRPSector)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Write protection disabled on sectors */ - FLASH->OPTCR |= (WRPSector); - } - - return status; -} - -/** - * @brief Set the read protection level. - * @param Level: specifies the read protection level. - * This parameter can be one of the following values: - * @arg OB_RDP_LEVEL_0: No protection - * @arg OB_RDP_LEVEL_1: Read protection of the memory - * @arg OB_RDP_LEVEL_2: Full chip protection - * - * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 - * - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_RDP_LEVEL(Level)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level; - } - - return status; -} - -/** - * @brief Set the BOR Level. - * @param Level: specifies the Option Bytes BOR Reset Level. - * This parameter can be one of the following values: - * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V - * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V - * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V - * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level) -{ - /* Check the parameters */ - assert_param(IS_OB_BOR_LEVEL(Level)); - - /* Set the BOR Level */ - MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_BOR_LEV, Level); - - return HAL_OK; - -} - -/** - * @brief Configure Boot base address. - * - * @param BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1 - * This parameter can be one of the following values: - * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 - * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 - * @param Address: specifies Boot base address - * This parameter can be one of the following values: - * @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) - * @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) - * @arg OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000) - * @arg OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000) - * @arg OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000) - * @arg OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000) - * @arg OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) - * - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_BOOT_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - if(BootOption == OPTIONBYTE_BOOTADDR_0) - { - MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address); - } - else - { - MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16)); - } - } - - return status; -} - -/** - * @brief Returns the FLASH Read Protection level. - * @retval FlagStatus FLASH ReadOut Protection Status: - * This parameter can be one of the following values: - * @arg OB_RDP_LEVEL_0: No protection - * @arg OB_RDP_LEVEL_1: Read protection of the memory - * @arg OB_RDP_LEVEL_2: Full chip protection - */ -static uint8_t FLASH_OB_GetRDP(void) -{ - uint8_t readstatus = OB_RDP_LEVEL_0; - - if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_0) - { - readstatus = OB_RDP_LEVEL_0; - } - else if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_2) - { - readstatus = OB_RDP_LEVEL_2; - } - else - { - readstatus = OB_RDP_LEVEL_1; - } - - return readstatus; -} - -/** - * @brief Returns the FLASH BOR level. - * @retval uint32_t The FLASH BOR level: - * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V - * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V - * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V - * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V - */ -static uint32_t FLASH_OB_GetBOR(void) -{ - /* Return the FLASH BOR level */ - return ((uint32_t)(FLASH->OPTCR & 0x0C)); -} - -/** - * @brief Configure Boot base address. - * - * @param BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1 - * This parameter can be one of the following values: - * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 - * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 - * - * @retval uint32_t Boot Base Address: - * - OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) - * - OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) - * - OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000) - * - OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000) - * - OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000) - * - OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000) - * - OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) - */ -static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption) -{ - uint32_t Address = 0; - - /* Return the Boot base Address */ - if(BootOption == OPTIONBYTE_BOOTADDR_0) - { - Address = FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD0; - } - else - { - Address = ((FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD1) >> 16); - } - - return Address; -} - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c deleted file mode 100644 index 2db3d64..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c +++ /dev/null @@ -1,543 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_gpio.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief GPIO HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the General Purpose Input/Output (GPIO) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * - @verbatim - ============================================================================== - ##### GPIO Peripheral features ##### - ============================================================================== - [..] - Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each - port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software - in several modes: - (+) Input mode - (+) Analog mode - (+) Output mode - (+) Alternate function mode - (+) External interrupt/event lines - - [..] - During and just after reset, the alternate functions and external interrupt - lines are not active and the I/O ports are configured in input floating mode. - - [..] - All GPIO pins have weak internal pull-up and pull-down resistors, which can be - activated or not. - - [..] - In Output or Alternate mode, each IO can be configured on open-drain or push-pull - type and the IO speed can be selected depending on the VDD value. - - [..] - All ports have external interrupt/event capability. To use external interrupt - lines, the port must be configured in input mode. All available GPIO pins are - connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. - - [..] - The external interrupt/event controller consists of up to 23 edge detectors - (16 lines are connected to GPIO) for generating event/interrupt requests (each - input line can be independently configured to select the type (interrupt or event) - and the corresponding trigger event (rising or falling or both). Each line can - also be masked independently. - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). - - (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). - (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure - (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef - structure. - (++) In case of Output or alternate function mode selection: the speed is - configured through "Speed" member from GPIO_InitTypeDef structure. - (++) In alternate mode is selection, the alternate function connected to the IO - is configured through "Alternate" member from GPIO_InitTypeDef structure. - (++) Analog mode is required when a pin is to be used as ADC channel - or DAC output. - (++) In case of external interrupt/event selection the "Mode" member from - GPIO_InitTypeDef structure select the type (interrupt or event) and - the corresponding trigger event (rising or falling or both). - - (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority - mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using - HAL_NVIC_EnableIRQ(). - - (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). - - (#) To set/reset the level of a pin configured in output mode use - HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). - - (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). - - - (#) During and just after reset, the alternate functions are not - active and the GPIO pins are configured in input floating mode (except JTAG - pins). - - (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose - (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has - priority over the GPIO function. - - (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as - general purpose PH0 and PH1, respectively, when the HSE oscillator is off. - The HSE has priority over the GPIO function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup GPIO GPIO - * @brief GPIO HAL module driver - * @{ - */ - -#ifdef HAL_GPIO_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup GPIO_Private_Constants GPIO Private Constants - * @{ - */ -#define GPIO_MODE ((uint32_t)0x00000003U) -#define EXTI_MODE ((uint32_t)0x10000000U) -#define GPIO_MODE_IT ((uint32_t)0x00010000U) -#define GPIO_MODE_EVT ((uint32_t)0x00020000U) -#define RISING_EDGE ((uint32_t)0x00100000U) -#define FALLING_EDGE ((uint32_t)0x00200000U) -#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U) - -#define GPIO_NUMBER ((uint32_t)16U) -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Functions GPIO Exported Functions - * @{ - */ - -/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to initialize and de-initialize the GPIOs - to be ready for use. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. - * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. - * @retval None - */ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) -{ - uint32_t position = 0x00; - uint32_t ioposition = 0x00; - uint32_t iocurrent = 0x00; - uint32_t temp = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); - assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); - assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); - - /* Configure the port pins */ - for(position = 0; position < GPIO_NUMBER; position++) - { - /* Get the IO position */ - ioposition = ((uint32_t)0x01) << position; - /* Get the current IO position */ - iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; - - if(iocurrent == ioposition) - { - /*--------------------- GPIO Mode Configuration ------------------------*/ - /* In case of Alternate function mode selection */ - if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Alternate function parameter */ - assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - - /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3]; - temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; - temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); - GPIOx->AFR[position >> 3] = temp; - } - - /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ - temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODER0 << (position * 2)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); - GPIOx->MODER = temp; - - /* In case of Output or Alternate function mode selection */ - if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || - (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Speed parameter */ - assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); - /* Configure the IO Speed */ - temp = GPIOx->OSPEEDR; - temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); - temp |= (GPIO_Init->Speed << (position * 2)); - GPIOx->OSPEEDR = temp; - - /* Configure the IO Output Type */ - temp = GPIOx->OTYPER; - temp &= ~(GPIO_OTYPER_OT_0 << position) ; - temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); - GPIOx->OTYPER = temp; - } - - /* Activate the Pull-up or Pull down resistor for the current IO */ - temp = GPIOx->PUPDR; - temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); - temp |= ((GPIO_Init->Pull) << (position * 2)); - GPIOx->PUPDR = temp; - - /*--------------------- EXTI Mode Configuration ------------------------*/ - /* Configure the External Interrupt or event for the current IO */ - if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) - { - /* Enable SYSCFG Clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - temp = SYSCFG->EXTICR[position >> 2]; - temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); - temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); - SYSCFG->EXTICR[position >> 2] = temp; - - /* Clear EXTI line configuration */ - temp = EXTI->IMR; - temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) - { - temp |= iocurrent; - } - EXTI->IMR = temp; - - temp = EXTI->EMR; - temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) - { - temp |= iocurrent; - } - EXTI->EMR = temp; - - /* Clear Rising Falling edge configuration */ - temp = EXTI->RTSR; - temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) - { - temp |= iocurrent; - } - EXTI->RTSR = temp; - - temp = EXTI->FTSR; - temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) - { - temp |= iocurrent; - } - EXTI->FTSR = temp; - } - } - } -} - -/** - * @brief De-initializes the GPIOx peripheral registers to their default reset values. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @retval None - */ -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) -{ - uint32_t position; - uint32_t ioposition = 0x00; - uint32_t iocurrent = 0x00; - uint32_t tmp = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - - /* Configure the port pins */ - for(position = 0; position < GPIO_NUMBER; position++) - { - /* Get the IO position */ - ioposition = ((uint32_t)0x01) << position; - /* Get the current IO position */ - iocurrent = (GPIO_Pin) & ioposition; - - if(iocurrent == ioposition) - { - /*------------------------- GPIO Mode Configuration --------------------*/ - /* Configure IO Direction in Input Floating Mode */ - GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2)); - - /* Configure the default Alternate Function in current IO */ - GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; - - /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); - - /* Configure the default value IO Output Type */ - GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; - - /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); - - /*------------------------- EXTI Mode Configuration --------------------*/ - tmp = SYSCFG->EXTICR[position >> 2]; - tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); - if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)))) - { - /* Configure the External Interrupt or event for the current IO */ - tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); - SYSCFG->EXTICR[position >> 2] &= ~tmp; - - /* Clear EXTI line configuration */ - EXTI->IMR &= ~((uint32_t)iocurrent); - EXTI->EMR &= ~((uint32_t)iocurrent); - - /* Clear Rising Falling edge configuration */ - EXTI->RTSR &= ~((uint32_t)iocurrent); - EXTI->FTSR &= ~((uint32_t)iocurrent); - } - } - } -} - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions - * @brief GPIO Read and Write - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_PIN_x where x can be (0..15). - * @retval The input port pin value. - */ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - GPIO_PinState bitstatus; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) - { - bitstatus = GPIO_PIN_SET; - } - else - { - bitstatus = GPIO_PIN_RESET; - } - return bitstatus; -} - -/** - * @brief Sets or clears the selected data port bit. - * - * @note This function uses GPIOx_BSRR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @param PinState: specifies the value to be written to the selected bit. - * This parameter can be one of the GPIO_PinState enum values: - * @arg GPIO_PIN_RESET: to clear the port pin - * @arg GPIO_PIN_SET: to set the port pin - * @retval None - */ -void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) -{ - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_PIN_ACTION(PinState)); - - if(PinState != GPIO_PIN_RESET) - { - GPIOx->BSRR = GPIO_Pin; - } - else - { - GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; - } -} - -/** - * @brief Toggles the specified GPIO pins. - * @param GPIOx: Where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: Specifies the pins to be toggled. - * @retval None - */ -void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->ODR ^= GPIO_Pin; -} - -/** - * @brief Locks GPIO Pins configuration registers. - * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, - * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. - * @note The configuration of the locked GPIO pins can no longer be modified - * until the next reset. - * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F7 family - * @param GPIO_Pin: specifies the port bit to be locked. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). - * @retval None - */ -HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - __IO uint32_t tmp = GPIO_LCKR_LCKK; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* Apply lock key write sequence */ - tmp |= GPIO_Pin; - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ - GPIOx->LCKR = tmp; - /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ - GPIOx->LCKR = tmp; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; - - if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) - { - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief This function handles EXTI interrupt request. - * @param GPIO_Pin: Specifies the pins connected EXTI line - * @retval None - */ -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) -{ - /* EXTI line interrupt detected */ - if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) - { - __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); - HAL_GPIO_EXTI_Callback(GPIO_Pin); - } -} - -/** - * @brief EXTI line detection callbacks. - * @param GPIO_Pin: Specifies the pins connected EXTI line - * @retval None - */ -__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(GPIO_Pin); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_GPIO_EXTI_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - - -/** - * @} - */ - -#endif /* HAL_GPIO_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c deleted file mode 100644 index b6bd942..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c +++ /dev/null @@ -1,1878 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_hash.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief HASH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the HASH peripheral: - * + Initialization and de-initialization functions - * + HASH/HMAC Processing functions by algorithm using polling mode - * + HASH/HMAC functions by algorithm using interrupt mode - * + HASH/HMAC functions by algorithm using DMA mode - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The HASH HAL driver can be used as follows: - (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit(): - (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE() - (##) In case of using processing APIs based on interrupts (e.g. HAL_HMAC_SHA1_Start_IT()) - (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority() - (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ() - (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler() - (##) In case of using DMA to control data transfer (e.g. HAL_HMAC_SHA1_Start_DMA()) - (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE() - (+++) Configure and enable one DMA stream one for managing data transfer from - memory to peripheral (input stream). Managing data transfer from - peripheral to memory can be performed only using CPU - (+++) Associate the initialized DMA handle to the HASH DMA handle - using __HAL_LINKDMA() - (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the DMA Stream using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() - (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly: - (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit. - (##) For HMAC, the encryption key. - (##) For HMAC, the key size used for encryption. - (#)Three processing functions are available: - (##) Polling mode: processing APIs are blocking functions - i.e. they process the data and wait till the digest computation is finished - e.g. HAL_HASH_SHA1_Start() - (##) Interrupt mode: encryption and decryption APIs are not blocking functions - i.e. they process the data under interrupt - e.g. HAL_HASH_SHA1_Start_IT() - (##) DMA mode: processing APIs are not blocking functions and the CPU is - not used for data transfer i.e. the data transfer is ensured by DMA - e.g. HAL_HASH_SHA1_Start_DMA() - (#)When the processing function is called at first time after HAL_HASH_Init() - the HASH peripheral is initialized and processes the buffer in input. - After that, the digest computation is started. - When processing multi-buffer use the accumulate function to write the - data in the peripheral without starting the digest computation. In last - buffer use the start function to input the last buffer ans start the digest - computation. - (##) e.g. HAL_HASH_SHA1_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation - (##) write (n-1)th data buffer in the peripheral without starting the digest computation - (##) HAL_HASH_SHA1_Start() : write (n)th data buffer in the peripheral and start the digest computation - (#)In HMAC mode, there is no Accumulate API. Only Start API is available. - (#)In case of using DMA, call the DMA start processing e.g. HAL_HASH_SHA1_Start_DMA(). - After that, call the finish function in order to get the digest value - e.g. HAL_HASH_SHA1_Finish() - (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) - -/** @defgroup HASH HASH - * @brief HASH HAL module driver. - * @{ - */ -#ifdef HAL_HASH_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup HASH_Private_Functions HASH Private Functions - * @{ - */ -static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma); -static void HASH_DMAError(DMA_HandleTypeDef *hdma); -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size); -static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size); -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup HASH_Private_Functions - * @{ - */ - -/** - * @brief DMA HASH Input Data complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) -{ - HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - uint32_t inputaddr = 0; - uint32_t buffersize = 0; - - if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE) - { - /* Disable the DMA transfer */ - HASH->CR &= (uint32_t)(~HASH_CR_DMAE); - - /* Change HASH peripheral state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Call Input data transfer complete callback */ - HAL_HASH_InCpltCallback(hhash); - } - else - { - /* Increment Interrupt counter */ - hhash->HashInCount++; - /* Disable the DMA transfer before starting the next transfer */ - HASH->CR &= (uint32_t)(~HASH_CR_DMAE); - - if(hhash->HashInCount <= 2) - { - /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */ - if(hhash->HashInCount == 1) - { - inputaddr = (uint32_t)hhash->pHashInBuffPtr; - buffersize = hhash->HashBuffSize; - } - /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */ - else if(hhash->HashInCount == 2) - { - inputaddr = (uint32_t)hhash->Init.pKey; - buffersize = hhash->Init.KeySize; - } - /* Configure the number of valid bits in last word of the message */ - MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4)); - - /* Set the HASH DMA transfer complete */ - hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; - - /* Enable the DMA In DMA Stream */ - HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4)); - - /* Enable DMA requests */ - HASH->CR |= (HASH_CR_DMAE); - } - else - { - /* Disable the DMA transfer */ - HASH->CR &= (uint32_t)(~HASH_CR_DMAE); - - /* Reset the InCount */ - hhash->HashInCount = 0; - - /* Change HASH peripheral state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Call Input data transfer complete callback */ - HAL_HASH_InCpltCallback(hhash); - } - } -} - -/** - * @brief DMA HASH communication error callback. - * @param hdma: DMA handle - * @retval None - */ -static void HASH_DMAError(DMA_HandleTypeDef *hdma) -{ - HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hhash->State= HAL_HASH_STATE_READY; - HAL_HASH_ErrorCallback(hhash); -} - -/** - * @brief Writes the input buffer in data register. - * @param pInBuffer: Pointer to input buffer - * @param Size: The size of input buffer - * @retval None - */ -static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size) -{ - uint32_t buffercounter; - uint32_t inputaddr = (uint32_t) pInBuffer; - - for(buffercounter = 0; buffercounter < Size; buffercounter+=4) - { - HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4; - } -} - -/** - * @brief Provides the message digest result. - * @param pMsgDigest: Pointer to the message digest - * @param Size: The size of the message digest in bytes - * @retval None - */ -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) -{ - uint32_t msgdigest = (uint32_t)pMsgDigest; - - switch(Size) - { - case 16: - /* Read the message digest */ - *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - break; - case 20: - /* Read the message digest */ - *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]); - break; - case 28: - /* Read the message digest */ - *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]); - break; - case 32: - /* Read the message digest */ - *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]); - break; - default: - break; - } -} - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup HASH_Exported_Functions - * @{ - */ - - -/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the HASH according to the specified parameters - in the HASH_InitTypeDef and creates the associated handle. - (+) DeInitialize the HASH peripheral. - (+) Initialize the HASH MSP. - (+) DeInitialize HASH MSP. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the HASH according to the specified parameters in the - HASH_HandleTypeDef and creates the associated handle. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) -{ - /* Check the hash handle allocation */ - if(hhash == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_HASH_DATATYPE(hhash->Init.DataType)); - - if(hhash->State == HAL_HASH_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hhash->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ - HAL_HASH_MspInit(hhash); - } - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Reset HashInCount, HashBuffSize and HashITCounter */ - hhash->HashInCount = 0; - hhash->HashBuffSize = 0; - hhash->HashITCounter = 0; - - /* Set the data type */ - HASH->CR |= (uint32_t) (hhash->Init.DataType); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Set the default HASH phase */ - hhash->Phase = HAL_HASH_PHASE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief DeInitializes the HASH peripheral. - * @note This API must be called before starting a new processing. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash) -{ - /* Check the HASH handle allocation */ - if(hhash == NULL) - { - return HAL_ERROR; - } - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Set the default HASH phase */ - hhash->Phase = HAL_HASH_PHASE_READY; - - /* Reset HashInCount, HashBuffSize and HashITCounter */ - hhash->HashInCount = 0; - hhash->HashBuffSize = 0; - hhash->HashITCounter = 0; - - /* DeInit the low level hardware */ - HAL_HASH_MspDeInit(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the HASH MSP. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @retval None - */ -__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhash); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_HASH_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes HASH MSP. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @retval None - */ -__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhash); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_HASH_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Input data transfer complete callback. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @retval None - */ - __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhash); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_HASH_InCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Data transfer Error callback. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @retval None - */ - __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhash); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_HASH_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief Digest computation complete callback. It is used only with interrupt. - * @note This callback is not relevant with DMA. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @retval None - */ - __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhash); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_HASH_DgstCpltCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions using polling mode - * @brief processing functions using polling mode - * -@verbatim - =============================================================================== - ##### HASH processing using polling mode functions##### - =============================================================================== - [..] This section provides functions allowing to calculate in polling mode - the hash value using one of the following algorithms: - (+) MD5 - (+) SHA1 - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer. - The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is multiple of 64 bytes, appending the input buffer is possible. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware - * and appending the input buffer is no more possible. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes. - * @param Timeout: Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT; - } - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - /* Write input buffer in data register */ - HASH_WriteData(pInBuffer, Size); - - /* Start the digest calculation */ - __HAL_HASH_START_DIGEST(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hhash->State = HAL_HASH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - - /* Read the message digest */ - HASH_GetDigest(pOutBuffer, 16); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the HASH peripheral in MD5 mode then writes the pInBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is multiple of 64 bytes, appending the input buffer is possible. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware - * and appending the input buffer is no more possible. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT; - } - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - /* Write input buffer in data register */ - HASH_WriteData(pInBuffer, Size); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer. - The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. - * @param Timeout: Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT; - } - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - /* Write input buffer in data register */ - HASH_WriteData(pInBuffer, Size); - - /* Start the digest calculation */ - __HAL_HASH_START_DIGEST(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hhash->State = HAL_HASH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - - /* Read the message digest */ - HASH_GetDigest(pOutBuffer, 20); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - /* Check the parameters */ - assert_param(IS_HASH_SHA1_BUFFER_SIZE(Size)); - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT; - } - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - /* Write input buffer in data register */ - HASH_WriteData(pInBuffer, Size); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions using interrupt mode - * @brief processing functions using interrupt mode. - * -@verbatim - =============================================================================== - ##### HASH processing using interrupt mode functions ##### - =============================================================================== - [..] This section provides functions allowing to calculate in interrupt mode - the hash value using one of the following algorithms: - (+) MD5 - (+) SHA1 - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer. - * The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) -{ - uint32_t inputaddr; - uint32_t outputaddr; - uint32_t buffercounter; - uint32_t inputcounter; - - /* Process Locked */ - __HAL_LOCK(hhash); - - if(hhash->State == HAL_HASH_STATE_READY) - { - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - hhash->HashInCount = Size; - hhash->pHashInBuffPtr = pInBuffer; - hhash->pHashOutBuffPtr = pOutBuffer; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Select the SHA1 mode */ - HASH->CR |= HASH_ALGOSELECTION_MD5; - /* Reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_CR_INIT; - } - - /* Reset interrupt counter */ - hhash->HashITCounter = 0; - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Enable Interrupts */ - HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI); - - /* Return function status */ - return HAL_OK; - } - if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS)) - { - outputaddr = (uint32_t)hhash->pHashOutBuffPtr; - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]); - outputaddr+=4; - *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]); - outputaddr+=4; - *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]); - outputaddr+=4; - *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]); - - if(hhash->HashInCount == 0) - { - /* Disable Interrupts */ - HASH->IMR = 0; - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - /* Call digest computation complete callback */ - HAL_HASH_DgstCpltCallback(hhash); - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; - } - } - - if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) - { - if(hhash->HashInCount >= 68) - { - inputaddr = (uint32_t)hhash->pHashInBuffPtr; - /* Write the Input block in the Data IN register */ - for(buffercounter = 0; buffercounter < 64; buffercounter+=4) - { - HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4; - } - if(hhash->HashITCounter == 0) - { - HASH->DIN = *(uint32_t*)inputaddr; - - if(hhash->HashInCount >= 68) - { - /* Decrement buffer counter */ - hhash->HashInCount -= 68; - hhash->pHashInBuffPtr+= 68; - } - else - { - hhash->HashInCount = 0; - hhash->pHashInBuffPtr+= hhash->HashInCount; - } - /* Set Interrupt counter */ - hhash->HashITCounter = 1; - } - else - { - /* Decrement buffer counter */ - hhash->HashInCount -= 64; - hhash->pHashInBuffPtr+= 64; - } - } - else - { - /* Get the buffer address */ - inputaddr = (uint32_t)hhash->pHashInBuffPtr; - /* Get the buffer counter */ - inputcounter = hhash->HashInCount; - /* Disable Interrupts */ - HASH->IMR &= ~(HASH_IT_DINI); - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(inputcounter); - - if((inputcounter > 4) && (inputcounter%4)) - { - inputcounter = (inputcounter+4-inputcounter%4); - } - else if ((inputcounter < 4) && (inputcounter != 0)) - { - inputcounter = 4; - } - - /* Write the Input block in the Data IN register */ - for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++) - { - HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4; - } - /* Start the digest calculation */ - __HAL_HASH_START_DIGEST(); - /* Reset buffer counter */ - hhash->HashInCount = 0; - /* Call Input data transfer complete callback */ - HAL_HASH_InCpltCallback(hhash); - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer. - * The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) -{ - uint32_t inputaddr; - uint32_t outputaddr; - uint32_t buffercounter; - uint32_t inputcounter; - - /* Process Locked */ - __HAL_LOCK(hhash); - - if(hhash->State == HAL_HASH_STATE_READY) - { - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - hhash->HashInCount = Size; - hhash->pHashInBuffPtr = pInBuffer; - hhash->pHashOutBuffPtr = pOutBuffer; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Select the SHA1 mode */ - HASH->CR |= HASH_ALGOSELECTION_SHA1; - /* Reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_CR_INIT; - } - - /* Reset interrupt counter */ - hhash->HashITCounter = 0; - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Enable Interrupts */ - HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI); - - /* Return function status */ - return HAL_OK; - } - if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS)) - { - outputaddr = (uint32_t)hhash->pHashOutBuffPtr; - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]); - outputaddr+=4; - *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]); - outputaddr+=4; - *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]); - outputaddr+=4; - *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]); - outputaddr+=4; - *(uint32_t*)(outputaddr) = __REV(HASH->HR[4]); - if(hhash->HashInCount == 0) - { - /* Disable Interrupts */ - HASH->IMR = 0; - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - /* Call digest computation complete callback */ - HAL_HASH_DgstCpltCallback(hhash); - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; - } - } - if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) - { - if(hhash->HashInCount >= 68) - { - inputaddr = (uint32_t)hhash->pHashInBuffPtr; - /* Write the Input block in the Data IN register */ - for(buffercounter = 0; buffercounter < 64; buffercounter+=4) - { - HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4; - } - if(hhash->HashITCounter == 0) - { - HASH->DIN = *(uint32_t*)inputaddr; - - if(hhash->HashInCount >= 68) - { - /* Decrement buffer counter */ - hhash->HashInCount -= 68; - hhash->pHashInBuffPtr+= 68; - } - else - { - hhash->HashInCount = 0; - hhash->pHashInBuffPtr+= hhash->HashInCount; - } - /* Set Interrupt counter */ - hhash->HashITCounter = 1; - } - else - { - /* Decrement buffer counter */ - hhash->HashInCount -= 64; - hhash->pHashInBuffPtr+= 64; - } - } - else - { - /* Get the buffer address */ - inputaddr = (uint32_t)hhash->pHashInBuffPtr; - /* Get the buffer counter */ - inputcounter = hhash->HashInCount; - /* Disable Interrupts */ - HASH->IMR &= ~(HASH_IT_DINI); - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(inputcounter); - - if((inputcounter > 4) && (inputcounter%4)) - { - inputcounter = (inputcounter+4-inputcounter%4); - } - else if ((inputcounter < 4) && (inputcounter != 0)) - { - inputcounter = 4; - } - /* Write the Input block in the Data IN register */ - for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++) - { - HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4; - } - /* Start the digest calculation */ - __HAL_HASH_START_DIGEST(); - /* Reset buffer counter */ - hhash->HashInCount = 0; - /* Call Input data transfer complete callback */ - HAL_HASH_InCpltCallback(hhash); - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief This function handles HASH interrupt request. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @retval None - */ -void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) -{ - switch(HASH->CR & HASH_CR_ALGO) - { - case HASH_ALGOSELECTION_MD5: - HAL_HASH_MD5_Start_IT(hhash, NULL, 0, NULL); - break; - - case HASH_ALGOSELECTION_SHA1: - HAL_HASH_SHA1_Start_IT(hhash, NULL, 0, NULL); - break; - - default: - break; - } -} - -/** - * @} - */ - -/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions using DMA mode - * @brief processing functions using DMA mode. - * -@verbatim - =============================================================================== - ##### HASH processing using DMA mode functions ##### - =============================================================================== - [..] This section provides functions allowing to calculate in DMA mode - the hash value using one of the following algorithms: - (+) MD5 - (+) SHA1 - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the HASH peripheral in MD5 mode then enables DMA to - control data transfer. Use HAL_HASH_MD5_Finish() to get the digest. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - uint32_t inputaddr = (uint32_t)pInBuffer; - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT; - } - - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* Set the HASH DMA transfer complete callback */ - hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; - /* Set the DMA error callback */ - hhash->hdmain->XferErrorCallback = HASH_DMAError; - - /* Enable the DMA In DMA Stream */ - HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4)); - - /* Enable DMA requests */ - HASH->CR |= (HASH_CR_DMAE); - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Returns the computed digest in MD5 mode - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes. - * @param Timeout: Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change HASH peripheral state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hhash->State = HAL_HASH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - - /* Read the message digest */ - HASH_GetDigest(pOutBuffer, 16); - - /* Change HASH peripheral state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the HASH peripheral in SHA1 mode then enables DMA to - control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - uint32_t inputaddr = (uint32_t)pInBuffer; - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_ALGOSELECTION_SHA1; - HASH->CR |= HASH_CR_INIT; - } - - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* Set the HASH DMA transfer complete callback */ - hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; - /* Set the DMA error callback */ - hhash->hdmain->XferErrorCallback = HASH_DMAError; - - /* Enable the DMA In DMA Stream */ - HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4)); - - /* Enable DMA requests */ - HASH->CR |= (HASH_CR_DMAE); - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Returns the computed digest in SHA1 mode. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. - * @param Timeout: Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change HASH peripheral state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Get tick */ - tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hhash->State = HAL_HASH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - - /* Read the message digest */ - HASH_GetDigest(pOutBuffer, 20); - - /* Change HASH peripheral state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Process UnLock */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - - -/** - * @} - */ - -/** @defgroup HASH_Exported_Functions_Group5 HASH-MAC (HMAC) processing functions using polling mode - * @brief HMAC processing functions using polling mode . - * -@verbatim - =============================================================================== - ##### HMAC processing using polling mode functions ##### - =============================================================================== - [..] This section provides functions allowing to calculate in polling mode - the HMAC value using one of the following algorithms: - (+) MD5 - (+) SHA1 - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the HASH peripheral in HMAC MD5 mode - * then processes pInBuffer. The digest is available in pOutBuffer - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. - * @param Timeout: Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Check if key size is greater than 64 bytes */ - if(hhash->Init.KeySize > 64) - { - /* Select the HMAC MD5 mode */ - HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); - } - else - { - /* Select the HMAC MD5 mode */ - HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT); - } - } - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /************************** STEP 1 ******************************************/ - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - - /* Write input buffer in data register */ - HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize); - - /* Start the digest calculation */ - __HAL_HASH_START_DIGEST(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hhash->State = HAL_HASH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - /************************** STEP 2 ******************************************/ - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - /* Write input buffer in data register */ - HASH_WriteData(pInBuffer, Size); - - /* Start the digest calculation */ - __HAL_HASH_START_DIGEST(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((HAL_GetTick() - tickstart ) > Timeout) - { - /* Change state */ - hhash->State = HAL_HASH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - /************************** STEP 3 ******************************************/ - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - - /* Write input buffer in data register */ - HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize); - - /* Start the digest calculation */ - __HAL_HASH_START_DIGEST(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((HAL_GetTick() - tickstart ) > Timeout) - { - /* Change state */ - hhash->State = HAL_HASH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - - /* Read the message digest */ - HASH_GetDigest(pOutBuffer, 16); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the HASH peripheral in HMAC SHA1 mode - * then processes pInBuffer. The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. - * @param Timeout: Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Check if key size is greater than 64 bytes */ - if(hhash->Init.KeySize > 64) - { - /* Select the HMAC SHA1 mode */ - HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); - } - else - { - /* Select the HMAC SHA1 mode */ - HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT); - } - } - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /************************** STEP 1 ******************************************/ - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - - /* Write input buffer in data register */ - HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize); - - /* Start the digest calculation */ - __HAL_HASH_START_DIGEST(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hhash->State = HAL_HASH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - /************************** STEP 2 ******************************************/ - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - /* Write input buffer in data register */ - HASH_WriteData(pInBuffer, Size); - - /* Start the digest calculation */ - __HAL_HASH_START_DIGEST(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((HAL_GetTick() - tickstart ) > Timeout) - { - /* Change state */ - hhash->State = HAL_HASH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - /************************** STEP 3 ******************************************/ - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - - /* Write input buffer in data register */ - HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize); - - /* Start the digest calculation */ - __HAL_HASH_START_DIGEST(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((HAL_GetTick() - tickstart ) > Timeout) - { - /* Change state */ - hhash->State = HAL_HASH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - /* Read the message digest */ - HASH_GetDigest(pOutBuffer, 20); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup HASH_Exported_Functions_Group6 HASH-MAC (HMAC) processing functions using DMA mode - * @brief HMAC processing functions using DMA mode . - * -@verbatim - =============================================================================== - ##### HMAC processing using DMA mode functions ##### - =============================================================================== - [..] This section provides functions allowing to calculate in DMA mode - the HMAC value using one of the following algorithms: - (+) MD5 - (+) SHA1 - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the HASH peripheral in HMAC MD5 mode - * then enables DMA to control data transfer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - uint32_t inputaddr = 0; - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Save buffer pointer and size in handle */ - hhash->pHashInBuffPtr = pInBuffer; - hhash->HashBuffSize = Size; - hhash->HashInCount = 0; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Check if key size is greater than 64 bytes */ - if(hhash->Init.KeySize > 64) - { - /* Select the HMAC MD5 mode */ - HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); - } - else - { - /* Select the HMAC MD5 mode */ - HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT); - } - } - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - - /* Get the key address */ - inputaddr = (uint32_t)(hhash->Init.pKey); - - /* Set the HASH DMA transfer complete callback */ - hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; - /* Set the DMA error callback */ - hhash->hdmain->XferErrorCallback = HASH_DMAError; - - /* Enable the DMA In DMA Stream */ - HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4)); - /* Enable DMA requests */ - HASH->CR |= (HASH_CR_DMAE); - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the HASH peripheral in HMAC SHA1 mode - * then enables DMA to control data transfer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - uint32_t inputaddr = 0; - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Save buffer pointer and size in handle */ - hhash->pHashInBuffPtr = pInBuffer; - hhash->HashBuffSize = Size; - hhash->HashInCount = 0; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Check if key size is greater than 64 bytes */ - if(hhash->Init.KeySize > 64) - { - /* Select the HMAC SHA1 mode */ - HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); - } - else - { - /* Select the HMAC SHA1 mode */ - HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT); - } - } - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - - /* Get the key address */ - inputaddr = (uint32_t)(hhash->Init.pKey); - - /* Set the HASH DMA transfer complete callback */ - hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; - /* Set the DMA error callback */ - hhash->hdmain->XferErrorCallback = HASH_DMAError; - - /* Enable the DMA In DMA Stream */ - HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4)); - /* Enable DMA requests */ - HASH->CR |= (HASH_CR_DMAE); - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup HASH_Exported_Functions_Group7 Peripheral State functions - * @brief Peripheral State functions. - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief return the HASH state - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @retval HAL state - */ -HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash) -{ - return hhash->State; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_HASH_MODULE_ENABLED */ - -/** - * @} - */ -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c deleted file mode 100644 index 8e14f53..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c +++ /dev/null @@ -1,1636 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_hash_ex.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief HASH HAL Extension module driver. - * This file provides firmware functions to manage the following - * functionalities of HASH peripheral: - * + Extended HASH processing functions based on SHA224 Algorithm - * + Extended HASH processing functions based on SHA256 Algorithm - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The HASH HAL driver can be used as follows: - (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit(): - (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE() - (##) In case of using processing APIs based on interrupts (e.g. HAL_HMACEx_SHA224_Start()) - (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority() - (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ() - (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler() - (##) In case of using DMA to control data transfer (e.g. HAL_HMACEx_SH224_Start_DMA()) - (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE() - (+++) Configure and enable one DMA stream one for managing data transfer from - memory to peripheral (input stream). Managing data transfer from - peripheral to memory can be performed only using CPU - (+++) Associate the initialized DMA handle to the HASH DMA handle - using __HAL_LINKDMA() - (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the DMA Stream: HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() - (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly: - (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit. - (##) For HMAC, the encryption key. - (##) For HMAC, the key size used for encryption. - (#)Three processing functions are available: - (##) Polling mode: processing APIs are blocking functions - i.e. they process the data and wait till the digest computation is finished - e.g. HAL_HASHEx_SHA224_Start() - (##) Interrupt mode: encryption and decryption APIs are not blocking functions - i.e. they process the data under interrupt - e.g. HAL_HASHEx_SHA224_Start_IT() - (##) DMA mode: processing APIs are not blocking functions and the CPU is - not used for data transfer i.e. the data transfer is ensured by DMA - e.g. HAL_HASHEx_SHA224_Start_DMA() - (#)When the processing function is called at first time after HAL_HASH_Init() - the HASH peripheral is initialized and processes the buffer in input. - After that, the digest computation is started. - When processing multi-buffer use the accumulate function to write the - data in the peripheral without starting the digest computation. In last - buffer use the start function to input the last buffer ans start the digest - computation. - (##) e.g. HAL_HASHEx_SHA224_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation - (##) write (n-1)th data buffer in the peripheral without starting the digest computation - (##) HAL_HASHEx_SHA224_Start() : write (n)th data buffer in the peripheral and start the digest computation - (#)In HMAC mode, there is no Accumulate API. Only Start API is available. - (#)In case of using DMA, call the DMA start processing e.g. HAL_HASHEx_SHA224_Start_DMA(). - After that, call the finish function in order to get the digest value - e.g. HAL_HASHEx_SHA224_Finish() - (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -#if defined(STM32F756xx) || defined(STM32F777xx) || defined(STM32F779xx) - -/** @defgroup HASHEx HASHEx - * @brief HASH Extension HAL module driver. - * @{ - */ - -#ifdef HAL_HASH_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup HASHEx_Private_Functions - * @{ - */ -static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma); -static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size); -static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size); -static void HASHEx_DMAError(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** @addtogroup HASHEx_Private_Functions - * @{ - */ - -/** - * @brief Writes the input buffer in data register. - * @param pInBuffer: Pointer to input buffer - * @param Size: The size of input buffer - * @retval None - */ -static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size) -{ - uint32_t buffercounter; - uint32_t inputaddr = (uint32_t) pInBuffer; - - for(buffercounter = 0; buffercounter < Size; buffercounter+=4) - { - HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4; - } -} - -/** - * @brief Provides the message digest result. - * @param pMsgDigest: Pointer to the message digest - * @param Size: The size of the message digest in bytes - * @retval None - */ -static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size) -{ - uint32_t msgdigest = (uint32_t)pMsgDigest; - - switch(Size) - { - case 16: - /* Read the message digest */ - *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - break; - case 20: - /* Read the message digest */ - *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]); - break; - case 28: - /* Read the message digest */ - *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]); - break; - case 32: - /* Read the message digest */ - *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]); - msgdigest+=4; - *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]); - break; - default: - break; - } -} - -/** - * @brief DMA HASH Input Data complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma) -{ - HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - uint32_t inputaddr = 0; - uint32_t buffersize = 0; - - if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE) - { - /* Disable the DMA transfer */ - HASH->CR &= (uint32_t)(~HASH_CR_DMAE); - - /* Change HASH peripheral state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Call Input data transfer complete callback */ - HAL_HASH_InCpltCallback(hhash); - } - else - { - /* Increment Interrupt counter */ - hhash->HashInCount++; - /* Disable the DMA transfer before starting the next transfer */ - HASH->CR &= (uint32_t)(~HASH_CR_DMAE); - - if(hhash->HashInCount <= 2) - { - /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */ - if(hhash->HashInCount == 1) - { - inputaddr = (uint32_t)hhash->pHashInBuffPtr; - buffersize = hhash->HashBuffSize; - } - /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */ - else if(hhash->HashInCount == 2) - { - inputaddr = (uint32_t)hhash->Init.pKey; - buffersize = hhash->Init.KeySize; - } - /* Configure the number of valid bits in last word of the message */ - MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4)); - - /* Set the HASH DMA transfer complete */ - hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt; - - /* Enable the DMA In DMA Stream */ - HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4)); - - /* Enable DMA requests */ - HASH->CR |= (HASH_CR_DMAE); - } - else - { - /* Disable the DMA transfer */ - HASH->CR &= (uint32_t)(~HASH_CR_DMAE); - - /* Reset the InCount */ - hhash->HashInCount = 0; - - /* Change HASH peripheral state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Call Input data transfer complete callback */ - HAL_HASH_InCpltCallback(hhash); - } - } -} - -/** - * @brief DMA HASH communication error callback. - * @param hdma: DMA handle - * @retval None - */ -static void HASHEx_DMAError(DMA_HandleTypeDef *hdma) -{ - HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hhash->State= HAL_HASH_STATE_READY; - HAL_HASH_ErrorCallback(hhash); -} - - /** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup HASHEx_Exported_Functions - * @{ - */ - -/** @defgroup HASHEx_Group1 HASH processing functions - * @brief processing functions using polling mode - * -@verbatim - =============================================================================== - ##### HASH processing using polling mode functions ##### - =============================================================================== - [..] This section provides functions allowing to calculate in polling mode - the hash value using one of the following algorithms: - (+) SHA224 - (+) SHA256 - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the HASH peripheral in SHA224 mode - * then processes pInBuffer. The digest is available in pOutBuffer - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes. - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT; - } - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - /* Write input buffer in data register */ - HASHEx_WriteData(pInBuffer, Size); - - /* Start the digest calculation */ - __HAL_HASH_START_DIGEST(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hhash->State = HAL_HASH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - - /* Read the message digest */ - HASHEx_GetDigest(pOutBuffer, 28); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer. - The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes. - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT; - } - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - /* Write input buffer in data register */ - HASHEx_WriteData(pInBuffer, Size); - - /* Start the digest calculation */ - __HAL_HASH_START_DIGEST(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hhash->State = HAL_HASH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - - /* Read the message digest */ - HASHEx_GetDigest(pOutBuffer, 32); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - - -/** - * @brief Initializes the HASH peripheral in SHA224 mode - * then processes pInBuffer. The digest is available in pOutBuffer - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT; - } - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - /* Write input buffer in data register */ - HASHEx_WriteData(pInBuffer, Size); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - - -/** - * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer. - The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT; - } - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - /* Write input buffer in data register */ - HASHEx_WriteData(pInBuffer, Size); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - - -/** - * @} - */ - -/** @defgroup HASHEx_Group2 HMAC processing functions using polling mode - * @brief HMAC processing functions using polling mode . - * -@verbatim - =============================================================================== - ##### HMAC processing using polling mode functions ##### - =============================================================================== - [..] This section provides functions allowing to calculate in polling mode - the HMAC value using one of the following algorithms: - (+) SHA224 - (+) SHA256 - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the HASH peripheral in HMAC SHA224 mode - * then processes pInBuffer. The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. - * @param Timeout: Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Check if key size is greater than 64 bytes */ - if(hhash->Init.KeySize > 64) - { - /* Select the HMAC SHA224 mode */ - HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); - } - else - { - /* Select the HMAC SHA224 mode */ - HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT); - } - } - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /************************** STEP 1 ******************************************/ - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - - /* Write input buffer in data register */ - HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize); - - /* Start the digest calculation */ - __HAL_HASH_START_DIGEST(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hhash->State = HAL_HASH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - /************************** STEP 2 ******************************************/ - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - /* Write input buffer in data register */ - HASHEx_WriteData(pInBuffer, Size); - - /* Start the digest calculation */ - __HAL_HASH_START_DIGEST(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((HAL_GetTick() - tickstart ) > Timeout) - { - /* Change state */ - hhash->State = HAL_HASH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - /************************** STEP 3 ******************************************/ - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - - /* Write input buffer in data register */ - HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize); - - /* Start the digest calculation */ - __HAL_HASH_START_DIGEST(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((HAL_GetTick() - tickstart ) > Timeout) - { - /* Change state */ - hhash->State = HAL_HASH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - /* Read the message digest */ - HASHEx_GetDigest(pOutBuffer, 28); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the HASH peripheral in HMAC SHA256 mode - * then processes pInBuffer. The digest is available in pOutBuffer - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. - * @param Timeout: Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Check if key size is greater than 64 bytes */ - if(hhash->Init.KeySize > 64) - { - /* Select the HMAC SHA256 mode */ - HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY); - } - else - { - /* Select the HMAC SHA256 mode */ - HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC); - } - /* Reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_CR_INIT; - } - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /************************** STEP 1 ******************************************/ - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - - /* Write input buffer in data register */ - HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize); - - /* Start the digest calculation */ - __HAL_HASH_START_DIGEST(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hhash->State = HAL_HASH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - /************************** STEP 2 ******************************************/ - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - /* Write input buffer in data register */ - HASHEx_WriteData(pInBuffer, Size); - - /* Start the digest calculation */ - __HAL_HASH_START_DIGEST(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((HAL_GetTick() - tickstart ) > Timeout) - { - /* Change state */ - hhash->State = HAL_HASH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - /************************** STEP 3 ******************************************/ - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - - /* Write input buffer in data register */ - HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize); - - /* Start the digest calculation */ - __HAL_HASH_START_DIGEST(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((HAL_GetTick() - tickstart ) > Timeout) - { - /* Change state */ - hhash->State = HAL_HASH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - /* Read the message digest */ - HASHEx_GetDigest(pOutBuffer, 32); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup HASHEx_Group3 HASH processing functions using interrupt mode - * @brief processing functions using interrupt mode. - * -@verbatim - =============================================================================== - ##### HASH processing using interrupt functions ##### - =============================================================================== - [..] This section provides functions allowing to calculate in interrupt mode - the hash value using one of the following algorithms: - (+) SHA224 - (+) SHA256 - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the HASH peripheral in SHA224 mode then processes pInBuffer. - * The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) -{ - uint32_t inputaddr; - uint32_t buffercounter; - uint32_t inputcounter; - - /* Process Locked */ - __HAL_LOCK(hhash); - - if(hhash->State == HAL_HASH_STATE_READY) - { - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - hhash->HashInCount = Size; - hhash->pHashInBuffPtr = pInBuffer; - hhash->pHashOutBuffPtr = pOutBuffer; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Select the SHA224 mode */ - HASH->CR |= HASH_ALGOSELECTION_SHA224; - /* Reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_CR_INIT; - } - /* Reset interrupt counter */ - hhash->HashITCounter = 0; - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Enable Interrupts */ - HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI); - - /* Return function status */ - return HAL_OK; - } - if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS)) - { - /* Read the message digest */ - HASHEx_GetDigest(hhash->pHashOutBuffPtr, 28); - if(hhash->HashInCount == 0) - { - /* Disable Interrupts */ - HASH->IMR = 0; - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - /* Call digest computation complete callback */ - HAL_HASH_DgstCpltCallback(hhash); - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; - } - } - if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) - { - if(hhash->HashInCount >= 68) - { - inputaddr = (uint32_t)hhash->pHashInBuffPtr; - /* Write the Input block in the Data IN register */ - for(buffercounter = 0; buffercounter < 64; buffercounter+=4) - { - HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4; - } - if(hhash->HashITCounter == 0) - { - HASH->DIN = *(uint32_t*)inputaddr; - if(hhash->HashInCount >= 68) - { - /* Decrement buffer counter */ - hhash->HashInCount -= 68; - hhash->pHashInBuffPtr+= 68; - } - else - { - hhash->HashInCount = 0; - hhash->pHashInBuffPtr+= hhash->HashInCount; - } - /* Set Interrupt counter */ - hhash->HashITCounter = 1; - } - else - { - /* Decrement buffer counter */ - hhash->HashInCount -= 64; - hhash->pHashInBuffPtr+= 64; - } - } - else - { - /* Get the buffer address */ - inputaddr = (uint32_t)hhash->pHashInBuffPtr; - /* Get the buffer counter */ - inputcounter = hhash->HashInCount; - /* Disable Interrupts */ - HASH->IMR &= ~(HASH_IT_DINI); - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(inputcounter); - - if((inputcounter > 4) && (inputcounter%4)) - { - inputcounter = (inputcounter+4-inputcounter%4); - } - else if ((inputcounter < 4) && (inputcounter != 0)) - { - inputcounter = 4; - } - /* Write the Input block in the Data IN register */ - for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++) - { - HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4; - } - /* Start the digest calculation */ - __HAL_HASH_START_DIGEST(); - /* Reset buffer counter */ - hhash->HashInCount = 0; - /* Call Input data transfer complete callback */ - HAL_HASH_InCpltCallback(hhash); - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - - -/** - * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer. - * The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) -{ - uint32_t inputaddr; - uint32_t buffercounter; - uint32_t inputcounter; - - /* Process Locked */ - __HAL_LOCK(hhash); - - if(hhash->State == HAL_HASH_STATE_READY) - { - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - hhash->HashInCount = Size; - hhash->pHashInBuffPtr = pInBuffer; - hhash->pHashOutBuffPtr = pOutBuffer; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Select the SHA256 mode */ - HASH->CR |= HASH_ALGOSELECTION_SHA256; - /* Reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_CR_INIT; - } - - /* Reset interrupt counter */ - hhash->HashITCounter = 0; - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Enable Interrupts */ - HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI); - - /* Return function status */ - return HAL_OK; - } - if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS)) - { - /* Read the message digest */ - HASHEx_GetDigest(hhash->pHashOutBuffPtr, 32); - if(hhash->HashInCount == 0) - { - /* Disable Interrupts */ - HASH->IMR = 0; - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - /* Call digest computation complete callback */ - HAL_HASH_DgstCpltCallback(hhash); - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; - } - } - if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) - { - if(hhash->HashInCount >= 68) - { - inputaddr = (uint32_t)hhash->pHashInBuffPtr; - /* Write the Input block in the Data IN register */ - for(buffercounter = 0; buffercounter < 64; buffercounter+=4) - { - HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4; - } - if(hhash->HashITCounter == 0) - { - HASH->DIN = *(uint32_t*)inputaddr; - - if(hhash->HashInCount >= 68) - { - /* Decrement buffer counter */ - hhash->HashInCount -= 68; - hhash->pHashInBuffPtr+= 68; - } - else - { - hhash->HashInCount = 0; - hhash->pHashInBuffPtr+= hhash->HashInCount; - } - /* Set Interrupt counter */ - hhash->HashITCounter = 1; - } - else - { - /* Decrement buffer counter */ - hhash->HashInCount -= 64; - hhash->pHashInBuffPtr+= 64; - } - } - else - { - /* Get the buffer address */ - inputaddr = (uint32_t)hhash->pHashInBuffPtr; - /* Get the buffer counter */ - inputcounter = hhash->HashInCount; - /* Disable Interrupts */ - HASH->IMR &= ~(HASH_IT_DINI); - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(inputcounter); - - if((inputcounter > 4) && (inputcounter%4)) - { - inputcounter = (inputcounter+4-inputcounter%4); - } - else if ((inputcounter < 4) && (inputcounter != 0)) - { - inputcounter = 4; - } - - /* Write the Input block in the Data IN register */ - for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++) - { - HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4; - } - /* Start the digest calculation */ - __HAL_HASH_START_DIGEST(); - /* Reset buffer counter */ - hhash->HashInCount = 0; - /* Call Input data transfer complete callback */ - HAL_HASH_InCpltCallback(hhash); - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief This function handles HASH interrupt request. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @retval None - */ -void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash) -{ - switch(HASH->CR & HASH_CR_ALGO) - { - - case HASH_ALGOSELECTION_SHA224: - HAL_HASHEx_SHA224_Start_IT(hhash, NULL, 0, NULL); - break; - - case HASH_ALGOSELECTION_SHA256: - HAL_HASHEx_SHA256_Start_IT(hhash, NULL, 0, NULL); - break; - - default: - break; - } -} - -/** - * @} - */ - -/** @defgroup HASHEx_Group4 HASH processing functions using DMA mode - * @brief processing functions using DMA mode. - * -@verbatim - =============================================================================== - ##### HASH processing using DMA functions ##### - =============================================================================== - [..] This section provides functions allowing to calculate in DMA mode - the hash value using one of the following algorithms: - (+) SHA224 - (+) SHA256 - -@endverbatim - * @{ - */ - - -/** - * @brief Initializes the HASH peripheral in SHA224 mode then enables DMA to - control data transfer. Use HAL_HASH_SHA224_Finish() to get the digest. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - uint32_t inputaddr = (uint32_t)pInBuffer; - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT; - } - - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* Set the HASH DMA transfer complete callback */ - hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt; - /* Set the DMA error callback */ - hhash->hdmain->XferErrorCallback = HASHEx_DMAError; - - /* Enable the DMA In DMA Stream */ - HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4)); - - /* Enable DMA requests */ - HASH->CR |= (HASH_CR_DMAE); - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Returns the computed digest in SHA224 - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes. - * @param Timeout: Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change HASH peripheral state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hhash->State = HAL_HASH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - - /* Read the message digest */ - HASHEx_GetDigest(pOutBuffer, 28); - - /* Change HASH peripheral state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the HASH peripheral in SHA256 mode then enables DMA to - control data transfer. Use HAL_HASH_SHA256_Finish() to get the digest. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - uint32_t inputaddr = (uint32_t)pInBuffer; - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT; - } - - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* Set the HASH DMA transfer complete callback */ - hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt; - /* Set the DMA error callback */ - hhash->hdmain->XferErrorCallback = HASHEx_DMAError; - - /* Enable the DMA In DMA Stream */ - HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4)); - - /* Enable DMA requests */ - HASH->CR |= (HASH_CR_DMAE); - - /* Process UnLock */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Returns the computed digest in SHA256. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes. - * @param Timeout: Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change HASH peripheral state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hhash->State = HAL_HASH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - - /* Read the message digest */ - HASHEx_GetDigest(pOutBuffer, 32); - - /* Change HASH peripheral state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - - -/** - * @} - */ -/** @defgroup HASHEx_Group5 HMAC processing functions using DMA mode - * @brief HMAC processing functions using DMA mode . - * -@verbatim - =============================================================================== - ##### HMAC processing using DMA functions ##### - =============================================================================== - [..] This section provides functions allowing to calculate in DMA mode - the HMAC value using one of the following algorithms: - (+) SHA224 - (+) SHA256 - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the HASH peripheral in HMAC SHA224 mode - * then enables DMA to control data transfer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - uint32_t inputaddr; - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Save buffer pointer and size in handle */ - hhash->pHashInBuffPtr = pInBuffer; - hhash->HashBuffSize = Size; - hhash->HashInCount = 0; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Check if key size is greater than 64 bytes */ - if(hhash->Init.KeySize > 64) - { - /* Select the HMAC SHA224 mode */ - HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); - } - else - { - /* Select the HMAC SHA224 mode */ - HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT); - } - } - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - - /* Get the key address */ - inputaddr = (uint32_t)(hhash->Init.pKey); - - /* Set the HASH DMA transfer complete callback */ - hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt; - /* Set the DMA error callback */ - hhash->hdmain->XferErrorCallback = HASHEx_DMAError; - - /* Enable the DMA In DMA Stream */ - HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4)); - /* Enable DMA requests */ - HASH->CR |= (HASH_CR_DMAE); - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the HASH peripheral in HMAC SHA256 mode - * then enables DMA to control data transfer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains - * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. - * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - uint32_t inputaddr; - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Save buffer pointer and size in handle */ - hhash->pHashInBuffPtr = pInBuffer; - hhash->HashBuffSize = Size; - hhash->HashInCount = 0; - - /* Check if initialization phase has already been performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Check if key size is greater than 64 bytes */ - if(hhash->Init.KeySize > 64) - { - /* Select the HMAC SHA256 mode */ - HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY); - } - else - { - /* Select the HMAC SHA256 mode */ - HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC); - } - /* Reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_CR_INIT; - } - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - - /* Get the key address */ - inputaddr = (uint32_t)(hhash->Init.pKey); - - /* Set the HASH DMA transfer complete callback */ - hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt; - /* Set the DMA error callback */ - hhash->hdmain->XferErrorCallback = HASHEx_DMAError; - - /* Enable the DMA In DMA Stream */ - HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4)); - /* Enable DMA requests */ - HASH->CR |= (HASH_CR_DMAE); - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ -#endif /* HAL_HASH_MODULE_ENABLED */ - -/** - * @} - */ -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c deleted file mode 100644 index 25f7004..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c +++ /dev/null @@ -1,1229 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_hcd.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief HCD HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#)Declare a HCD_HandleTypeDef handle structure, for example: - HCD_HandleTypeDef hhcd; - - (#)Fill parameters of Init structure in HCD handle - - (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...) - - (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API: - (##) Enable the HCD/USB Low Level interface clock using the following macros - (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); - (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) - (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode) - - (##) Initialize the related GPIO clocks - (##) Configure HCD pin-out - (##) Configure HCD NVIC interrupt - - (#)Associate the Upper USB Host stack to the HAL HCD Driver: - (##) hhcd.pData = phost; - - (#)Enable HCD transmission and reception: - (##) HAL_HCD_Start(); - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup HCD HCD - * @brief HCD HAL module driver - * @{ - */ - -#ifdef HAL_HCD_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function ----------------------------------------------------------*/ -/** @defgroup HCD_Private_Functions HCD Private Functions - * @{ - */ -static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); -static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); -static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd); -static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup HCD_Exported_Functions HCD Exported Functions - * @{ - */ - -/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the host driver. - * @param hhcd: HCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) -{ - /* Check the HCD handle allocation */ - if(hhcd == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); - - hhcd->State = HAL_HCD_STATE_BUSY; - - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - HAL_HCD_MspInit(hhcd); - - /* Disable the Interrupts */ - __HAL_HCD_DISABLE(hhcd); - - /*Init the Core (common init.) */ - USB_CoreInit(hhcd->Instance, hhcd->Init); - - /* Force Host Mode*/ - USB_SetCurrentMode(hhcd->Instance , USB_OTG_HOST_MODE); - - /* Init Host */ - USB_HostInit(hhcd->Instance, hhcd->Init); - - hhcd->State= HAL_HCD_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Initialize a host channel. - * @param hhcd: HCD handle - * @param ch_num: Channel number. - * This parameter can be a value from 1 to 15 - * @param epnum: Endpoint number. - * This parameter can be a value from 1 to 15 - * @param dev_address : Current device address - * This parameter can be a value from 0 to 255 - * @param speed: Current device speed. - * This parameter can be one of these values: - * HCD_SPEED_HIGH: High speed mode, - * HCD_SPEED_FULL: Full speed mode, - * HCD_SPEED_LOW: Low speed mode - * @param ep_type: Endpoint Type. - * This parameter can be one of these values: - * EP_TYPE_CTRL: Control type, - * EP_TYPE_ISOC: Isochronous type, - * EP_TYPE_BULK: Bulk type, - * EP_TYPE_INTR: Interrupt type - * @param mps: Max Packet Size. - * This parameter can be a value from 0 to32K - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps) -{ - HAL_StatusTypeDef status = HAL_OK; - - __HAL_LOCK(hhcd); - - hhcd->hc[ch_num].dev_addr = dev_address; - hhcd->hc[ch_num].max_packet = mps; - hhcd->hc[ch_num].ch_num = ch_num; - hhcd->hc[ch_num].ep_type = ep_type; - hhcd->hc[ch_num].ep_num = epnum & 0x7F; - hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80); - hhcd->hc[ch_num].speed = speed; - - status = USB_HC_Init(hhcd->Instance, - ch_num, - epnum, - dev_address, - speed, - ep_type, - mps); - __HAL_UNLOCK(hhcd); - - return status; -} - -/** - * @brief Halt a host channel. - * @param hhcd: HCD handle - * @param ch_num: Channel number. - * This parameter can be a value from 1 to 15 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) -{ - HAL_StatusTypeDef status = HAL_OK; - - __HAL_LOCK(hhcd); - USB_HC_Halt(hhcd->Instance, ch_num); - __HAL_UNLOCK(hhcd); - - return status; -} - -/** - * @brief DeInitialize the host driver. - * @param hhcd: HCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd) -{ - /* Check the HCD handle allocation */ - if(hhcd == NULL) - { - return HAL_ERROR; - } - - hhcd->State = HAL_HCD_STATE_BUSY; - - /* DeInit the low level hardware */ - HAL_HCD_MspDeInit(hhcd); - - __HAL_HCD_DISABLE(hhcd); - - hhcd->State = HAL_HCD_STATE_RESET; - - return HAL_OK; -} - -/** - * @brief Initialize the HCD MSP. - * @param hhcd: HCD handle - * @retval None - */ -__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_HCD_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize the HCD MSP. - * @param hhcd: HCD handle - * @retval None - */ -__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_HCD_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions - * @brief HCD IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USB Host Data - Transfer - -@endverbatim - * @{ - */ - -/** - * @brief Submit a new URB for processing. - * @param hhcd: HCD handle - * @param ch_num: Channel number. - * This parameter can be a value from 1 to 15 - * @param direction: Channel number. - * This parameter can be one of these values: - * 0 : Output / 1 : Input - * @param ep_type: Endpoint Type. - * This parameter can be one of these values: - * EP_TYPE_CTRL: Control type/ - * EP_TYPE_ISOC: Isochronous type/ - * EP_TYPE_BULK: Bulk type/ - * EP_TYPE_INTR: Interrupt type/ - * @param token: Endpoint Type. - * This parameter can be one of these values: - * 0: HC_PID_SETUP / 1: HC_PID_DATA1 - * @param pbuff: pointer to URB data - * @param length: Length of URB data - * @param do_ping: activate do ping protocol (for high speed only). - * This parameter can be one of these values: - * 0 : do ping inactive / 1 : do ping active - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, - uint8_t ch_num, - uint8_t direction , - uint8_t ep_type, - uint8_t token, - uint8_t* pbuff, - uint16_t length, - uint8_t do_ping) -{ - hhcd->hc[ch_num].ep_is_in = direction; - hhcd->hc[ch_num].ep_type = ep_type; - - if(token == 0) - { - hhcd->hc[ch_num].data_pid = HC_PID_SETUP; - } - else - { - hhcd->hc[ch_num].data_pid = HC_PID_DATA1; - } - - /* Manage Data Toggle */ - switch(ep_type) - { - case EP_TYPE_CTRL: - if((token == 1) && (direction == 0)) /*send data */ - { - if ( length == 0 ) - { /* For Status OUT stage, Length==0, Status Out PID = 1 */ - hhcd->hc[ch_num].toggle_out = 1; - } - - /* Set the Data Toggle bit as per the Flag */ - if ( hhcd->hc[ch_num].toggle_out == 0) - { /* Put the PID 0 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - } - else - { /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ; - } - if(hhcd->hc[ch_num].urb_state != URB_NOTREADY) - { - hhcd->hc[ch_num].do_ping = do_ping; - } - } - break; - - case EP_TYPE_BULK: - if(direction == 0) - { - /* Set the Data Toggle bit as per the Flag */ - if ( hhcd->hc[ch_num].toggle_out == 0) - { /* Put the PID 0 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - } - else - { /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ; - } - if(hhcd->hc[ch_num].urb_state != URB_NOTREADY) - { - hhcd->hc[ch_num].do_ping = do_ping; - } - } - else - { - if( hhcd->hc[ch_num].toggle_in == 0) - { - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - } - else - { - hhcd->hc[ch_num].data_pid = HC_PID_DATA1; - } - } - - break; - case EP_TYPE_INTR: - if(direction == 0) - { - /* Set the Data Toggle bit as per the Flag */ - if ( hhcd->hc[ch_num].toggle_out == 0) - { /* Put the PID 0 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - } - else - { /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ; - } - } - else - { - if( hhcd->hc[ch_num].toggle_in == 0) - { - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - } - else - { - hhcd->hc[ch_num].data_pid = HC_PID_DATA1; - } - } - break; - - case EP_TYPE_ISOC: - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - break; - } - - hhcd->hc[ch_num].xfer_buff = pbuff; - hhcd->hc[ch_num].xfer_len = length; - hhcd->hc[ch_num].urb_state = URB_IDLE; - hhcd->hc[ch_num].xfer_count = 0 ; - hhcd->hc[ch_num].ch_num = ch_num; - hhcd->hc[ch_num].state = HC_IDLE; - - return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]), hhcd->Init.dma_enable); -} - -/** - * @brief Handle HCD interrupt request. - * @param hhcd: HCD handle - * @retval None - */ -void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) -{ - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t i = 0 , interrupt = 0; - - /* ensure that we are in device mode */ - if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST) - { - /* avoid spurious interrupt */ - if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) - { - return; - } - - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) - { - /* incorrect mode, acknowledge the interrupt */ - __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); - } - - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR)) - { - /* incorrect mode, acknowledge the interrupt */ - __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR); - } - - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE)) - { - /* incorrect mode, acknowledge the interrupt */ - __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE); - } - - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS)) - { - /* incorrect mode, acknowledge the interrupt */ - __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS); - } - - /* Handle Host Disconnect Interrupts */ - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT)) - { - - /* Cleanup HPRT */ - USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - /* Handle Host Port Interrupts */ - HAL_HCD_Disconnect_Callback(hhcd); - USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ ); - __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); - } - - /* Handle Host Port Interrupts */ - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT)) - { - HCD_Port_IRQHandler (hhcd); - } - - /* Handle Host SOF Interrupts */ - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF)) - { - HAL_HCD_SOF_Callback(hhcd); - __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF); - } - - /* Handle Host channel Interrupts */ - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) - { - interrupt = USB_HC_ReadInterrupt(hhcd->Instance); - for (i = 0; i < hhcd->Init.Host_channels ; i++) - { - if (interrupt & (1 << i)) - { - if ((USBx_HC(i)->HCCHAR) & USB_OTG_HCCHAR_EPDIR) - { - HCD_HC_IN_IRQHandler (hhcd, i); - } - else - { - HCD_HC_OUT_IRQHandler (hhcd, i); - } - } - } - __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT); - } - - /* Handle Rx Queue Level Interrupts */ - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) - { - USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); - - HCD_RXQLVL_IRQHandler (hhcd); - - USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); - } - } -} - -/** - * @brief SOF callback. - * @param hhcd: HCD handle - * @retval None - */ -__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_HCD_SOF_Callback could be implemented in the user file - */ -} - -/** - * @brief Connection Event callback. - * @param hhcd: HCD handle - * @retval None - */ -__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_HCD_Connect_Callback could be implemented in the user file - */ -} - -/** - * @brief Disconnection Event callback. - * @param hhcd: HCD handle - * @retval None - */ -__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_HCD_Disconnect_Callback could be implemented in the user file - */ -} - -/** - * @brief Notify URB state change callback. - * @param hhcd: HCD handle - * @param chnum: Channel number. - * This parameter can be a value from 1 to 15 - * @param urb_state: - * This parameter can be one of these values: - * URB_IDLE/ - * URB_DONE/ - * URB_NOTREADY/ - * URB_NYET/ - * URB_ERROR/ - * URB_STALL/ - * @retval None - */ -__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions - * @brief Management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the HCD data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Start the host driver. - * @param hhcd: HCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) -{ - __HAL_LOCK(hhcd); - __HAL_HCD_ENABLE(hhcd); - USB_DriveVbus(hhcd->Instance, 1); - __HAL_UNLOCK(hhcd); - return HAL_OK; -} - -/** - * @brief Stop the host driver. - * @param hhcd: HCD handle - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) -{ - __HAL_LOCK(hhcd); - USB_StopHost(hhcd->Instance); - __HAL_UNLOCK(hhcd); - return HAL_OK; -} - -/** - * @brief Reset the host port. - * @param hhcd: HCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) -{ - return (USB_ResetPort(hhcd->Instance)); -} - -/** - * @} - */ - -/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the HCD handle state. - * @param hhcd: HCD handle - * @retval HAL state - */ -HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd) -{ - return hhcd->State; -} - -/** - * @brief Return URB state for a channel. - * @param hhcd: HCD handle - * @param chnum: Channel number. - * This parameter can be a value from 1 to 15 - * @retval URB state. - * This parameter can be one of these values: - * URB_IDLE/ - * URB_DONE/ - * URB_NOTREADY/ - * URB_NYET/ - * URB_ERROR/ - * URB_STALL - */ -HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum) -{ - return hhcd->hc[chnum].urb_state; -} - - -/** - * @brief Return the last host transfer size. - * @param hhcd: HCD handle - * @param chnum: Channel number. - * This parameter can be a value from 1 to 15 - * @retval last transfer size in byte - */ -uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum) -{ - return hhcd->hc[chnum].xfer_count; -} - -/** - * @brief Return the Host Channel state. - * @param hhcd: HCD handle - * @param chnum: Channel number. - * This parameter can be a value from 1 to 15 - * @retval Host channel state - * This parameter can be one of these values: - * HC_IDLE/ - * HC_XFRC/ - * HC_HALTED/ - * HC_NYET/ - * HC_NAK/ - * HC_STALL/ - * HC_XACTERR/ - * HC_BBLERR/ - * HC_DATATGLERR - */ -HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum) -{ - return hhcd->hc[chnum].state; -} - -/** - * @brief Return the current Host frame number. - * @param hhcd: HCD handle - * @retval Current Host frame number - */ -uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) -{ - return (USB_GetCurrentFrame(hhcd->Instance)); -} - -/** - * @brief Return the Host enumeration speed. - * @param hhcd: HCD handle - * @retval Enumeration speed - */ -uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) -{ - return (USB_GetHostSpeed(hhcd->Instance)); -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup HCD_Private_Functions - * @{ - */ -/** - * @brief Handle Host Channel IN interrupt requests. - * @param hhcd: HCD handle - * @param chnum: Channel number. - * This parameter can be a value from 1 to 15 - * @retval none - */ -static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) -{ - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t tmpreg = 0; - - if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR) - { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK) - { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); - } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL) - { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - hhcd->hc[chnum].state = HC_STALL; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); - USB_HC_Halt(hhcd->Instance, chnum); - } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR) - { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - hhcd->hc[chnum].state = HC_DATATGLERR; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); - } - - if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR) - { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); - } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC) - { - - if (hhcd->Init.dma_enable) - { - hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \ - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); - } - - hhcd->hc[chnum].state = HC_XFRC; - hhcd->hc[chnum].ErrCnt = 0; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); - - - if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)|| - (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) - { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - - } - else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR) - { - USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; - hhcd->hc[chnum].urb_state = URB_DONE; - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); - } - hhcd->hc[chnum].toggle_in ^= 1; - - } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH) - { - __HAL_HCD_MASK_HALT_HC_INT(chnum); - - if(hhcd->hc[chnum].state == HC_XFRC) - { - hhcd->hc[chnum].urb_state = URB_DONE; - } - - else if (hhcd->hc[chnum].state == HC_STALL) - { - hhcd->hc[chnum].urb_state = URB_STALL; - } - - else if((hhcd->hc[chnum].state == HC_XACTERR) || - (hhcd->hc[chnum].state == HC_DATATGLERR)) - { - if(hhcd->hc[chnum].ErrCnt++ > 3) - { - hhcd->hc[chnum].ErrCnt = 0; - hhcd->hc[chnum].urb_state = URB_ERROR; - } - else - { - hhcd->hc[chnum].urb_state = URB_NOTREADY; - } - - /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; - } - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); - } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR) - { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - hhcd->hc[chnum].ErrCnt++; - hhcd->hc[chnum].state = HC_XACTERR; - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); - } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK) - { - if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR) - { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - } - else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)|| - (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) - { - /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; - } - hhcd->hc[chnum].state = HC_NAK; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - } -} - -/** - * @brief Handle Host Channel OUT interrupt requests. - * @param hhcd: HCD handle - * @param chnum: Channel number. - * This parameter can be a value from 1 to 15 - * @retval none - */ -static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) -{ - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t tmpreg = 0; - - if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR) - { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK) - { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); - - if( hhcd->hc[chnum].do_ping == 1) - { - hhcd->hc[chnum].state = HC_NYET; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - hhcd->hc[chnum].urb_state = URB_NOTREADY; - } - } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NYET) - { - hhcd->hc[chnum].state = HC_NYET; - hhcd->hc[chnum].ErrCnt= 0; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); - - } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR) - { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); - } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC) - { - hhcd->hc[chnum].ErrCnt = 0; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); - hhcd->hc[chnum].state = HC_XFRC; - - } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL) - { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - hhcd->hc[chnum].state = HC_STALL; - } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK) - { - hhcd->hc[chnum].ErrCnt = 0; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - hhcd->hc[chnum].state = HC_NAK; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR) - { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - hhcd->hc[chnum].state = HC_XACTERR; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); - } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR) - { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); - hhcd->hc[chnum].state = HC_DATATGLERR; - } - - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH) - { - __HAL_HCD_MASK_HALT_HC_INT(chnum); - - if(hhcd->hc[chnum].state == HC_XFRC) - { - hhcd->hc[chnum].urb_state = URB_DONE; - if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK) - { - hhcd->hc[chnum].toggle_out ^= 1; - } - } - else if (hhcd->hc[chnum].state == HC_NAK) - { - hhcd->hc[chnum].urb_state = URB_NOTREADY; - } - - else if (hhcd->hc[chnum].state == HC_NYET) - { - hhcd->hc[chnum].urb_state = URB_NOTREADY; - hhcd->hc[chnum].do_ping = 0; - } - - else if (hhcd->hc[chnum].state == HC_STALL) - { - hhcd->hc[chnum].urb_state = URB_STALL; - } - - else if((hhcd->hc[chnum].state == HC_XACTERR) || - (hhcd->hc[chnum].state == HC_DATATGLERR)) - { - if(hhcd->hc[chnum].ErrCnt++ > 3) - { - hhcd->hc[chnum].ErrCnt = 0; - hhcd->hc[chnum].urb_state = URB_ERROR; - } - else - { - hhcd->hc[chnum].urb_state = URB_NOTREADY; - } - - /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; - } - - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); - } -} - -/** - * @brief Handle Rx Queue Level interrupt requests. - * @param hhcd: HCD handle - * @retval none - */ -static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd) -{ - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint8_t channelnum =0; - uint32_t pktsts; - uint32_t pktcnt; - uint32_t temp = 0; - uint32_t tmpreg = 0; - - temp = hhcd->Instance->GRXSTSP ; - channelnum = temp & USB_OTG_GRXSTSP_EPNUM; - pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17; - pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - - switch (pktsts) - { - case GRXSTS_PKTSTS_IN: - /* Read the data into the host buffer. */ - if ((pktcnt > 0) && (hhcd->hc[channelnum].xfer_buff != (void *)0)) - { - - USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt); - - /*manage multiple Xfer */ - hhcd->hc[channelnum].xfer_buff += pktcnt; - hhcd->hc[channelnum].xfer_count += pktcnt; - - if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0) - { - /* re-activate the channel when more packets are expected */ - tmpreg = USBx_HC(channelnum)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(channelnum)->HCCHAR = tmpreg; - hhcd->hc[channelnum].toggle_in ^= 1; - } - } - break; - - case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: - break; - case GRXSTS_PKTSTS_IN_XFER_COMP: - case GRXSTS_PKTSTS_CH_HALTED: - default: - break; - } -} - -/** - * @brief Handle Host Port interrupt requests. - * @param hhcd: HCD handle - * @retval None - */ -static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) -{ - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - __IO uint32_t hprt0, hprt0_dup; - - /* Handle Host Port Interrupts */ - hprt0 = USBx_HPRT0; - hprt0_dup = USBx_HPRT0; - - hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - /* Check whether Port Connect detected */ - if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET) - { - if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS) - { - USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); - HAL_HCD_Connect_Callback(hhcd); - } - hprt0_dup |= USB_OTG_HPRT_PCDET; - - } - - /* Check whether Port Enable Changed */ - if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG) - { - hprt0_dup |= USB_OTG_HPRT_PENCHNG; - - if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) - { - if(hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) - { - if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) - { - USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ ); - } - else - { - USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ ); - } - } - else - { - if(hhcd->Init.speed == HCD_SPEED_FULL) - { - USBx_HOST->HFIR = (uint32_t)60000; - } - } - HAL_HCD_Connect_Callback(hhcd); - - } - else - { - /* Cleanup HPRT */ - USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); - } - } - - /* Check For an overcurrent */ - if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG) - { - hprt0_dup |= USB_OTG_HPRT_POCCHNG; - } - - /* Clear Port Interrupts */ - USBx_HPRT0 = hprt0_dup; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_HCD_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c deleted file mode 100644 index 789c3ca..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c +++ /dev/null @@ -1,4758 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_i2c.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief I2C HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Inter Integrated Circuit (I2C) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and Errors functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The I2C HAL driver can be used as follows: - - (#) Declare a I2C_HandleTypeDef handle structure, for example: - I2C_HandleTypeDef hi2c; - - (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: - (##) Enable the I2Cx interface clock - (##) I2C pins configuration - (+++) Enable the clock for the I2C GPIOs - (+++) Configure I2C pins as alternate function open-drain - (##) NVIC configuration if you need to use interrupt process - (+++) Configure the I2Cx interrupt priority - (+++) Enable the NVIC I2C IRQ Channel - (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream - (+++) Enable the DMAx interface clock using - (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx stream - (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on - the DMA Tx or Rx stream - - (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, - Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. - - (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. - - (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() - - (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() - (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() - (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() - (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() - - *** Polling mode IO MEM operation *** - ===================================== - [..] - (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() - (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() - - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() - (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. - This action will inform Master to generate a Stop condition to discard the communication. - - - *** Interrupt mode IO sequential operation *** - =================================== - [..] - (@) These interfaces allow to manage a sequential transfer with a repeated start condition - when a direction change during transfer - [..] - (+) A specific option field manage the different steps of a sequential transfer - (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: - (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode - (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address - and data to transfer without a final stop condition - (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer - if no direction change and without a final stop condition in both cases - (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer - if no direction change and with a final stop condition in both cases - - (+) Differents sequential I2C interfaces are listed below: - (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() - (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() - (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (+++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit - (+++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive - (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() - (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can - add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). - (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() - (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() - (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() - (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. - This action will inform Master to generate a Stop condition to discard the communication. - - *** Interrupt mode IO MEM operation *** - ======================================= - [..] - (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using - HAL_I2C_Mem_Write_IT() - (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() - (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using - HAL_I2C_Mem_Read_IT() - (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - - *** DMA mode IO operation *** - ============================== - [..] - (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() - (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. - This action will inform Master to generate a Stop condition to discard the communication. - - *** DMA mode IO MEM operation *** - ================================= - [..] - (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using - HAL_I2C_Mem_Write_DMA() - (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() - (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using - HAL_I2C_Mem_Read_DMA() - (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - - - *** I2C HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in I2C HAL driver. - - (+) __HAL_I2C_ENABLE: Enable the I2C peripheral - (+) __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode - (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not - (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag - (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt - (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt - - [..] - (@) You can refer to the I2C HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup I2C I2C - * @brief I2C HAL module driver - * @{ - */ - -#ifdef HAL_I2C_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup I2C_Private_Define I2C Private Define - * @{ - */ -#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ -#define I2C_TIMEOUT_ADDR ((uint32_t)10000U) /*!< 10 s */ -#define I2C_TIMEOUT_BUSY ((uint32_t)25U) /*!< 25 ms */ -#define I2C_TIMEOUT_DIR ((uint32_t)25U) /*!< 25 ms */ -#define I2C_TIMEOUT_RXNE ((uint32_t)25U) /*!< 25 ms */ -#define I2C_TIMEOUT_STOPF ((uint32_t)25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TC ((uint32_t)25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TCR ((uint32_t)25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TXIS ((uint32_t)25U) /*!< 25 ms */ -#define I2C_TIMEOUT_FLAG ((uint32_t)25U) /*!< 25 ms */ - -#define MAX_NBYTE_SIZE 255U -#define SlaveAddr_SHIFT 7U -#define SlaveAddr_MSK 0x06U - -/* Private define for @ref PreviousState usage */ -#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ -#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ -#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ - - -/* Private define to centralize the enable/disable of Interrupts */ -#define I2C_XFER_TX_IT ((uint32_t)0x00000001) -#define I2C_XFER_RX_IT ((uint32_t)0x00000002) -#define I2C_XFER_LISTEN_IT ((uint32_t)0x00000004) - -#define I2C_XFER_ERROR_IT ((uint32_t)0x00000011) -#define I2C_XFER_CPLT_IT ((uint32_t)0x00000012) -#define I2C_XFER_RELOAD_IT ((uint32_t)0x00000012) -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \ - ((uint32_t)((__HANDLE__)->hdmatx->Instance->NDTR)) : \ - ((uint32_t)((__HANDLE__)->hdmarx->Instance->NDTR))) - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/** @defgroup I2C_Private_Functions I2C Private Functions - * @{ - */ -/* Private functions to handle DMA transfer */ -static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAError(DMA_HandleTypeDef *hdma); -static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); - -/* Private functions to handle IT transfer */ -static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c); -static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c); -static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); - -/* Private functions to handle IT transfer */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); - -/* Private functions for I2C transfer IRQ handler */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); - -/* Private functions to handle flags during polling transfer */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); - -/* Private functions to centralize the enable/disable of Interrupts */ -static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); -static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); - -/* Private functions to flush TXDR register */ -static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); - -/* Private functions to handle start, restart or stop a transfer */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Functions I2C Exported Functions - * @{ - */ - -/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - deinitialize the I2Cx peripheral: - - (+) User must Implement HAL_I2C_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - - (+) Call the function HAL_I2C_Init() to configure the selected device with - the selected configuration: - (++) Clock Timing - (++) Own Address 1 - (++) Addressing mode (Master, Slave) - (++) Dual Addressing mode - (++) Own Address 2 - (++) Own Address 2 Mask - (++) General call mode - (++) Nostretch mode - - (+) Call the function HAL_I2C_DeInit() to restore the default configuration - of the selected I2Cx peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the I2C according to the specified parameters - * in the I2C_InitTypeDef and initialize the associated handle. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) -{ - /* Check the I2C handle allocation */ - if(hi2c == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); - assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); - assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); - assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); - assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); - assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); - assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); - - if(hi2c->State == HAL_I2C_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hi2c->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ - HAL_I2C_MspInit(hi2c); - } - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ - /* Configure I2Cx: Frequency range */ - hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; - - /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ - /* Configure I2Cx: Own Address1 and ack own address1 mode */ - hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; - if(hi2c->Init.OwnAddress1 != 0) - { - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) - { - hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); - } - else /* I2C_ADDRESSINGMODE_10BIT */ - { - hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); - } - } - - /*---------------------------- I2Cx CR2 Configuration ----------------------*/ - /* Configure I2Cx: Addressing Master mode */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - hi2c->Instance->CR2 = (I2C_CR2_ADD10); - } - /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ - hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); - - /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ - /* Configure I2Cx: Dual mode and Own Address2 */ - hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); - - /*---------------------------- I2Cx CR1 Configuration ----------------------*/ - /* Configure I2Cx: Generalcall and NoStretch mode */ - hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); - - /* Enable the selected I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - - return HAL_OK; -} - -/** - * @brief DeInitialize the I2C peripheral. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) -{ - /* Check the I2C handle allocation */ - if(hi2c == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the I2C Peripheral Clock */ - __HAL_I2C_DISABLE(hi2c); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_I2C_MspDeInit(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_RESET; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Release Lock */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Initialize the I2C MSP. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize the I2C MSP. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the I2C data - transfers. - - (#) There are two modes of transfer: - (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts - or DMA. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the - dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - - (#) Blocking mode functions are : - (++) HAL_I2C_Master_Transmit() - (++) HAL_I2C_Master_Receive() - (++) HAL_I2C_Slave_Transmit() - (++) HAL_I2C_Slave_Receive() - (++) HAL_I2C_Mem_Write() - (++) HAL_I2C_Mem_Read() - (++) HAL_I2C_IsDeviceReady() - - (#) No-Blocking mode functions with Interrupt are : - (++) HAL_I2C_Master_Transmit_IT() - (++) HAL_I2C_Master_Receive_IT() - (++) HAL_I2C_Slave_Transmit_IT() - (++) HAL_I2C_Slave_Receive_IT() - (++) HAL_I2C_Mem_Write_IT() - (++) HAL_I2C_Mem_Read_IT() - - (#) No-Blocking mode functions with DMA are : - (++) HAL_I2C_Master_Transmit_DMA() - (++) HAL_I2C_Master_Receive_DMA() - (++) HAL_I2C_Slave_Transmit_DMA() - (++) HAL_I2C_Slave_Receive_DMA() - (++) HAL_I2C_Mem_Write_DMA() - (++) HAL_I2C_Mem_Read_DMA() - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_I2C_MemTxCpltCallback() - (++) HAL_I2C_MemRxCpltCallback() - (++) HAL_I2C_MasterTxCpltCallback() - (++) HAL_I2C_MasterRxCpltCallback() - (++) HAL_I2C_SlaveTxCpltCallback() - (++) HAL_I2C_SlaveRxCpltCallback() - (++) HAL_I2C_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Transmits in master mode an amount of data in blocking mode. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); - } - - while(hi2c->XferSize > 0) - { - /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - hi2c->XferSize--; - - if((hi2c->XferSize == 0) && (hi2c->XferCount!=0)) - { - /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - } - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives in master mode an amount of data in blocking mode. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - } - - while(hi2c->XferSize > 0) - { - /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - - if((hi2c->XferSize == 0) && (hi2c->XferCount != 0)) - { - /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - } - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmits in slave mode an amount of data in blocking mode. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); - - /* If 10bit addressing mode is selected */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); - } - - /* Wait until DIR flag is set Transmitter mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - while(hi2c->XferCount > 0) - { - /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - } - - /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Normal use case for Transmitter mode */ - /* A NACK is generated to confirm the end of transfer */ - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in blocking mode - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); - - /* Wait until DIR flag is reset Receiver mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - while(hi2c->XferCount > 0) - { - /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Store Last receive data if any */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferCount--; - } - - if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) - { - return HAL_TIMEOUT; - } - else - { - return HAL_ERROR; - } - } - - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferCount--; - } - - /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - uint32_t xfermode = 0; - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - uint32_t xfermode = 0; - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_IT; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_IT; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in master mode an amount of data in non-blocking mode with DMA - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - uint32_t xfermode = 0; - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in master mode an amount of data in non-blocking mode with DMA - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - uint32_t xfermode = 0; - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - if(hi2c->XferSize > 0) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - } - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_DMA; - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in non-blocking mode with DMA - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_DMA; - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @brief Write an amount of data in blocking mode to a specific memory address - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - - do - { - /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - hi2c->XferSize--; - - if((hi2c->XferSize == 0) && (hi2c->XferCount!=0)) - { - /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - - }while(hi2c->XferCount > 0); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Read an amount of data in blocking mode from a specific memory address - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - } - - do - { - /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - - if((hi2c->XferSize == 0) && (hi2c->XferCount != 0)) - { - /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - }while(hi2c->XferCount > 0); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0; - uint32_t xfermode = 0; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0; - uint32_t xfermode = 0; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0; - uint32_t xfermode = 0; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be read - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0; - uint32_t xfermode = 0; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Checks if target device is ready for communication. - * @note This function is used with Memory devices - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param Trials: Number of trials - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - __IO uint32_t I2C_Trials = 0; - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - do - { - /* Generate Start */ - hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set or a NACK flag is set*/ - tickstart = HAL_GetTick(); - while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - } - - /* Check if the NACKF flag has not been set */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) - { - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - - /* Check if the maximum allowed number of trials has been reached */ - if (I2C_Trials++ == Trials) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - }while(I2C_Trials < Trials); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - uint32_t xfermode = 0; - uint32_t xferrequest = I2C_GENERATE_START_WRITE; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Master_ISR_IT; - - /* If size > MAX_NBYTE_SIZE, use reload mode */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = hi2c->XferOptions; - - /* If transfer direction not change, do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - if(hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_TX) - { - xferrequest = I2C_NO_STARTSTOP; - } - } - - /* Send Slave Address and set NBYTES to write */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - uint32_t xfermode = 0; - uint32_t xferrequest = I2C_GENERATE_START_READ; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Master_ISR_IT; - - /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = hi2c->XferOptions; - - /* If transfer direction not change, do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) - { - xferrequest = I2C_NO_STARTSTOP; - } - } - - /* Send Slave Address and set NBYTES to read */ - I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if(hi2c->State == HAL_I2C_STATE_LISTEN) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Slave_ISR_IT; - - if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) - { - /* Clear ADDR flag after prepare the transfer parameters */ - /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* REnable ADDR interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if(hi2c->State == HAL_I2C_STATE_LISTEN) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Slave_ISR_IT; - - if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) - { - /* Clear ADDR flag after prepare the transfer parameters */ - /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* REnable ADDR interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Enable the Address listen mode with Interrupt. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) -{ - if(hi2c->State == HAL_I2C_STATE_READY) - { - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->XferISR = I2C_Slave_ISR_IT; - - /* Enable the Address Match interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Disable the Address listen mode with Interrupt. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) -{ - /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp; - - /* Disable Address listen mode only if a transfer is not ongoing */ - if(hi2c->State == HAL_I2C_STATE_LISTEN) - { - tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; - hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferISR = NULL; - - /* Disable the Address Match interrupt */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Abort a master I2C IT or DMA process communication with Interrupt. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) -{ - if(hi2c->Mode == HAL_I2C_MODE_MASTER) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Set State at HAL_I2C_STATE_ABORT */ - hi2c->State = HAL_I2C_STATE_ABORT; - - /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ - /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ - I2C_TransferConfig(hi2c, 0, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - - return HAL_OK; - } - else - { - /* Wrong usage of abort function */ - /* This function should be used only in case of abort monitored by master device */ - return HAL_ERROR; - } -} - -/** - * @} - */ - -/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ - -/** - * @brief This function handles I2C event interrupt request. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) -{ - /* Get current IT Flags and IT sources value */ - uint32_t itflags = READ_REG(hi2c->Instance->ISR); - uint32_t itsources = READ_REG(hi2c->Instance->CR1); - - /* I2C events treatment -------------------------------------*/ - if(hi2c->XferISR != NULL) - { - hi2c->XferISR(hi2c, itflags, itsources); - } -} - -/** - * @brief This function handles I2C error interrupt request. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) -{ - uint32_t itflags = READ_REG(hi2c->Instance->ISR); - uint32_t itsources = READ_REG(hi2c->Instance->CR1); - - /* I2C Bus error interrupt occurred ------------------------------------*/ - if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; - - /* Clear BERR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); - } - - /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; - - /* Clear OVR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); - } - - /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; - - /* Clear ARLO flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); - } - - /* Call the Error Callback in case of Error detected */ - if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) - { - I2C_ITError(hi2c, hi2c->ErrorCode); - } -} - -/** - * @brief Master Tx Transfer completed callback. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MasterTxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Master Rx Transfer completed callback. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MasterRxCpltCallback could be implemented in the user file - */ -} - -/** @brief Slave Tx Transfer completed callback. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Slave Rx Transfer completed callback. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Slave Address Match callback. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFEROPTIONS - * @param AddrMatchCode: Address Match Code - * @retval None - */ -__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - UNUSED(TransferDirection); - UNUSED(AddrMatchCode); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_AddrCallback() could be implemented in the user file - */ -} - -/** - * @brief Listen Complete callback. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_ListenCpltCallback() could be implemented in the user file - */ -} - -/** - * @brief Memory Tx Transfer completed callback. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MemTxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Memory Rx Transfer completed callback. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MemRxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief I2C error callback. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief I2C abort callback. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_AbortCpltCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions - * @brief Peripheral State, Mode and Error functions - * -@verbatim - =============================================================================== - ##### Peripheral State, Mode and Error functions ##### - =============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the I2C handle state. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL state - */ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) -{ - /* Return I2C handle state */ - return hi2c->State; -} - -/** - * @brief Returns the I2C Master, Slave, Memory or no mode. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL mode - */ -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) -{ - return hi2c->Mode; -} - -/** -* @brief Return the I2C error code. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. -* @retval I2C Error Code -*/ -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) -{ - return hi2c->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup I2C_Private_Functions - * @{ - */ - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags: Interrupt flags to handle. - * @param ITSources: Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) -{ - uint16_t devaddress = 0; - - /* Process Locked */ - __HAL_LOCK(hi2c); - - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set corresponding Error Code */ - /* No need to generate STOP, it is automatically done */ - /* Error callback will be send during stop flag treatment */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - } - else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - } - else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) - { - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferSize--; - hi2c->XferCount--; - } - else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) - { - if((hi2c->XferSize == 0) && (hi2c->XferCount != 0)) - { - devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - if(hi2c->XferOptions != I2C_NO_OPTION_FRAME) - { - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - } - else - { - /* Call TxCpltCallback() if no stop mode is set */ - if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER)) - { - /* Call I2C Master Sequential complete process */ - I2C_ITMasterSequentialCplt(hi2c); - } - else - { - /* Wrong size Status regarding TCR flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - } - else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) - { - if(hi2c->XferCount == 0) - { - if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER)) - { - /* Call I2C Master Sequential complete process */ - I2C_ITMasterSequentialCplt(hi2c); - } - } - else - { - /* Wrong size Status regarding TC flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - - if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) - { - /* Call I2C Master complete process */ - I2C_ITMasterCplt(hi2c, ITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags: Interrupt flags to handle. - * @param ITSources: Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) -{ - /* Process locked */ - __HAL_LOCK(hi2c); - - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) - { - /* Check that I2C transfer finished */ - /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0*/ - /* So clear Flag NACKF only */ - if(hi2c->XferCount == 0) - { - if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ - (hi2c->State == HAL_I2C_STATE_LISTEN)) - { - /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, ITFlags); - } - else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Last Byte is Transmitted */ - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSequentialCplt(hi2c); - } - else - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - } - else - { - /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) - { - if(hi2c->XferCount > 0) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - } - - if((hi2c->XferCount == 0) && \ - (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) - { - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSequentialCplt(hi2c); - } - } - else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) - { - I2C_ITAddrCplt(hi2c, ITFlags); - } - else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) - { - /* Write data to TXDR only if XferCount not reach "0" */ - /* A TXIS flag can be set, during STOP treatment */ - /* Check if all Datas have already been sent */ - /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if(hi2c->XferCount > 0) - { - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - hi2c->XferSize--; - } - else - { - if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) - { - /* Last Byte is Transmitted */ - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSequentialCplt(hi2c); - } - } - } - - /* Check if STOPF is set */ - if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, ITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags: Interrupt flags to handle. - * @param ITSources: Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) -{ - uint16_t devaddress = 0; - uint32_t xfermode = 0; - - /* Process Locked */ - __HAL_LOCK(hi2c); - - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set corresponding Error Code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* No need to generate STOP, it is automatically done */ - /* But enable STOP interrupt, to treat it */ - /* Error callback will be send during stop flag treatment */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - } - else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) - { - /* Disable TC interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); - - if(hi2c->XferCount != 0) - { - /* Recover Slave address */ - devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - /* Prepare the new XferSize to transfer */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Set the new XferSize in Nbytes register */ - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Enable DMA Request */ - if(hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - } - else - { - /* Wrong size Status regarding TCR flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) - { - /* Call I2C Master complete process */ - I2C_ITMasterCplt(hi2c, ITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags: Interrupt flags to handle. - * @param ITSources: Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) -{ - /* Process locked */ - __HAL_LOCK(hi2c); - - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) - { - /* Check that I2C transfer finished */ - /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0 */ - /* So clear Flag NACKF only */ - if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - else - { - /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, ITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Master sends target device address followed by internal memory address for write request. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param Timeout: Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) -{ - I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - - /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* If Memory address size is 8Bit */ - if(MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Send Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - /* If Memory address size is 16Bit */ - else - { - /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - - /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - -return HAL_OK; -} - -/** - * @brief Master sends target device address followed by internal memory address for read request. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param Timeout: Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) -{ - I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); - - /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* If Memory address size is 8Bit */ - if(MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Send Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - /* If Memory address size is 16Bit */ - else - { - /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - - /* Wait until TC flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - return HAL_OK; -} - -/** - * @brief I2C Address complete process callback. - * @param hi2c: I2C handle. - * @param ITFlags: Interrupt flags to handle. - * @retval None - */ -static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - uint8_t transferdirection = 0; - uint16_t slaveaddrcode = 0; - uint16_t ownadd1code = 0; - uint16_t ownadd2code = 0; - - /* In case of Listen state, need to inform upper layer of address match code event */ - if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) - { - transferdirection = I2C_GET_DIR(hi2c); - slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); - ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); - ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); - - /* If 10bits addressing mode is selected */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) - { - slaveaddrcode = ownadd1code; - hi2c->AddrEventCount++; - if(hi2c->AddrEventCount == 2) - { - /* Reset Address Event counter */ - hi2c->AddrEventCount = 0; - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call Slave Addr callback */ - HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); - } - } - else - { - slaveaddrcode = ownadd2code; - - /* Disable ADDR Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call Slave Addr callback */ - HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); - } - } - /* else 7 bits addressing mode is selected */ - else - { - /* Disable ADDR Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call Slave Addr callback */ - HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); - } - } - /* Else clear address flag only */ - else - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - } -} - -/** - * @brief I2C Master sequential complete process. - * @param hi2c: I2C handle. - * @retval None - */ -static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) -{ - /* Reset I2C handle mode */ - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* No Generate Stop, to permit restart mode */ - /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ - if (hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; - hi2c->XferISR = NULL; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_MasterTxCpltCallback(hi2c); - } - /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ - else - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; - hi2c->XferISR = NULL; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_MasterRxCpltCallback(hi2c); - } -} - -/** - * @brief I2C Slave sequential complete process. - * @param hi2c: I2C handle. - * @retval None - */ -static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) -{ - /* Reset I2C handle mode */ - hi2c->Mode = HAL_I2C_MODE_NONE; - - if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) - { - /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Tx complete callback to inform upper layer of the end of transmit process */ - HAL_I2C_SlaveTxCpltCallback(hi2c); - } - - else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) - { - /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Rx complete callback to inform upper layer of the end of receive process */ - HAL_I2C_SlaveRxCpltCallback(hi2c); - } -} - -/** - * @brief I2C Master complete process. - * @param hi2c: I2C handle. - * @param ITFlags: Interrupt flags to handle. - * @retval None - */ -static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Reset handle parameters */ - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->XferISR = NULL; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - - if((ITFlags & I2C_FLAG_AF) != RESET) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set acknowledge error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, hi2c->ErrorCode); - } - /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ - else if(hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - hi2c->State = HAL_I2C_STATE_READY; - - if (hi2c->Mode == HAL_I2C_MODE_MEM) - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_MemTxCpltCallback(hi2c); - } - else - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_MasterTxCpltCallback(hi2c); - } - } - /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ - else if(hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->State = HAL_I2C_STATE_READY; - - if (hi2c->Mode == HAL_I2C_MODE_MEM) - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_MemRxCpltCallback(hi2c); - } - else - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_MasterRxCpltCallback(hi2c); - } - } -} - -/** - * @brief I2C Slave complete process. - * @param hi2c: I2C handle. - * @param ITFlags: Interrupt flags to handle. - * @retval None - */ -static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); - - /* Disable all interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* If a DMA is ongoing, Update handle size context */ - if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || - ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) - { - if((hi2c->XferSize - I2C_GET_DMA_REMAIN_DATA(hi2c)) != hi2c->XferSize) - { - hi2c->XferSize = I2C_GET_DMA_REMAIN_DATA(hi2c); - hi2c->XferCount += hi2c->XferSize; - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - - /* Store Last receive data if any */ - if(((ITFlags & I2C_FLAG_RXNE) != RESET)) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - - if((hi2c->XferSize > 0)) - { - hi2c->XferSize--; - hi2c->XferCount--; - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferISR = NULL; - - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->State = HAL_I2C_STATE_READY; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, hi2c->ErrorCode); - } - else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME) - { - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - HAL_I2C_ListenCpltCallback(hi2c); - } - /* Call the corresponding callback to inform upper layer of End of Transfer */ - else if(hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Slave Rx Complete callback */ - HAL_I2C_SlaveRxCpltCallback(hi2c); - } - else - { - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Slave Tx Complete callback */ - HAL_I2C_SlaveTxCpltCallback(hi2c); - } -} - -/** - * @brief I2C Listen complete process. - * @param hi2c: I2C handle. - * @param ITFlags: Interrupt flags to handle. - * @retval None - */ -static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - /* Reset handle parameters */ - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferISR = NULL; - - /* Store Last receive data if any */ - if(((ITFlags & I2C_FLAG_RXNE) != RESET)) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - - if((hi2c->XferSize > 0)) - { - hi2c->XferSize--; - hi2c->XferCount--; - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - - /* Disable all Interrupts*/ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - HAL_I2C_ListenCpltCallback(hi2c); -} - -/** - * @brief I2C interrupts error process. - * @param hi2c: I2C handle. - * @param ErrorCode: Error code to handle. - * @retval None - */ -static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) -{ - /* Reset handle parameters */ - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferCount = 0; - - /* Set new error code */ - hi2c->ErrorCode |= ErrorCode; - - /* Disable Interrupts */ - if((hi2c->State == HAL_I2C_STATE_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) - { - /* Disable all interrupts, except interrupts related to LISTEN state */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); - - /* keep HAL_I2C_STATE_LISTEN if set */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->XferISR = I2C_Slave_ISR_IT; - } - else - { - /* Disable all interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - - /* Set HAL_I2C_STATE_READY */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->XferISR = NULL; - } - - /* Abort DMA TX transfer if any */ - if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); - } - } - /* Abort DMA RX transfer if any */ - else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) - { - /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ - hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); - } - } - else if(hi2c->ErrorCode == HAL_I2C_ERROR_ABORT) - { - hi2c->ErrorCode &= ~HAL_I2C_ERROR_ABORT; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_AbortCpltCallback(hi2c); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_ErrorCallback(hi2c); - } -} - -/** - * @brief I2C Tx data register flush process. - * @param hi2c: I2C handle. - * @retval None - */ -static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) -{ - /* If a pending TXIS flag is set */ - /* Write a dummy data in TXDR to clear it */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) - { - hi2c->Instance->TXDR = 0x00; - } - - /* Flush TX register if not empty */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); - } -} - -/** - * @brief DMA I2C master transmit process complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* If last transfer, enable STOP interrupt */ - if(hi2c->XferCount == 0) - { - /* Enable STOP interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - } - /* else prepare a new DMA transfer and enable TCReload interrupt */ - else - { - /* Update Buffer pointer */ - hi2c->pBuffPtr += hi2c->XferSize; - - /* Set the XferSize to transfer */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Enable TC interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); - } -} - -/** - * @brief DMA I2C slave transmit process complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) -{ - /* No specific action, Master fully manage the generation of STOP condition */ - /* Mean that this generation can arrive at any time, at the end or during DMA process */ - /* So STOP condition should be manage through Interrupt treatment */ -} - -/** - * @brief DMA I2C master receive process complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* If last transfer, enable STOP interrupt */ - if(hi2c->XferCount == 0) - { - /* Enable STOP interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - } - /* else prepare a new DMA transfer and enable TCReload interrupt */ - else - { - /* Update Buffer pointer */ - hi2c->pBuffPtr += hi2c->XferSize; - - /* Set the XferSize to transfer */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); - - /* Enable TC interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); - } -} - -/** - * @brief DMA I2C slave receive process complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) -{ - /* No specific action, Master fully manage the generation of STOP condition */ - /* Mean that this generation can arrive at any time, at the end or during DMA process */ - /* So STOP condition should be manage through Interrupt treatment */ -} - -/** - * @brief DMA I2C communication error callback. - * @param hdma: DMA handle - * @retval None - */ -static void I2C_DMAError(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Disable Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); -} - -/** - * @brief DMA I2C communication abort callback - * (To be called at end of DMA Abort procedure). - * @param hdma: DMA handle. - * @retval None - */ -static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Disable Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Reset AbortCpltCallback */ - hi2c->hdmatx->XferAbortCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Check if come from abort from user */ - if(hi2c->ErrorCode == HAL_I2C_ERROR_ABORT) - { - hi2c->ErrorCode &= ~HAL_I2C_ERROR_ABORT; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_AbortCpltCallback(hi2c); - } - else - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_ErrorCallback(hi2c); - } -} - -/** - * @brief This function handles I2C Communication Timeout. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Flag: Specifies the I2C flag to check. - * @param Status: The new Flag status (SET or RESET). - * @param Timeout: Timeout duration - * @param Tickstart: Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) -{ - while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - Tickstart ) > Timeout)) - { - hi2c->State= HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout: Timeout duration - * @param Tickstart: Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) - { - /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State= HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout: Timeout duration - * @param Tickstart: Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) - { - /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check for the Timeout */ - if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State= HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout: Timeout duration - * @param Tickstart: Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) - { - /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check if a STOPF is detected */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) - { - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State= HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - /* Check for the Timeout */ - if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief This function handles Acknowledge failed detection during an I2C Communication. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout: Timeout duration - * @param Tickstart: Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - /* Wait until STOP Flag is reset */ - /* AutoEnd should be initiate after AF */ - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->State= HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - } - - /* Clear NACKF Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_AF; - hi2c->State= HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - return HAL_OK; -} - -/** - * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). - * @param hi2c: I2C handle. - * @param DevAddress: Specifies the slave address to be programmed. - * @param Size: Specifies the number of bytes to be programmed. - * This parameter must be a value between 0 and 255. - * @param Mode: New state of the I2C START condition generation. - * This parameter can be a value of @ref I2C_RELOAD_END_MODE. - * @param Request: New state of the I2C START condition generation. - * This parameter can be a value of I2C_START_STOP_MODE. - * @retval None - */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_TRANSFER_MODE(Mode)); - assert_param(IS_TRANSFER_REQUEST(Request)); - - /* Get the CR2 register value */ - tmpreg = hi2c->Instance->CR2; - - /* clear tmpreg specific bits */ - tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); - - /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request); - - /* update CR2 register */ - hi2c->Instance->CR2 = tmpreg; -} - -/** - * @brief Manage the enabling of Interrupts. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) -{ - uint32_t tmpisr = 0; - - if((hi2c->XferISR == I2C_Master_ISR_DMA) || \ - (hi2c->XferISR == I2C_Slave_ISR_DMA)) - { - if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Enable ERR, STOP, NACK and ADDR interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) - { - /* Enable ERR and NACK interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; - } - - if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; - } - - if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) - { - /* Enable TC interrupts */ - tmpisr |= I2C_IT_TCI; - } - } - else - { - if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Enable ERR, STOP, NACK, and ADDR interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) - { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; - } - - if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) - { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; - } - - if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; - } - } - - /* Enable interrupts only at the end */ - /* to avoid the risk of I2C interrupt handle execution before */ - /* all interrupts requested done */ - __HAL_I2C_ENABLE_IT(hi2c, tmpisr); - - return HAL_OK; -} - -/** - * @brief Manage the disabling of Interrupts. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) -{ - uint32_t tmpisr = 0; - - if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) - { - /* Disable TC and TXI interrupts */ - tmpisr |= I2C_IT_TCI | I2C_IT_TXI; - - if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) - { - /* Disable NACK and STOP interrupts */ - tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - } - - if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) - { - /* Disable TC and RXI interrupts */ - tmpisr |= I2C_IT_TCI | I2C_IT_RXI; - - if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) - { - /* Disable NACK and STOP interrupts */ - tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - } - - if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Disable ADDR, NACK and STOP interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) - { - /* Enable ERR and NACK interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; - } - - if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; - } - - if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) - { - /* Enable TC interrupts */ - tmpisr |= I2C_IT_TCI; - } - - /* Disable interrupts only at the end */ - /* to avoid a breaking situation like at "t" time */ - /* all disable interrupts request are not done */ - __HAL_I2C_DISABLE_IT(hi2c, tmpisr); - - return HAL_OK; -} - -/** - * @} - */ - -#endif /* HAL_I2C_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c deleted file mode 100644 index b16690a..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c +++ /dev/null @@ -1,255 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_i2c_ex.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief I2C Extended HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of I2C Extended peripheral: - * + Extended features functions - * - @verbatim - ============================================================================== - ##### I2C peripheral Extended features ##### - ============================================================================== - - [..] Comparing to other previous devices, the I2C interface for STM32F7XX - devices contains the following additional features - - (+) Possibility to disable or enable Analog Noise Filter - (+) Use of a configured Digital Noise Filter - (+) Disable or enable Fast Mode Plus (available only for STM32F76xxx/STM32F77xxx - devices) - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to: - (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() - (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() - (#) Configure the enable or disable of fast mode plus driving capability using the functions : - (++) HAL_I2CEx_EnableFastModePlus() - (++) HAL_I2CEx_DisbleFastModePlus() - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup I2CEx I2C Extended HAL module driver - * @brief I2C Extended HAL module driver - * @{ - */ - -#ifdef HAL_I2C_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions - * @{ - */ - -/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure Noise Filters - (+) Configure Fast Mode Plus - -@endverbatim - * @{ - */ - -/** - * @brief Configure I2C Analog noise filter. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param AnalogFilter: New state of the Analog filter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Reset I2Cx ANOFF bit */ - hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); - - /* Set analog filter bit*/ - hi2c->Instance->CR1 |= AnalogFilter; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Configure I2C Digital noise filter. - * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param DigitalFilter: Coefficient of digital noise filter between 0x00 and 0x0F. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Get the old register value */ - tmpreg = hi2c->Instance->CR1; - - /* Reset I2Cx DNF bits [11:8] */ - tmpreg &= ~(I2C_CR1_DNF); - - /* Set I2Cx DNF coefficient */ - tmpreg |= DigitalFilter << 8; - - /* Store the new register value */ - hi2c->Instance->CR1 = tmpreg; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -/** - * @brief Enable the I2C fast mode plus driving capability. - * @param ConfigFastModePlus: Selects the pin. - * This parameter can be one of the @ref I2CEx_FastModePlus values - * @retval None - */ -void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) -{ - /* Check the parameter */ - assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); - - /* Enable SYSCFG clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - /* Enable fast mode plus driving capability for selected pin */ - SET_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus); -} - -/** - * @brief Disable the I2C fast mode plus driving capability. - * @param ConfigFastModePlus: Selects the pin. - * This parameter can be one of the @ref I2CEx_FastModePlus values - * @retval None - */ -void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) -{ - /* Check the parameter */ - assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); - - /* Enable SYSCFG clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - /* Disable fast mode plus driving capability for selected pin */ - CLEAR_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus); -} -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_I2C_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2s.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2s.c deleted file mode 100644 index 1ffe173..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2s.c +++ /dev/null @@ -1,1556 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_i2s.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief I2S HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Integrated Interchip Sound (I2S) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and Errors functions - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The I2S HAL driver can be used as follows: - - (#) Declare a I2S_HandleTypeDef handle structure. - (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API: - (##) Enable the SPIx interface clock. - (##) I2S pins configuration: - (+++) Enable the clock for the I2S GPIOs. - (+++) Configure these I2S pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT() - and HAL_I2S_Receive_IT() APIs). - (+++) Configure the I2Sx interrupt priority. - (+++) Enable the NVIC I2S IRQ handle. - (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA() - and HAL_I2S_Receive_DMA() APIs: - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx Channel. - (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the - DMA Tx/Rx Channel. - - (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity - using HAL_I2S_Init() function. - - -@- The specific I2S interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process. - -@- Make sure that either: - (+@) I2S clock is configured based on SYSCLK or - (+@) External clock source is configured after setting correctly - the define constant EXTERNAL_CLOCK_VALUE in the stm32f3xx_hal_conf.h file. - - (#) Three mode of operations are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() - (+) Receive an amount of data in blocking mode using HAL_I2S_Receive() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() - (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback - (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() - (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback - (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_RxCpltCallback - (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2S_ErrorCallback - - *** DMA mode IO operation *** - ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() - (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback - (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_TxCpltCallback - (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() - (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback - (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_RxCpltCallback - (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2S_ErrorCallback - (+) Pause the DMA Transfer using HAL_I2S_DMAPause() - (+) Resume the DMA Transfer using HAL_I2S_DMAResume() - (+) Stop the DMA Transfer using HAL_I2S_DMAStop() - - *** I2S HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in I2S HAL driver. - - (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) - (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode) - (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts - (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts - (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not - - [..] - (@) You can refer to the I2S HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup I2S I2S - * @brief I2S HAL module driver - * @{ - */ - -#ifdef HAL_I2S_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup I2S_Private_Functions I2S Private Functions - * @{ - */ -static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma); -static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); -static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma); -static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void I2S_DMAError(DMA_HandleTypeDef *hdma); -static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s); -static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s); -static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s); -static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup I2S_Exported_Functions I2S Exported Functions - * @{ - */ - -/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - de-initialize the I2Sx peripheral in simplex mode: - - (+) User must Implement HAL_I2S_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - - (+) Call the function HAL_I2S_Init() to configure the selected device with - the selected configuration: - (++) Mode - (++) Standard - (++) Data Format - (++) MCLK Output - (++) Audio frequency - (++) Polarity - (++) Full duplex mode - - (+) Call the function HAL_I2S_DeInit() to restore the default configuration - of the selected I2Sx peripheral. -@endverbatim - * @{ - */ - -/** - * @brief Initializes the I2S according to the specified parameters - * in the I2S_InitTypeDef and create the associated handle. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) -{ - uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0, i2sclk = 0; - - /* Check the I2S handle allocation */ - if(hi2s == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); - assert_param(IS_I2S_MODE(hi2s->Init.Mode)); - assert_param(IS_I2S_STANDARD(hi2s->Init.Standard)); - assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat)); - assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput)); - assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq)); - assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); - assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource)); - - if(hi2s->State == HAL_I2S_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hi2s->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ - HAL_I2S_MspInit(hi2s); - } - - hi2s->State = HAL_I2S_STATE_BUSY; - - /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ - SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ - SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD); - hi2s->Instance->I2SPR = 0x0002; - - /* Get the I2SCFGR register value */ - tmpreg = hi2s->Instance->I2SCFGR; - - /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ - if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT) - { - i2sodd = (uint16_t)0; - i2sdiv = (uint16_t)2; - } - /* If the requested audio frequency is not the default, compute the prescaler */ - else - { - /* Check the frame length (For the Prescaler computing) *******************/ - if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) - { - /* Packet length is 16 bits */ - packetlength = 1; - } - else - { - /* Packet length is 32 bits */ - packetlength = 2; - } - - /* Get I2S source Clock frequency ****************************************/ - - /* If an external I2S clock has to be used, the specific define should be set - in the project configuration or in the stm32f3xx_conf.h file */ - if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL) - { - /* Set the I2S clock to the external clock value */ - i2sclk = EXTERNAL_CLOCK_VALUE; - } - else - { - /* Get the I2S source clock value */ - i2sclk = I2S_GetClockFreq(hi2s); - } - - /* Compute the Real divider depending on the MCLK output state, with a floating point */ - if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) - { - /* MCLK output is enabled */ - tmp = (uint16_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5); - } - else - { - /* MCLK output is disabled */ - tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5); - } - - /* Remove the flatting point */ - tmp = tmp / 10; - - /* Check the parity of the divider */ - i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); - - /* Compute the i2sdiv prescaler */ - i2sdiv = (uint16_t)((tmp - i2sodd) / 2); - - /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (uint16_t) (i2sodd << 8); - } - - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if((i2sdiv < 2) || (i2sdiv > 0xFF)) - { - /* Set the default values */ - i2sdiv = 2; - i2sodd = 0; - } - - /* Write to SPIx I2SPR register the computed value */ - hi2s->Instance->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)hi2s->Init.MCLKOutput)); - - /* Configure the I2S with the I2S_InitStruct values */ - tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \ - (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \ - (uint16_t)hi2s->Init.CPOL)))); - - /* Write to SPIx I2SCFGR */ - hi2s->Instance->I2SCFGR = tmpreg; - - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->State= HAL_I2S_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the I2S peripheral - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) -{ - /* Check the I2S handle allocation */ - if(hi2s == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); - - hi2s->State = HAL_I2S_STATE_BUSY; - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ - HAL_I2S_MspDeInit(hi2s); - - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->State = HAL_I2S_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; -} - -/** - * @brief I2S MSP Init - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ - __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2s); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_MspInit could be implemented in the user file - */ -} - -/** - * @brief I2S MSP DeInit - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ - __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2s); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2S_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the I2S data - transfers. - - (#) There are two modes of transfer: - (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts - or DMA. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the - dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - - (#) Blocking mode functions are : - (++) HAL_I2S_Transmit() - (++) HAL_I2S_Receive() - - (#) No-Blocking mode functions with Interrupt are : - (++) HAL_I2S_Transmit_IT() - (++) HAL_I2S_Receive_IT() - - (#) No-Blocking mode functions with DMA are : - (++) HAL_I2S_Transmit_DMA() - (++) HAL_I2S_Receive_DMA() - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_I2S_TxCpltCallback() - (++) HAL_I2S_RxCpltCallback() - (++) HAL_I2S_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Transmit an amount of data in blocking mode - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer. - * @param Size: number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @param Timeout: Timeout duration - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) -{ - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - if(hi2s->State == HAL_I2S_STATE_READY) - { - if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ - ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) - { - hi2s->TxXferSize = (Size << 1); - hi2s->TxXferCount = (Size << 1); - } - else - { - hi2s->TxXferSize = Size; - hi2s->TxXferCount = Size; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->State = HAL_I2S_STATE_BUSY_TX; - - /* Check if the I2S is already enabled */ - if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - while(hi2s->TxXferCount > 0) - { - hi2s->Instance->DR = (*pData++); - hi2s->TxXferCount--; - /* Wait until TXE flag is set */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK) - { - /* Set the error code and execute error callback*/ - hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT; - HAL_I2S_ErrorCallback(hi2s); - return HAL_TIMEOUT; - } - - /* Check if an underrun occurs */ - if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) - { - /* Set the I2S State ready */ - hi2s->State = HAL_I2S_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - /* Set the error code and execute error callback*/ - hi2s->ErrorCode |= HAL_I2S_ERROR_UDR; - HAL_I2S_ErrorCallback(hi2s); - - return HAL_ERROR; - } - } - - /* Check if Slave mode is selected */ - if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX)) - { - /* Wait until Busy flag is reset */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK) - { - /* Set the error code and execute error callback*/ - hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT; - HAL_I2S_ErrorCallback(hi2s); - return HAL_TIMEOUT; - } - } - - hi2s->State = HAL_I2S_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in blocking mode - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer. - * @param Size: number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @param Timeout: Timeout duration - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate - * in continuous way and as the I2S is not disabled at the end of the I2S transaction. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) -{ - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - if(hi2s->State == HAL_I2S_STATE_READY) - { - if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ - ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) - { - hi2s->RxXferSize = (Size << 1); - hi2s->RxXferCount = (Size << 1); - } - else - { - hi2s->RxXferSize = Size; - hi2s->RxXferCount = Size; - } - /* Process Locked */ - __HAL_LOCK(hi2s); - - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->State = HAL_I2S_STATE_BUSY_RX; - - /* Check if the I2S is already enabled */ - if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Check if Master Receiver mode is selected */ - if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) - { - /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read - access to the SPI_SR register. */ - __HAL_I2S_CLEAR_OVRFLAG(hi2s); - } - - /* Receive data */ - while(hi2s->RxXferCount > 0) - { - /* Wait until RXNE flag is set */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK) - { - /* Set the error code and execute error callback*/ - hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT; - HAL_I2S_ErrorCallback(hi2s); - return HAL_TIMEOUT; - } - - /* Check if an overrun occurs */ - if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET) - { - /* Set the I2S State ready */ - hi2s->State = HAL_I2S_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - /* Set the error code and execute error callback*/ - hi2s->ErrorCode |= HAL_I2S_ERROR_OVR; - HAL_I2S_ErrorCallback(hi2s); - - return HAL_ERROR; - } - - (*pData++) = hi2s->Instance->DR; - hi2s->RxXferCount--; - } - - hi2s->State = HAL_I2S_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer. - * @param Size: number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) -{ - if(hi2s->State == HAL_I2S_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - hi2s->pTxBuffPtr = pData; - if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ - ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) - { - hi2s->TxXferSize = (Size << 1); - hi2s->TxXferCount = (Size << 1); - } - else - { - hi2s->TxXferSize = Size; - hi2s->TxXferCount = Size; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->State = HAL_I2S_STATE_BUSY_TX; - - /* Enable TXE and ERR interrupt */ - __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); - - /* Check if the I2S is already enabled */ - if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData: a 16-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation - * between Master and Slave otherwise the I2S interrupt should be optimized. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) -{ - if(hi2s->State == HAL_I2S_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - hi2s->pRxBuffPtr = pData; - if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ - ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) - { - hi2s->RxXferSize = (Size << 1); - hi2s->RxXferCount = (Size << 1); - } - else - { - hi2s->RxXferSize = Size; - hi2s->RxXferCount = Size; - } - /* Process Locked */ - __HAL_LOCK(hi2s); - - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->State = HAL_I2S_STATE_BUSY_RX; - - /* Enable TXE and ERR interrupt */ - __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); - - /* Check if the I2S is already enabled */ - if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit an amount of data in non-blocking mode with DMA - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData: a 16-bit pointer to the Transmit data buffer. - * @param Size: number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) -{ - uint32_t *tmp; - - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(hi2s->State == HAL_I2S_STATE_READY) - { - hi2s->pTxBuffPtr = pData; - if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ - ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) - { - hi2s->TxXferSize = (Size << 1); - hi2s->TxXferCount = (Size << 1); - } - else - { - hi2s->TxXferSize = Size; - hi2s->TxXferCount = Size; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->State = HAL_I2S_STATE_BUSY_TX; - - /* Set the I2S Tx DMA Half transfer complete callback */ - hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt; - - /* Set the I2S TxDMA transfer complete callback */ - hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt; - - /* Set the DMA error callback */ - hi2s->hdmatx->XferErrorCallback = I2S_DMAError; - - /* Enable the Tx DMA Channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize); - - /* Check if the I2S is already enabled */ - if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Enable Tx DMA Request */ - hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in non-blocking mode with DMA - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData: a 16-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) -{ - uint32_t *tmp; - - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(hi2s->State == HAL_I2S_STATE_READY) - { - hi2s->pRxBuffPtr = pData; - if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ - ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) - { - hi2s->RxXferSize = (Size << 1); - hi2s->RxXferCount = (Size << 1); - } - else - { - hi2s->RxXferSize = Size; - hi2s->RxXferCount = Size; - } - /* Process Locked */ - __HAL_LOCK(hi2s); - - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->State = HAL_I2S_STATE_BUSY_RX; - - /* Set the I2S Rx DMA Half transfer complete callback */ - hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt; - - /* Set the I2S Rx DMA transfer complete callback */ - hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt; - - /* Set the DMA error callback */ - hi2s->hdmarx->XferErrorCallback = I2S_DMAError; - - /* Check if Master Receiver mode is selected */ - if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) - { - /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read - access to the SPI_SR register. */ - __HAL_I2S_CLEAR_OVRFLAG(hi2s); - } - - /* Enable the Rx DMA Channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize); - - /* Check if the I2S is already enabled */ - if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Enable Rx DMA Request */ - hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Pauses the audio stream playing from the Media. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) -{ - /* Process Locked */ - __HAL_LOCK(hi2s); - - if(hi2s->State == HAL_I2S_STATE_BUSY_TX) - { - /* Disable the I2S DMA Tx request */ - hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); - } - else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) - { - /* Disable the I2S DMA Rx request */ - hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); - } - else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) - { - if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX)) - { - /* Disable the I2S DMA Tx request */ - hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); - } - else - { - /* Disable the I2S DMA Rx request */ - hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; -} - -/** - * @brief Resumes the audio stream playing from the Media. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) -{ - /* Process Locked */ - __HAL_LOCK(hi2s); - - if(hi2s->State == HAL_I2S_STATE_BUSY_TX) - { - /* Enable the I2S DMA Tx request */ - SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - } - else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) - { - /* Enable the I2S DMA Rx request */ - SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - } - - /* If the I2S peripheral is still not enabled, enable it */ - if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; -} - -/** - * @brief Stops the audio stream playing from the Media. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) -{ - /* Process Locked */ - __HAL_LOCK(hi2s); - - /* Disable the I2S Tx/Rx DMA requests */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - - /* Abort the I2S DMA Channel tx */ - if(hi2s->hdmatx != NULL) - { - /* Disable the I2S DMA channel */ - __HAL_DMA_DISABLE(hi2s->hdmatx); - HAL_DMA_Abort(hi2s->hdmatx); - } - /* Abort the I2S DMA Channel rx */ - if(hi2s->hdmarx != NULL) - { - /* Disable the I2S DMA channel */ - __HAL_DMA_DISABLE(hi2s->hdmarx); - HAL_DMA_Abort(hi2s->hdmarx); - } - - /* Disable I2S peripheral */ - __HAL_I2S_DISABLE(hi2s); - - hi2s->State = HAL_I2S_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; -} - -/** - * @brief This function handles I2S interrupt request. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status - */ -void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) -{ - __IO uint32_t i2ssr = hi2s->Instance->SR; - - if(hi2s->State == HAL_I2S_STATE_BUSY_RX) - { - /* I2S in mode Receiver ----------------------------------------------------*/ - if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET)) - { - I2S_Receive_IT(hi2s); - } - - /* I2S Overrun error interrupt occurred -------------------------------------*/ - if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) - { - /* Disable RXNE and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); - - /* Set the I2S State ready */ - hi2s->State = HAL_I2S_STATE_READY; - - /* Set the error code and execute error callback*/ - hi2s->ErrorCode |= HAL_I2S_ERROR_OVR; - HAL_I2S_ErrorCallback(hi2s); - } - } - else if(hi2s->State == HAL_I2S_STATE_BUSY_TX) - { - /* I2S in mode Transmitter ---------------------------------------------------*/ - if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET)) - { - I2S_Transmit_IT(hi2s); - } - - /* I2S Underrun error interrupt occurred ------------------------------------*/ - if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) - { - /* Disable TXE and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); - - /* Set the I2S State ready */ - hi2s->State = HAL_I2S_STATE_READY; - - /* Set the error code and execute error callback*/ - hi2s->ErrorCode |= HAL_I2S_ERROR_UDR; - HAL_I2S_ErrorCallback(hi2s); - } - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup I2S_Private_Functions I2S Private Functions - * @{ - */ -/** - * @brief This function handles I2S Communication Timeout. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param Flag: Flag checked - * @param State: Value of the flag expected - * @param Timeout: Duration of the timeout - * @retval HAL status - */ -static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, - uint32_t State, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until flag is set */ - if(State == RESET) - { - while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Set the I2S State ready */ - hi2s->State= HAL_I2S_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_TIMEOUT; - } - } - } - } - else - { - while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Set the I2S State ready */ - hi2s->State= HAL_I2S_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_TIMEOUT; - } - } - } - } - return HAL_OK; -} -/** - * @} - */ - -/** @addtogroup I2S_Exported_Functions I2S Exported Functions - * @{ - */ - -/** @addtogroup I2S_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ -/** - * @brief Tx Transfer Half completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ - __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2s); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_TxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Tx Transfer completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ - __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2s); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer half completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2s); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2s); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief I2S error callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ - __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2s); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the I2S state - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL state - */ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) -{ - return hi2s->State; -} - -/** - * @brief Return the I2S error code - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval I2S Error Code - */ -uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) -{ - return hi2s->ErrorCode; -} -/** - * @} - */ - -/** - * @} - */ - - /** - * @brief Get I2S Input Clock based on I2S source clock selection - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module. - * @retval I2S Clock Input - */ -static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s) -{ - uint32_t tmpreg = 0; - /* This variable used to store the VCO Input (value in Hz) */ - uint32_t vcoinput = 0; - /* This variable used to store the I2S_CK_x (value in Hz) */ - uint32_t i2sclocksource = 0; - - /* Configure I2S Clock based on I2S source clock selection */ - - /* I2S_CLK_x : I2S Block Clock configuration for different clock sources selected */ - switch(hi2s->Init.ClockSource) - { - case I2S_CLOCK_PLL : - { - /* Configure the PLLI2S division factor */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) - { - /* In Case the PLL Source is HSI (Internal Clock) */ - vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - else - { - /* In Case the PLL Source is HSE (External Clock) */ - vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); - } - - /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ - /* I2S_CLK(first level) = PLLI2S_VCO Output/PLLI2SR */ - tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28; - i2sclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); - - break; - } - case I2S_CLOCK_EXTERNAL : - { - i2sclocksource = EXTERNAL_CLOCK_VALUE; - break; - } - default : - { - break; - } - } - - /* the return result is the value of I2S clock */ - return i2sclocksource; -} - -/** @addtogroup I2S_Private_Functions I2S Private Functions - * @{ - */ -/** - * @brief DMA I2S transmit process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) -{ - I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) - { - hi2s->TxXferCount = 0; - - /* Disable Tx DMA Request */ - hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); - - if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) - { - if(hi2s->RxXferCount == 0) - { - hi2s->State = HAL_I2S_STATE_READY; - } - } - else - { - hi2s->State = HAL_I2S_STATE_READY; - } - } - HAL_I2S_TxCpltCallback(hi2s); -} - -/** - * @brief DMA I2S transmit process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) -{ - I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - HAL_I2S_TxHalfCpltCallback(hi2s); -} - -/** - * @brief DMA I2S receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) -{ - I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) - { - /* Disable Rx DMA Request */ - hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); - - hi2s->RxXferCount = 0; - if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) - { - if(hi2s->TxXferCount == 0) - { - hi2s->State = HAL_I2S_STATE_READY; - } - } - else - { - hi2s->State = HAL_I2S_STATE_READY; - } - } - HAL_I2S_RxCpltCallback(hi2s); -} - -/** - * @brief DMA I2S receive process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - HAL_I2S_RxHalfCpltCallback(hi2s); -} - -/** - * @brief DMA I2S communication error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void I2S_DMAError(DMA_HandleTypeDef *hdma) -{ - I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Disable Rx and Tx DMA Request */ - hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); - hi2s->TxXferCount = 0; - hi2s->RxXferCount = 0; - - hi2s->State= HAL_I2S_STATE_READY; - - /* Set the error code and execute error callback*/ - hi2s->ErrorCode |= HAL_I2S_ERROR_DMA; - HAL_I2S_ErrorCallback(hi2s); -} - -/** - * @brief Transmit an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) -{ - /* Transmit data */ - hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); - hi2s->TxXferCount--; - - if(hi2s->TxXferCount == 0) - { - /* Disable TXE and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); - - hi2s->State = HAL_I2S_STATE_READY; - HAL_I2S_TxCpltCallback(hi2s); - } -} - -/** - * @brief Receive an amount of data in non-blocking mode with Interrupt - * @param hi2s: I2S handle - * @retval None - */ -static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) -{ - /* Receive data */ - (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; - hi2s->RxXferCount--; - - if(hi2s->RxXferCount == 0) - { - /* Disable RXNE and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); - - hi2s->State = HAL_I2S_STATE_READY; - HAL_I2S_RxCpltCallback(hi2s); - } -} -/** - * @} - */ - -#endif /* HAL_I2S_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_irda.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_irda.c deleted file mode 100644 index 672598c..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_irda.c +++ /dev/null @@ -1,1571 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_irda.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief IRDA HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the IrDA SIR ENDEC block (IrDA): - * + Initialization and de-initialization methods - * + IO operation methods - * + Peripheral Control methods - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The IRDA HAL driver can be used as follows: - - (#) Declare a IRDA_HandleTypeDef handle structure. - (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API: - (##) Enable the USARTx interface clock. - (##) IRDA pins configuration: - (+++) Enable the clock for the IRDA GPIOs. - (+++) Configure these IRDA pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT() - and HAL_IRDA_Receive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. - (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA() - and HAL_IRDA_Receive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx stream. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx Stream. - (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream. - - (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler - and Mode(Receiver/Transmitter) in the hirda Init structure. - - (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API: - (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customized HAL_IRDA_MspInit() API. - -@@- The specific IRDA interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. - - (#) Three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit() - (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT() - (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_IRDA_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT() - (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_IRDA_RxCpltCallback - (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_IRDA_ErrorCallback - - *** DMA mode IO operation *** - ============================= - [..] - (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA() - (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_IRDA_TxCpltCallback - (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA() - (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_IRDA_RxCpltCallback - (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_IRDA_ErrorCallback - - *** IRDA HAL driver macros list *** - =================================== - [..] - Below the list of most used macros in IRDA HAL driver. - - (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral - (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral - (+) __HAL_IRDA_GET_FLAG : Checks whether the specified IRDA flag is set or not - (+) __HAL_IRDA_CLEAR_FLAG : Clears the specified IRDA pending flag - (+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt - (+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt - - (@) You can refer to the IRDA HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup IRDA IRDA - * @brief HAL IRDA module driver - * @{ - */ -#ifdef HAL_IRDA_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup IRDA_Private_Constants - * @{ - */ -#define TEACK_REACK_TIMEOUT 1000U -#define HAL_IRDA_TXDMA_TIMEOUTVALUE 22000U -#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \ - | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup IRDA_Private_Functions - * @{ - */ -static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma); -static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma); -static void IRDA_DMAError(DMA_HandleTypeDef *hdma); -static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma); -static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda); -static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda); -static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda); -static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda); -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); -static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); -static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); -static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup IRDA_Exported_Functions IrDA Exported Functions - * @{ - */ - -/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USARTx or the UARTy - in IrDA mode. - (+) For the asynchronous mode only these parameters can be configured: - (++) BaudRate - (++) WordLength - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - please refer to Reference manual for possible IRDA frame formats. - (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may - not be rejected. The receiver set up time should be managed by software. The IrDA physical layer - specification specifies a minimum of 10 ms delay between transmission and - reception (IrDA is a half duplex protocol). - (++) Mode: Receiver/transmitter modes - (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode. - [..] - The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures - are available in reference manual). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the IRDA mode according to the specified - * parameters in the IRDA_InitTypeDef and create the associated handle. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) -{ - /* Check the IRDA handle allocation */ - if(hirda == NULL) - { - return HAL_ERROR; - } - - /* Check the USART/UART associated to the IRDA handle */ - assert_param(IS_IRDA_INSTANCE(hirda->Instance)); - - if(hirda->gState == HAL_IRDA_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hirda->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK, CORTEX */ - HAL_IRDA_MspInit(hirda); - } - - hirda->gState = HAL_IRDA_STATE_BUSY; - - /* Disable the Peripheral to update the configuration registers */ - __HAL_IRDA_DISABLE(hirda); - - /* Set the IRDA Communication parameters */ - IRDA_SetConfig(hirda); - - /* In IRDA mode, the following bits must be kept cleared: - - LINEN, STOP and CLKEN bits in the USART_CR2 register, - - SCEN and HDSEL bits in the USART_CR3 register.*/ - CLEAR_BIT(hirda->Instance->CR3, USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN); - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_SCEN | USART_CR3_HDSEL); - - /* set the UART/USART in IRDA mode */ - SET_BIT(hirda->Instance->CR3, USART_CR3_IREN); - - /* Enable the Peripheral */ - __HAL_IRDA_ENABLE(hirda); - - /* TEACK and/or REACK to check before moving hirda->State to Ready */ - return (IRDA_CheckIdleState(hirda)); -} - -/** - * @brief DeInitializes the IRDA peripheral - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) -{ - /* Check the IRDA handle allocation */ - if(hirda == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_IRDA_INSTANCE(hirda->Instance)); - - hirda->gState = HAL_IRDA_STATE_BUSY; - - /* DeInit the low level hardware */ - HAL_IRDA_MspDeInit(hirda); - /* Disable the Peripheral */ - __HAL_IRDA_DISABLE(hirda); - - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->gState = HAL_IRDA_STATE_RESET; - hirda->RxState = HAL_IRDA_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hirda); - - return HAL_OK; -} - -/** - * @brief IRDA MSP Init. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_IRDA_MspInit could be implemented in the user file - */ -} - -/** - * @brief IRDA MSP DeInit. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_IRDA_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions - * @brief IRDA Transmit/Receive functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of functions allowing to manage the IRDA data transfers. - [..] - IrDA is a half duplex communication protocol. If the Transmitter is busy, any data - on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver - is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. - While receiving data, transmission should be avoided as the data to be transmitted - could be corrupted. - - (#) There are two modes of transfer: - (++) Blocking mode: the communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode: the communication is performed using Interrupts - or DMA, these API's return the HAL status. - The end of the data processing will be indicated through the - dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks - will be executed respectively at the end of the Transmit or Receive process - The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected - - (#) Blocking mode API's are : - (++) HAL_IRDA_Transmit() - (++) HAL_IRDA_Receive() - - (#) Non-Blocking mode API's with Interrupt are : - (++) HAL_IRDA_Transmit_IT() - (++) HAL_IRDA_Receive_IT() - (++) HAL_IRDA_IRQHandler() - (++) IRDA_Transmit_IT() - (++) IRDA_Receive_IT() - - (#) Non-Blocking mode functions with DMA are : - (++) HAL_IRDA_Transmit_DMA() - (++) HAL_IRDA_Receive_DMA() - - (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: - (++) HAL_IRDA_TxCpltCallback() - (++) HAL_IRDA_RxCpltCallback() - (++) HAL_IRDA_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Sends an amount of data in blocking mode. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Specify timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint16_t* tmp; - uint32_t tickstart = 0U; - - /* Check that a Tx process is not already ongoing */ - if(hirda->gState == HAL_IRDA_STATE_READY) - { - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->gState = HAL_IRDA_STATE_BUSY_TX; - - /* Init tickstart for timeout managment*/ - tickstart = HAL_GetTick(); - - hirda->TxXferSize = Size; - hirda->TxXferCount = Size; - while(hirda->TxXferCount > 0U) - { - hirda->TxXferCount--; - - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) - { - tmp = (uint16_t*) pData; - hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU); - pData +=2; - } - else - { - hirda->Instance->TDR = (*pData++ & (uint8_t)0xFFU); - } - } - - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* At end of Tx process, restore hirda->gState to Ready */ - hirda->gState = HAL_IRDA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in blocking mode. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Specify timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint16_t* tmp; - uint16_t uhMask; - uint32_t tickstart = 0U; - - /* Check that a Rx process is not already ongoing */ - if(hirda->RxState == HAL_IRDA_STATE_READY) - { - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->RxState = HAL_IRDA_STATE_BUSY_RX; - - /* Init tickstart for timeout managment*/ - tickstart = HAL_GetTick(); - - hirda->RxXferSize = Size; - hirda->RxXferCount = Size; - - /* Computation of the mask to apply to the RDR register - of the UART associated to the IRDA */ - IRDA_MASK_COMPUTATION(hirda); - uhMask = hirda->Mask; - - /* Check data remaining to be received */ - while(hirda->RxXferCount > 0U) - { - hirda->RxXferCount--; - - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) - { - tmp = (uint16_t*) pData ; - *tmp = (uint16_t)(hirda->Instance->RDR & uhMask); - pData +=2; - } - else - { - *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); - } - } - - /* At end of Rx process, restore hirda->RxState to Ready */ - hirda->RxState = HAL_IRDA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in non blocking mode. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) -{ - /* Check that a Tx process is not already ongoing */ - if(hirda->gState == HAL_IRDA_STATE_READY) - { - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - - hirda->pTxBuffPtr = pData; - hirda->TxXferSize = Size; - hirda->TxXferCount = Size; - - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->gState = HAL_IRDA_STATE_BUSY_TX; - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - /* Enable the IRDA Transmit Complete Interrupt */ - SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives an amount of data in non blocking mode. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) -{ - /* Check that a Rx process is not already ongoing */ - if(hirda->RxState == HAL_IRDA_STATE_READY) - { - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - - hirda->pRxBuffPtr = pData; - hirda->RxXferSize = Size; - hirda->RxXferCount = Size; - - /* Computation of the mask to apply to the RDR register - of the UART associated to the IRDA */ - IRDA_MASK_COMPUTATION(hirda); - - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->RxState = HAL_IRDA_STATE_BUSY_RX; - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - /* Enable the IRDA Parity Error Interrupt */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); - - /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); - - /* Enable the IRDA Data Register not empty Interrupt */ - SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sends an amount of data in non blocking mode. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) -{ - uint32_t *tmp; - - /* Check that a Tx process is not already ongoing */ - if(hirda->gState == HAL_IRDA_STATE_READY) - { - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - - hirda->pTxBuffPtr = pData; - hirda->TxXferSize = Size; - hirda->TxXferCount = Size; - - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->gState = HAL_IRDA_STATE_BUSY_TX; - - /* Set the IRDA DMA transfer complete callback */ - hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt; - - /* Set the IRDA DMA half transfer complete callback */ - hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt; - - /* Set the DMA error callback */ - hirda->hdmatx->XferErrorCallback = IRDA_DMAError; - - /* Set the DMA abort callback */ - hirda->hdmatx->XferAbortCallback = NULL; - - /* Enable the IRDA transmit DMA channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->TDR, Size); - - /* Clear the TC flag in the SR register by writing 0 to it */ - __HAL_IRDA_CLEAR_IT(hirda, IRDA_FLAG_TC); - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the IRDA CR3 register */ - SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives an amount of data in non blocking mode. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @note When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) -{ - uint32_t *tmp; - - /* Check that a Rx process is not already ongoing */ - if(hirda->RxState == HAL_IRDA_STATE_READY) - { - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - - hirda->pRxBuffPtr = pData; - hirda->RxXferSize = Size; - - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->RxState = HAL_IRDA_STATE_BUSY_RX; - - /* Set the IRDA DMA transfer complete callback */ - hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt; - - /* Set the IRDA DMA half transfer complete callback */ - hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt; - - /* Set the DMA error callback */ - hirda->hdmarx->XferErrorCallback = IRDA_DMAError; - - /* Set the DMA abort callback */ - hirda->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, *(uint32_t*)tmp, Size); - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - /* Enable the IRDA Parity Error Interrupt */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); - - /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the USART CR3 register */ - SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Pauses the DMA Transfer. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) -{ - /* Process Locked */ - __HAL_LOCK(hirda); - - if((hirda->gState == HAL_IRDA_STATE_BUSY_TX)&& - (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))) - { - /* Disable the UART DMA Tx request */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - } - if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX)&& - (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))) - { - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); - - /* Disable the UART DMA Rx request */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; -} - -/** - * @brief Resumes the DMA Transfer. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) -{ - /* Process Locked */ - __HAL_LOCK(hirda); - - if(hirda->gState == HAL_IRDA_STATE_BUSY_TX) - { - /* Enable the UART DMA Tx request */ - SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - } - if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX) - { - /* Clear the Overrun flag before resuming the Rx transfer*/ - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); - - /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); - SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); - - /* Enable the UART DMA Rx request */ - SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; -} - -/** - * @brief Stops the DMA Transfer. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) -{ - /* The Lock is not implemented on this API to allow the user application - to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() / - HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback: - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete - interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of - the stream and the corresponding call back is executed. */ - - /* Stop IRDA DMA Tx request if ongoing */ - if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && - (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))) - { - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - - /* Abort the IRDA DMA Tx channel */ - if(hirda->hdmatx != NULL) - { - HAL_DMA_Abort(hirda->hdmatx); - } - IRDA_EndTxTransfer(hirda); - } - - /* Stop IRDA DMA Rx request if ongoing */ - if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && - (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))) - { - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - - /* Abort the IRDA DMA Rx channel */ - if(hirda->hdmarx != NULL) - { - HAL_DMA_Abort(hirda->hdmarx); - } - IRDA_EndRxTransfer(hirda); - } - return HAL_OK; -} - -/** - * @brief DMA IRDA communication abort callback, when call by HAL services on Error - * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma: DMA handle. - * @retval None - */ -static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hirda->RxXferCount = 0U; - hirda->TxXferCount = 0U; - - HAL_IRDA_ErrorCallback(hirda); -} - -/** - * @brief This function handles IRDA interrupt request. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) -{ - uint32_t isrflags, cr1its, cr3its, errorflags; - - isrflags = READ_REG(hirda->Instance->ISR); - cr1its = READ_REG(hirda->Instance->CR1); - cr3its = READ_REG(hirda->Instance->CR3); - - /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); - if (errorflags == RESET) - { - /* IRDA in mode Receiver ---------------------------------------------------*/ - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) - { - IRDA_Receive_IT(hirda); - /* Clear RXNE interrupt flag */ - __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST); - } - } - - /* If some errors occur */ - if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET)) - { - /* IRDA parity error interrupt occurred -------------------------------------*/ - if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) - { - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF); - hirda->ErrorCode |= HAL_IRDA_ERROR_PE; - } - - /* IRDA frame error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) - { - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF); - hirda->ErrorCode |= HAL_IRDA_ERROR_FE; - } - - /* IRDA noise error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) - { - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF); - hirda->ErrorCode |= HAL_IRDA_ERROR_NE; - } - - /* IRDA Over-Run interrupt occurred -----------------------------------------*/ - if(((isrflags & USART_ISR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) - { - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); - hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; - } - - /* Call IRDA Error Call back function if need be --------------------------*/ - if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE) - { - /* IRDA in mode Receiver ---------------------------------------------------*/ - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) - { - IRDA_Receive_IT(hirda); - } - - /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ - if (((hirda->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || - (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))) - { - /* Blocking error : transfer is aborted - Set the IRDA state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ - IRDA_EndRxTransfer(hirda); - - /* Disable the IRDA DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - - /* Abort the IRDA DMA Rx channel */ - if(hirda->hdmarx != NULL) - { - /* Set the IRDA DMA Abort callback : - will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */ - hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError; - - /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) - { - /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */ - hirda->hdmarx->XferAbortCallback(hirda->hdmarx); - } - } - else - { - /* Call user error callback */ - HAL_IRDA_ErrorCallback(hirda); - } - } - else - { - /* Call user error callback */ - HAL_IRDA_ErrorCallback(hirda); - } - } - else - { - /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ - HAL_IRDA_ErrorCallback(hirda); - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - } - } - return; - - } /* End if some error occurs */ - - /* IRDA in mode Transmitter ------------------------------------------------*/ - if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) - { - IRDA_Transmit_IT(hirda); - return; - } - - /* IRDA in mode Transmitter (transmission end) -----------------------------*/ - if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) - { - IRDA_EndTransmit_IT(hirda); - return; - } -} - -/** - * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion). - * @param hirda: IRDA handle. - * @retval None - */ -static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda) -{ - /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - - /* At end of Tx process, restore hirda->gState to Ready */ - hirda->gState = HAL_IRDA_STATE_READY; -} - -/** - * @brief End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion). - * @param hirda: IRDA handle. - * @retval None - */ -static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); - - /* At end of Rx process, restore huart->RxState to Ready */ - hirda->RxState = HAL_IRDA_STATE_READY; -} - -/** - * @brief Tx Transfer complete callbacks. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Tx Half Transfer completed callbacks. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval None - */ -__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_TxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Rx Transfer complete callbacks. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Rx Half Transfer complete callbacks. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_RxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief IRDA error callbacks. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_ErrorCallback can be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup IRDA_Exported_Functions_Group3 Peripheral Control functions - * @brief IRDA control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the IRDA. - (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IRDA peripheral. - (+) IRDA_SetConfig() API is used to configure the IRDA communications parameters. -@endverbatim - * @{ - */ - -/** - * @brief Returns the IRDA state. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL state - */ -HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) -{ - uint32_t temp1 = 0x00U, temp2 = 0x00U; - temp1 = hirda->gState; - temp2 = hirda->RxState; - - return (HAL_IRDA_StateTypeDef)(temp1 | temp2); -} - -/** - * @brief Return the IRDA error code - * @param hirda : pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA. -* @retval IRDA Error Code -*/ -uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) -{ - uint32_t temp1 = 0x00U, temp2 = 0x00U; - temp1 = hirda->gState; - temp2 = hirda->RxState; - - return (HAL_IRDA_StateTypeDef)(temp1 | temp2); -} - -/** - * @} - */ - -/** - * @brief Configure the IRDA peripheral - * @param hirda: irda handle - * @retval None - */ -static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda) -{ - uint32_t tmpreg = 0x00000000U; - uint32_t clocksource = 0x00000000U; - - /* Check the communication parameters */ - assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); - assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength)); - assert_param(IS_IRDA_PARITY(hirda->Init.Parity)); - assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode)); - assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler)); - assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode)); - /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Configure the IRDA Word Length, Parity and transfer Mode: - Set the M bits according to hirda->Init.WordLength value - Set PCE and PS bits according to hirda->Init.Parity value - Set TE and RE bits according to hirda->Init.Mode value */ - tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ; - - MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg); - - /*-------------------------- USART CR3 Configuration -----------------------*/ - MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode); - - /*-------------------------- USART GTPR Configuration ----------------------*/ - MODIFY_REG(hirda->Instance->GTPR, (uint32_t)USART_GTPR_PSC, hirda->Init.Prescaler); - - /*-------------------------- USART BRR Configuration -----------------------*/ - IRDA_GETCLOCKSOURCE(hirda, clocksource); - switch (clocksource) - { - case IRDA_CLOCKSOURCE_PCLK1: - hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate); - break; - case IRDA_CLOCKSOURCE_PCLK2: - hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate); - break; - case IRDA_CLOCKSOURCE_HSI: - hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate); - break; - case IRDA_CLOCKSOURCE_SYSCLK: - hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate); - break; - case IRDA_CLOCKSOURCE_LSE: - hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate); - break; - default: - break; - } -} - -/** - * @brief Check the IRDA Idle State - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL status - */ -static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) -{ - uint32_t tickstart = 0U; - - /* Initialize the IRDA ErrorCode */ - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - - /* Init tickstart for timeout managment*/ - tickstart = HAL_GetTick(); - - /* Check if the Transmitter is enabled */ - if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - { - /* Wait until TEACK flag is set */ - if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK) - { - return HAL_TIMEOUT; - } - } - /* Check if the Receiver is enabled */ - if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK) - { - return HAL_TIMEOUT; - } - } - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - /* Initialize the IRDA state*/ - hirda->gState= HAL_IRDA_STATE_READY; - hirda->RxState= HAL_IRDA_STATE_READY; - - return HAL_OK; -} - -/** - * @brief This function handles IRDA Communication Timeout. - * @param hirda pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param Flag specifies the IRDA flag to check. - * @param Status The new Flag status (SET or RESET). - * @param Tickstart Tick start value - * @param Timeout Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) -{ - /* Wait until flag is set */ - while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - Tickstart ) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); - - hirda->gState= HAL_IRDA_STATE_READY; - hirda->RxState= HAL_IRDA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief Send an amount of data in non blocking mode. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL status - */ -static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) -{ - uint16_t* tmp; - - /* Check that a Tx process is ongoing */ - if(hirda->gState == HAL_IRDA_STATE_BUSY_TX) - { - if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B) - { - tmp = (uint16_t*) hirda->pTxBuffPtr; - hirda->Instance->RDR = (uint16_t)(*tmp & (uint16_t)0x01FFU); - if(hirda->Init.Parity == IRDA_PARITY_NONE) - { - hirda->pTxBuffPtr += 2U; - } - else - { - hirda->pTxBuffPtr += 1U; - } - } - else - { - hirda->Instance->RDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0x00FFU); - } - - if(--hirda->TxXferCount == 0U) - { - /* Disable the IRDA Transmit Data Register Empty Interrupt */ - CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE); - - /* Enable the IRDA Transmit Complete Interrupt */ - SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Wraps up transmission in non blocking mode. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL status - */ -static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) -{ - /* Disable the IRDA Transmit Complete Interrupt */ - CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE); - - /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); - - /* Tx process is ended, restore hirda->gState to Ready */ - hirda->gState = HAL_IRDA_STATE_READY; - - HAL_IRDA_TxCpltCallback(hirda); - - return HAL_OK; -} - -/** - * @brief Receive an amount of data in non blocking mode. - * Function called under interruption only, once - * interruptions have been enabled by HAL_IRDA_Receive_IT() - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL status - */ -static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) -{ - uint16_t* tmp; - uint16_t uhdata; - uint16_t uhMask = hirda->Mask; - - if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX) - { - uhdata = (uint16_t) READ_REG(hirda->Instance->RDR); - if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) - { - tmp = (uint16_t*) hirda->pRxBuffPtr ; - *tmp = (uint16_t)(uhdata & uhMask); - hirda->pRxBuffPtr +=2U; - } - else - { - *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); - } - - if(--hirda->RxXferCount == 0U) - { - CLEAR_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE); - - /* Disable the IRDA Parity Error Interrupt */ - CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); - - /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); - - /* Rx process is completed, restore hirda->RxState to Ready */ - hirda->RxState = HAL_IRDA_STATE_READY; - - HAL_IRDA_RxCpltCallback(hirda); - - return HAL_OK; - } - return HAL_OK; - } - else - { - /* Clear RXNE interrupt flag */ - __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST); - return HAL_BUSY; - } -} - -/** - * @brief DMA IRDA Tx transfer completed callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* DMA Normal mode*/ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) - { - hirda->TxXferCount = 0U; - - /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the IRDA CR3 register */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - - /* Enable the IRDA Transmit Complete Interrupt */ - SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE); - } - /* DMA Circular mode */ - else - { - HAL_IRDA_TxCpltCallback(hirda); - } -} - -/** - * @brief DMA IRDA receive process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - HAL_IRDA_TxHalfCpltCallback(hirda); -} - -/** - * @brief DMA IRDA Rx Transfer completed callback - * @param hdma: DMA handle - * @retval None - */ -static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* DMA Normal mode */ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) - { - hirda->RxXferCount = 0U; - - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); - - /* Disable the DMA transfer for the receiver request by setting the DMAR bit - in the IRDA CR3 register */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - - /* At end of Rx process, restore hirda->RxState to Ready */ - hirda->RxState = HAL_IRDA_STATE_READY; - } - - HAL_IRDA_RxCpltCallback(hirda); -} - -/** - * @brief DMA IRDA receive process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - HAL_IRDA_RxHalfCpltCallback(hirda); -} - -/** - * @brief DMA IRDA communication error callback - * @param hdma: DMA handle - * @retval None - */ -static void IRDA_DMAError(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - hirda->RxXferCount = 0U; - hirda->TxXferCount = 0U; - - /* Stop IRDA DMA Tx request if ongoing */ - if ( (hirda->gState == HAL_IRDA_STATE_BUSY_TX) - &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) ) - { - IRDA_EndTxTransfer(hirda); - } - - /* Stop IRDA DMA Rx request if ongoing */ - if ( (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) - &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) ) - { - IRDA_EndRxTransfer(hirda); - } - - hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; - - HAL_IRDA_ErrorCallback(hirda); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_IRDA_MODULE_ENABLED */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_iwdg.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_iwdg.c deleted file mode 100644 index c0a83c6..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_iwdg.c +++ /dev/null @@ -1,282 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_iwdg.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief IWDG HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Independent Watchdog (IWDG) peripheral: - * + Initialization and Start functions - * + IO operation functions - * - @verbatim - ============================================================================== - ##### IWDG Generic features ##### - ============================================================================== - [..] - (+) The IWDG can be started by either software or hardware (configurable - through option byte). - - (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even - if the main clock fails. - - (+) Once the IWDG is started, the LSI is forced ON and both can not be - disabled. The counter starts counting down from the reset value (0xFFF). - When it reaches the end of count value (0x000) a reset signal is - generated (IWDG reset). - - (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, - the IWDG_RLR value is reloaded in the counter and the watchdog reset is - prevented. - - (+) The IWDG is implemented in the VDD voltage domain that is still functional - in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). - IWDGRST flag in RCC_CSR register can be used to inform when an IWDG - reset occurs. - - (+) Debug mode : When the microcontroller enters debug mode (core halted), - the IWDG counter either continues to work normally or stops, depending - on DBG_IWDG_STOP configuration bit in DBG module, accessible through - __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros - - [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s - The IWDG timeout may vary due to LSI frequency dispersion. STM32F7xx - devices provide the capability to measure the LSI frequency (LSI clock - connected internally to TIM16 CH1 input capture). The measured value - can be used to have an IWDG timeout with an acceptable accuracy. - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Use IWDG using HAL_IWDG_Init() function to : - (+) Enable instance by writing Start keyword in IWDG_KEY register. LSI - clock is forced ON and IWDG counter starts downcounting. - (+) Enable write access to configuration register: IWDG_PR, IWDG_RLR & - IWDG_WINR. - (+) Configure the IWDG prescaler and counter reload value. This reload - value will be loaded in the IWDG counter each time the watchdog is - reloaded, then the IWDG will start counting down from this value. - (+) wait for status flags to be reset" - (+) Depending on window parameter: - (++) If Window Init parameter is same as Window register value, - nothing more is done but reload counter value in order to exit - function withy exact time base. - (++) Else modify Window register. This will automatically reload - watchdog counter. - - (#) Then the application program must refresh the IWDG counter at regular - intervals during normal operation to prevent an MCU reset, using - HAL_IWDG_Refresh() function. - - *** IWDG HAL driver macros list *** - ==================================== - [..] - Below the list of most used macros in IWDG HAL driver: - (+) __HAL_IWDG_START: Enable the IWDG peripheral - (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in - the reload register - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#ifdef HAL_IWDG_MODULE_ENABLED -/** @addtogroup IWDG - * @brief IWDG HAL module driver. - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup IWDG_Private_Defines IWDG Private Defines - * @{ - */ -/* Status register need 5 RC LSI divided by prescaler clock to be updated. With - higher prescaler (256), and according to LSI variation, we need to wait at - least 6 cycles so 48 ms. */ -#define HAL_IWDG_DEFAULT_TIMEOUT 48u -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup IWDG_Exported_Functions - * @{ - */ - -/** @addtogroup IWDG_Exported_Functions_Group1 - * @brief Initialization and Start functions. - * -@verbatim - =============================================================================== - ##### Initialization and Start functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the IWDG according to the specified parameters in the - IWDG_InitTypeDef of associated handle. - (+) Manage Window option. - (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog - is reloaded in order to exit function with correct time base. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the IWDG according to the specified parameters in the - * IWDG_InitTypeDef and start watchdog. Before exiting function, - * watchdog is refreshed in order to have correct time base. - * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) -{ - uint32_t tickstart; - - /* Check the IWDG handle allocation */ - if(hiwdg == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance)); - assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); - assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); - assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window)); - - /* Enable IWDG. LSI is turned on automaticaly */ - __HAL_IWDG_START(hiwdg); - - /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing - 0x5555 in KR */ - IWDG_ENABLE_WRITE_ACCESS(hiwdg); - - /* Write to IWDG registers the Prescaler & Reload values to work with */ - hiwdg->Instance->PR = hiwdg->Init.Prescaler; - hiwdg->Instance->RLR = hiwdg->Init.Reload; - - /* Check pending flag, if previous update not done, return timeout */ - tickstart = HAL_GetTick(); - - /* Wait for register to be updated */ - while(hiwdg->Instance->SR != RESET) - { - if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT) - { - return HAL_TIMEOUT; - } - } - - /* If window parameter is different than current value, modify window - register */ - if(hiwdg->Instance->WINR != hiwdg->Init.Window) - { - /* Write to IWDG WINR the IWDG_Window value to compare with. In any case, - even if window feature is disabled, Watchdog will be reloaded by writing - windows register */ - hiwdg->Instance->WINR = hiwdg->Init.Window; - } - else - { - /* Reload IWDG counter with value defined in the reload register */ - __HAL_IWDG_RELOAD_COUNTER(hiwdg); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - - -/** @addtogroup IWDG_Exported_Functions_Group2 - * @brief IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Refresh the IWDG. - -@endverbatim - * @{ - */ - - -/** - * @brief Refresh the IWDG. - * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) -{ - /* Reload IWDG counter with value defined in the reload register */ - __HAL_IWDG_RELOAD_COUNTER(hiwdg); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_IWDG_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_jpeg.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_jpeg.c deleted file mode 100644 index e8b55d3..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_jpeg.c +++ /dev/null @@ -1,3403 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_jpeg.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief JPEG HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the JPEG encoder/decoder peripheral: - * + Initialization and de-initialization functions - * + JPEG processing functions encoding and decoding - * + JPEG decoding Getting Info and encoding configuration setting - * + JPEG enable/disable header parsing functions (for decoding) - * + JPEG Input/Output Buffer configuration. - * + JPEG callback functions - * + JPEG Abort/Pause/Resume functions - * + JPEG custom quantization tables setting functions - * + IRQ handler management - * + Peripheral State and Error functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the JPEG peripheral using HAL_JPEG_Init : No initialization parameters are required. - Only the call to HAL_JPEG_Init is necessary to initialize the JPEG peripheral. - - (#) If operation is JPEG encoding use function HAL_JPEG_ConfigEncoding to set - the encoding parameters (mandatory before calling the encoding function). - the application can change the encoding parameter "ImageQuality" from - 1 to 100 to obtain a more or less quality (visual quality vs the original row image), - and inversely more or less jpg file size. - - (#) Note that for decoding operation the JPEG peripheral output data are organized in - YCbCr blocks called MCU (Minimum Coded Unit) as defioned in the JPEG specification - ISO/IEC 10918-1 standard. - It is up to the application to transform these YCbCr blocks to RGB data that can be display. - - Respectively, for Encoding operation the JPEG peripheral input should be organized - in YCbCr MCU blocks. It is up to the application to perform the necessary RGB to YCbCr - MCU blocks transformation before feeding the JPEG peripheral with data. - - (#) Use functions HAL_JPEG_Encode and HAL_JPEG_Decode to start respectively - a JPEG encoding/decoding operation in polling method (blocking). - - (#) Use functions HAL_JPEG_Encode_IT and HAL_JPEG_Decode_IT to start respectively - a JPEG encoding/decoding operation with Interrupt method (not blocking). - - (#) Use functions HAL_JPEG_Encode_DMA and HAL_JPEG_Decode_DMA to start respectively - a JPEG encoding/decoding operation with DMA method (not blocking). - - (#) Callback HAL_JPEG_InfoReadyCallback is asserted if the current operation - is a JPEG decoding to provide the application with JPEG image parameters. - This callback is asserted when the JPEG peripheral successfully parse the - JPEG header. - - (#) Callback HAL_JPEG_GetDataCallback is asserted for both encoding and decoding - operations to inform the application that the input buffer has been - consumed by the peripheral and to ask for a new data chunk if the operation - (encoding/decoding) has not been complete yet. - - This CallBack should be implemented in the application side. It should - call the function HAL_JPEG_ConfigInputBuffer if new input data are available, - or call HAL_JPEG_Pause with parameter XferSelection set to "JPEG_PAUSE_RESUME_INPUT" - to inform the JPEG HAL driver that the ongoing operation shall pause waiting for the - application to provide a new input data chunk. - Once the application succeed getting new data and if the input has been paused, - the application can call the function HAL_JPEG_ConfigInputBuffer to set the new - input buffer and size, then resume the JPEG HAL input by calling new function HAL_JPEG_Resume. - If the application has ended feeding the HAL JPEG with input data (no more input data), the application - Should call the function “HAL_JPEG_ConfigInputBuffer” (within the callback HAL_JPEG_GetDataCallback) - with the parameter “InDataLength” set to zero. - - The mechanism of HAL_JPEG_ConfigInputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows - to the application to provide the input data (for encoding or decoding) by chunks. - If the new input data chunk is not available (because data should be read from an input file - for example) the application can pause the JPEG input (using function HAL_JPEG_Pause) - Once the new input data chunk is available ( read from a file for example), the application - can call the function "HAL_JPEG_ConfigInputBuffer" to provide the HAL with the new chunk - then resume the JPEG HAL input by calling function "HAL_JPEG_Resume". - - The application can call functions “HAL_JPEG_ConfigInputBuffer “ then "HAL_JPEG_Resume". - any time (outside the HAL_JPEG_GetDataCallback) Once the new input chunk data available. - However, to keep data coherency, the function “HAL_JPEG_Pause” must be imperatively called - (if necessary) within the callback “HAL_JPEG_GetDataCallback”, i.e when the HAL JPEG has ended - Transferring the previous chunk buffer to the JPEG peripheral. - - (#) Callback HAL_JPEG_DataReadyCallback is asserted when the HAL JPEG driver - has filled the given output buffer with the given size. - - This CallBack should be implemented in the application side. It should - call the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver - with the new output buffer location and size to be used to store next data chunk. - if the application is not ready to provide the output chunk location then it can - call the function "HAL_JPEG_Pause" with parameter XferSelection set to "JPEG_PAUSE_RESUME_OUTPUT" - to inform the JPEG HAL driver that it shall pause output data. Once the application - is ready to receive the new data chunk (output buffer location free or available) it should call - the function "HAL_JPEG_ConfigOutputBuffer" to provide the HAL JPEG driver - with the new output chunk buffer location and size, then call "HAL_JPEG_Resume" - to inform the HAL that it shall resume outputting data in the given output buffer. - - The mechanism of HAL_JPEG_ConfigOutputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows - the application to receive data from the JPEG peripheral by chunks. when a chunk - is received, the application can pause the HAL JPEG output data to be able to process - these received data (YCbCr to RGB conversion in case of decoding or data storage in case - of encoding). - - The application can call functions “HAL_JPEG_ ConfigOutputBuffer“ then "HAL_JPEG_Resume". - any time (outside the HAL_JPEG_ DataReadyCallback) Once the output data buffer is free to use. - However, to keep data coherency, the function “HAL_JPEG_Pause” must be imperatively called - (if necessary) within the callback “HAL_JPEG_ DataReadyCallback”, i.e when the HAL JPEG has ended - Transferring the previous chunk buffer from the JPEG peripheral to the application. - - (#) Callback HAL_JPEG_EncodeCpltCallback is asserted when the HAL JPEG driver has - ended the current JPEG encoding operation, and all output data has been transmitted - to the application. - - (#) Callback HAL_JPEG_DecodeCpltCallback is asserted when the HAL JPEG driver has - ended the current JPEG decoding operation. and all output data has been transmitted - to the application. - - (#) Callback HAL_JPEG_ErrorCallback is asserted when an error occurred during - the current operation. the application can call the function "HAL_JPEG_GetError" - to retrieve the error codes. - - (#) By default the HAL JPEG driver uses the default quantization tables - as provide in the JPEG specification (ISO/IEC 10918-1 standard) for encoding. - User can change these default tables if necessary using the function "HAL_JPEG_SetUserQuantTables" - Note that for decoding the quantization tables are automatically extracted from - the JPEG header. - - (#) To control JPEG state you can use the following function: HAL_JPEG_GetState() - - *** JPEG HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in JPEG HAL driver. - - (+) __HAL_JPEG_RESET_HANDLE_STATE : Reset JPEG handle state. - (+) __HAL_JPEG_ENABLE : Enable the JPEG peripheral. - (+) __HAL_JPEG_DISABLE : Disable the JPEG peripheral. - (+) __HAL_JPEG_GET_FLAG : Check the specified JPEG status flag. - (+) __HAL_JPEG_CLEAR_FLAG : Clear the specified JPEG status flag. - (+) __HAL_JPEG_ENABLE_IT : Enable the specified JPEG Interrupt. - (+) __HAL_JPEG_DISABLE_IT : Disable the specified JPEG Interrupt. - (+) __HAL_JPEG_GET_IT_SOURCE : returns the state of the specified JPEG Interrupt (Enabled or disabled). - - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup JPEG JPEG - * @brief JPEG HAL module driver. - * @{ - */ - -#ifdef HAL_JPEG_MODULE_ENABLED - -#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - -/* Private define ------------------------------------------------------------*/ -/** @addtogroup JPEG_Private_Constants - * @{ - */ -#define JPEG_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */ -#define JPEG_AC_HUFF_TABLE_SIZE ((uint32_t)162U) /* Huffman AC table size : 162 codes*/ -#define JPEG_DC_HUFF_TABLE_SIZE ((uint32_t)12U) /* Huffman AC table size : 12 codes*/ - -#define JPEG_FIFO_SIZE ((uint32_t)8U) /* JPEG Input/Output HW FIFO size in words*/ - -#define JPEG_INTERRUPT_MASK ((uint32_t)0x0000007EU) /* JPEG Interrupt Mask*/ - -#define JPEG_DMA_MASK ((uint32_t)0x00001800U) /* JPEG DMA request Mask*/ -#define JPEG_DMA_IDMA ((uint32_t)JPEG_CR_IDMAEN) /* DMA request for the input FIFO */ -#define JPEG_DMA_ODMA ((uint32_t)JPEG_CR_ODMAEN) /* DMA request for the output FIFO */ - -#define JPEG_CONTEXT_ENCODE ((uint32_t)0x00000001U) /* JPEG context : operation is encoding*/ -#define JPEG_CONTEXT_DECODE ((uint32_t)0x00000002U) /* JPEG context : operation is decoding*/ -#define JPEG_CONTEXT_OPERATION_MASK ((uint32_t)0x00000003U) /* JPEG context : operation Mask */ - -#define JPEG_CONTEXT_POLLING ((uint32_t)0x00000004U) /* JPEG context : Transfer use Polling */ -#define JPEG_CONTEXT_IT ((uint32_t)0x00000008U) /* JPEG context : Transfer use Interrupt */ -#define JPEG_CONTEXT_DMA ((uint32_t)0x0000000CU) /* JPEG context : Transfer use DMA */ -#define JPEG_CONTEXT_METHOD_MASK ((uint32_t)0x0000000CU) /* JPEG context : Transfer Mask */ - - -#define JPEG_CONTEXT_CONF_ENCODING ((uint32_t)0x00000100U) /* JPEG context : encoding config done */ - -#define JPEG_CONTEXT_PAUSE_INPUT ((uint32_t)0x00001000U) /* JPEG context : Pause Input */ -#define JPEG_CONTEXT_PAUSE_OUTPUT ((uint32_t)0x00002000U) /* JPEG context : Pause Output */ - -#define JPEG_CONTEXT_CUSTOM_TABLES ((uint32_t)0x00004000U) /* JPEG context : Use custom quantization tables */ - -#define JPEG_CONTEXT_ENDING_DMA ((uint32_t)0x00008000U) /* JPEG context : ending with DMA in progress */ - -#define JPEG_PROCESS_ONGOING ((uint32_t)0x00000000U) /* Process is on going */ -#define JPEG_PROCESS_DONE ((uint32_t)0x00000001U) /* Process is done (ends) */ -/** - * @} - */ - -/* Private typedef -----------------------------------------------------------*/ -/** @addtogroup JPEG_Private_Types - * @{ - */ - -/* - JPEG Huffman Table Structure definition : - This implementation of Huffman table structure is compliant with ISO/IEC 10918-1 standard , Annex C Huffman Table specification - */ -typedef struct -{ - /* These two fields directly represent the contents of a JPEG DHT marker */ - uint8_t Bits[16]; /*!< bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C */ - - uint8_t HuffVal[162]; /*!< The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C */ - - -}JPEG_ACHuffTableTypeDef; - -typedef struct -{ - /* These two fields directly represent the contents of a JPEG DHT marker */ - uint8_t Bits[16]; /*!< bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C */ - - uint8_t HuffVal[12]; /*!< The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C */ - - -}JPEG_DCHuffTableTypeDef; - -typedef struct -{ - uint8_t CodeLength[JPEG_AC_HUFF_TABLE_SIZE]; /*!< Code length */ - - uint32_t HuffmanCode[JPEG_AC_HUFF_TABLE_SIZE]; /*!< HuffmanCode */ - -}JPEG_AC_HuffCodeTableTypeDef; - -typedef struct -{ - uint8_t CodeLength[JPEG_DC_HUFF_TABLE_SIZE]; /*!< Code length */ - - uint32_t HuffmanCode[JPEG_DC_HUFF_TABLE_SIZE]; /*!< HuffmanCode */ - -}JPEG_DC_HuffCodeTableTypeDef; -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @addtogroup JPEG_Private_Macros - * @{ - */ -#define JPEG_ENABLE_DMA(__HANDLE__,__DMA__) ((__HANDLE__)->Instance->CR |= ((__DMA__) & JPEG_DMA_MASK)) -/*note : To disable a DMA request we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits - located in the same DMA request enable register (CR register). */ -#define JPEG_DISABLE_DMA(__HANDLE__,__DMA__) MODIFY_REG((__HANDLE__)->Instance->CR, ((__DMA__) & JPEG_DMA_MASK), 0) -/** - * @} - */ - - -/* Private variables ---------------------------------------------------------*/ -/** @addtogroup JPEG_Private_Variables - * @{ - */ - -static const JPEG_DCHuffTableTypeDef JPEG_DCLUM_HuffTable = -{ - { 0, 1, 5, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 }, /*Bits*/ - - { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb } /*HUFFVAL */ - -}; - -static const JPEG_DCHuffTableTypeDef JPEG_DCCHROM_HuffTable = -{ - { 0, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 }, /*Bits*/ - - { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb } /*HUFFVAL */ -}; - -static const JPEG_ACHuffTableTypeDef JPEG_ACLUM_HuffTable = -{ - { 0, 2, 1, 3, 3, 2, 4, 3, 5, 5, 4, 4, 0, 0, 1, 0x7d }, /*Bits*/ - - { 0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, /*HUFFVAL */ - 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, - 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08, - 0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0, - 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16, - 0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28, - 0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, - 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, - 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, - 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, - 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, - 0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, - 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, - 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, - 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, - 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5, - 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4, - 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2, - 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, - 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, - 0xf9, 0xfa } -}; - -static const JPEG_ACHuffTableTypeDef JPEG_ACCHROM_HuffTable = -{ - { 0, 2, 1, 2, 4, 4, 3, 4, 7, 5, 4, 4, 0, 1, 2, 0x77 }, /*Bits*/ - - { 0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, /*HUFFVAL */ - 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71, - 0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91, - 0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33, 0x52, 0xf0, - 0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24, 0x34, - 0xe1, 0x25, 0xf1, 0x17, 0x18, 0x19, 0x1a, 0x26, - 0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37, 0x38, - 0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, - 0x49, 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, - 0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, - 0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, - 0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, - 0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, - 0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, - 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, - 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, - 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, - 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, - 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, - 0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, - 0xf9, 0xfa } -}; - - -/* - These are the sample quantization tables given in JPEG spec ISO/IEC 10918-1 standard , section K.1. -*/ -static const uint8_t JPEG_LUM_QuantTable[JPEG_QUANT_TABLE_SIZE] = -{ - 16, 11, 10, 16, 24, 40, 51, 61, - 12, 12, 14, 19, 26, 58, 60, 55, - 14, 13, 16, 24, 40, 57, 69, 56, - 14, 17, 22, 29, 51, 87, 80, 62, - 18, 22, 37, 56, 68, 109, 103, 77, - 24, 35, 55, 64, 81, 104, 113, 92, - 49, 64, 78, 87, 103, 121, 120, 101, - 72, 92, 95, 98, 112, 100, 103, 99 -}; -static const uint8_t JPEG_CHROM_QuantTable[JPEG_QUANT_TABLE_SIZE] = -{ - 17, 18, 24, 47, 99, 99, 99, 99, - 18, 21, 26, 66, 99, 99, 99, 99, - 24, 26, 56, 99, 99, 99, 99, 99, - 47, 66, 99, 99, 99, 99, 99, 99, - 99, 99, 99, 99, 99, 99, 99, 99, - 99, 99, 99, 99, 99, 99, 99, 99, - 99, 99, 99, 99, 99, 99, 99, 99, - 99, 99, 99, 99, 99, 99, 99, 99 -}; - -static const uint8_t JPEG_ZIGZAG_ORDER[JPEG_QUANT_TABLE_SIZE] = -{ - 0, 1, 8, 16, 9, 2, 3, 10, - 17, 24, 32, 25, 18, 11, 4, 5, - 12, 19, 26, 33, 40, 48, 41, 34, - 27, 20, 13, 6, 7, 14, 21, 28, - 35, 42, 49, 56, 57, 50, 43, 36, - 29, 22, 15, 23, 30, 37, 44, 51, - 58, 59, 52, 45, 38, 31, 39, 46, - 53, 60, 61, 54, 47, 55, 62, 63 -}; -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup JPEG_Private_Functions_Prototypes - * @{ - */ - -static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK); -static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable); -static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable); -static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, uint32_t *DCTableAddress); -static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, uint32_t *ACTableAddress); -static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1); -static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1); -static HAL_StatusTypeDef JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, uint32_t *QTableAddress); -static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg); -static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg); -static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg); - -static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg); -static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg); -static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords); -static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords); -static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg); - -static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg); -static uint32_t JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg); -static uint32_t JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg); -static void JPEG_DMAOutCpltCallback(DMA_HandleTypeDef *hdma); -static void JPEG_DMAInCpltCallback(DMA_HandleTypeDef *hdma); -static void JPEG_DMAErrorCallback(DMA_HandleTypeDef *hdma); -static void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma) ; -/** - * @} - */ - -/** @defgroup JPEG_Exported_Functions JPEG Exported Functions - * @{ - */ - -/** @defgroup JPEG_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions. - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the JPEG peripheral and creates the associated handle - (+) DeInitialize the JPEG peripheral - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the JPEG according to the specified - * parameters in the JPEG_InitTypeDef and creates the associated handle. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg) -{ - /*Note : these intermediate variables are used to avoid MISRA warning - regarding rule 11.5 */ - uint32_t acLum_huffmanTableAddr = (uint32_t)(&JPEG_ACLUM_HuffTable); - uint32_t dcLum_huffmanTableAddr = (uint32_t)(&JPEG_DCLUM_HuffTable); - uint32_t acChrom_huffmanTableAddr = (uint32_t)(&JPEG_ACCHROM_HuffTable); - uint32_t dcChrom_huffmanTableAddr = (uint32_t)(&JPEG_DCCHROM_HuffTable); - - /* Check the JPEG handle allocation */ - if(hjpeg == NULL) - { - return HAL_ERROR; - } - - if(hjpeg->State == HAL_JPEG_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hjpeg->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK */ - HAL_JPEG_MspInit(hjpeg); - } - - /* Change the JPEG state */ - hjpeg->State = HAL_JPEG_STATE_BUSY; - - /* Start the JPEG Core*/ - __HAL_JPEG_ENABLE(hjpeg); - - /* Stop the JPEG encoding/decoding process*/ - hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; - - /* Disable All Interrupts */ - __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK); - - /* Disable All DMA requests */ - JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_MASK); - - /* Flush input and output FIFOs*/ - hjpeg->Instance->CR |= JPEG_CR_IFF; - hjpeg->Instance->CR |= JPEG_CR_OFF; - - /* Clear all flags */ - __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL); - - hjpeg->QuantTable0 = (uint8_t *)JPEG_LUM_QuantTable; - hjpeg->QuantTable1 = (uint8_t *)JPEG_CHROM_QuantTable; - hjpeg->QuantTable2 = NULL; - hjpeg->QuantTable3 = NULL; - - /* init the default Huffman tables*/ - if(JPEG_Set_HuffEnc_Mem(hjpeg, (JPEG_ACHuffTableTypeDef *)acLum_huffmanTableAddr, (JPEG_DCHuffTableTypeDef *)dcLum_huffmanTableAddr, (JPEG_ACHuffTableTypeDef *)acChrom_huffmanTableAddr, (JPEG_DCHuffTableTypeDef *)dcChrom_huffmanTableAddr) != HAL_OK) - { - hjpeg->ErrorCode = HAL_JPEG_ERROR_HUFF_TABLE; - - return HAL_ERROR; - } - - /* Enable header processing*/ - hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR; - - /* Reset JpegInCount and JpegOutCount */ - hjpeg->JpegInCount = 0; - hjpeg->JpegOutCount = 0; - - /* Change the JPEG state */ - hjpeg->State = HAL_JPEG_STATE_READY; - - /* Reset the JPEG ErrorCode */ - hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE; - - /*Clear the context filelds*/ - hjpeg->Context = 0; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief DeInitializes the JPEG peripheral. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg) -{ - /* Check the JPEG handle allocation */ - if(hjpeg == NULL) - { - return HAL_ERROR; - } - - /* DeInit the low level hardware: CLOCK, NVIC.*/ - HAL_JPEG_MspDeInit(hjpeg); - - /* Change the JPEG state */ - hjpeg->State = HAL_JPEG_STATE_BUSY; - - /* Reset the JPEG ErrorCode */ - hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE; - - /* Reset JpegInCount and JpegOutCount */ - hjpeg->JpegInCount = 0; - hjpeg->JpegOutCount = 0; - - /* Change the JPEG state */ - hjpeg->State = HAL_JPEG_STATE_RESET; - - /*Clear the context fields*/ - hjpeg->Context = 0; - - /* Release Lock */ - __HAL_UNLOCK(hjpeg); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the JPEG MSP. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ -__weak void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hjpeg); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_JPEG_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes JPEG MSP. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ -__weak void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hjpeg); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_JPEG_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup JPEG_Exported_Functions_Group2 Configuration functions - * @brief JPEG Configuration functions. - * -@verbatim - ============================================================================== - ##### Configuration functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) HAL_JPEG_ConfigEncoding() : JPEG encoding configuration - (+) HAL_JPEG_GetInfo() : Extract the image configuration from the JPEG header during the decoding - (+) HAL_JPEG_EnableHeaderParsing() : Enable JPEG Header parsing for decoding - (+) HAL_JPEG_DisableHeaderParsing() : Disable JPEG Header parsing for decoding - (+) HAL_JPEG_SetUserQuantTables : Modify the default Quantization tables used for JPEG encoding. - -@endverbatim - * @{ - */ - -/** - * @brief Set the JPEG encoding configuration. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param pConf: pointer to a JPEG_ConfTypeDef structure that contains - * the encoding configuration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf) -{ - uint32_t error = HAL_OK; - uint32_t numberMCU, hfactor, vfactor,hMCU, vMCU; - - /* Check the JPEG handle allocation */ - if( (hjpeg == NULL) || (pConf == NULL) ) - { - return HAL_ERROR; - } - else - { - /* Check the parameters */ - assert_param(IS_JPEG_COLORSPACE(pConf->ColorSpace)); - assert_param(IS_JPEG_CHROMASUBSAMPLING(pConf->ChromaSubsampling)); - assert_param(IS_JPEG_IMAGE_QUALITY(pConf->ImageQuality)); - - /* Process Locked */ - __HAL_LOCK(hjpeg); - - if(hjpeg->State == HAL_JPEG_STATE_READY) - { - hjpeg->State = HAL_JPEG_STATE_BUSY; - - hjpeg->Conf.ColorSpace = pConf->ColorSpace; - hjpeg->Conf.ChromaSubsampling = pConf->ChromaSubsampling; - hjpeg->Conf.ImageHeight = pConf->ImageHeight; - hjpeg->Conf.ImageWidth = pConf->ImageWidth; - hjpeg->Conf.ImageQuality = pConf->ImageQuality; - - /* Reset the Color Space : by default only one quantization table is used*/ - hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_COLORSPACE; - - /* Set Number of color components*/ - if(hjpeg->Conf.ColorSpace == JPEG_GRAYSCALE_COLORSPACE) - { - /*Gray Scale is only one component 8x8 blocks i.e 4:4:4*/ - hjpeg->Conf.ChromaSubsampling = JPEG_444_SUBSAMPLING; - - JPEG_SetColorGrayScale(hjpeg); - /* Set quantization table 0*/ - error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (uint32_t *)(hjpeg->Instance->QMEM0)); - } - else if(hjpeg->Conf.ColorSpace == JPEG_YCBCR_COLORSPACE) - { - /* - Set the Color Space for YCbCr : 2 quantization tables are used - one for Luminance(Y) and one for both Chrominances (Cb & Cr) - */ - hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_0; - - JPEG_SetColorYCBCR(hjpeg); - - /* Set quantization table 0*/ - error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (uint32_t *)(hjpeg->Instance->QMEM0)); - /*By default quantization table 0 for component 0 and quantization table 1 for both components 1 and 2*/ - error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (uint32_t *)(hjpeg->Instance->QMEM1)); - - if((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0) /*Use user customized quantization tables , 1 table per component*/ - { - /* use 3 quantization tables , one for each component*/ - hjpeg->Instance->CONFR1 &= (~JPEG_CONFR1_COLORSPACE); - hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_1; - - error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (uint32_t *)(hjpeg->Instance->QMEM2)); - - /*Use Quantization 1 table for component 1*/ - hjpeg->Instance->CONFR5 &= (~JPEG_CONFR6_QT); - hjpeg->Instance->CONFR5 |= JPEG_CONFR5_QT_0; - - /*Use Quantization 2 table for component 2*/ - hjpeg->Instance->CONFR6 &= (~JPEG_CONFR6_QT); - hjpeg->Instance->CONFR6 |= JPEG_CONFR6_QT_1; - } - } - else if(hjpeg->Conf.ColorSpace == JPEG_CMYK_COLORSPACE) - { - JPEG_SetColorCMYK(hjpeg); - - /* Set quantization table 0*/ - error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (uint32_t *)(hjpeg->Instance->QMEM0)); - /*By default quantization table 0 for All components*/ - - if((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0) /*Use user customized quantization tables , 1 table per component*/ - { - /* use 4 quantization tables , one for each component*/ - hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE; - - error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (uint32_t *)(hjpeg->Instance->QMEM1)); - error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (uint32_t *)(hjpeg->Instance->QMEM2)); - error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable3, (uint32_t *)(hjpeg->Instance->QMEM3)); - - /*Use Quantization 1 table for component 1*/ - hjpeg->Instance->CONFR5 |= JPEG_CONFR5_QT_0; - - /*Use Quantization 2 table for component 2*/ - hjpeg->Instance->CONFR6 |= JPEG_CONFR6_QT_1; - - /*Use Quantization 3 table for component 3*/ - hjpeg->Instance->CONFR7 |= JPEG_CONFR7_QT; - } - } - - if(error != HAL_OK) - { - hjpeg->ErrorCode = HAL_JPEG_ERROR_QUANT_TABLE; - - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /* Set the JPEG State to ready */ - hjpeg->State = HAL_JPEG_STATE_READY; - - return HAL_ERROR; - } - /* Set the image size*/ - hjpeg->Instance->CONFR1 |= ((hjpeg->Conf.ImageHeight & 0x0000FFFF) << 16); /* set the number of lines*/ - hjpeg->Instance->CONFR3 |= ((hjpeg->Conf.ImageWidth & 0x0000FFFF) << 16); /* set the number of pixels per line*/ - - if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) /* 4:2:0*/ - { - hfactor = 16; - vfactor = 16; - } - else if(hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) /* 4:2:2*/ - { - hfactor = 16; - vfactor = 8; - } - else /* Default is 8x8 MCU, 4:4:4*/ - { - hfactor = 8; - vfactor = 8; - } - - hMCU = (hjpeg->Conf.ImageWidth / hfactor); - if((hjpeg->Conf.ImageWidth % hfactor) != 0) - { - hMCU++; /*+1 for horizontal incomplete MCU */ - } - - vMCU = (hjpeg->Conf.ImageHeight / vfactor); - if((hjpeg->Conf.ImageHeight % vfactor) != 0) - { - vMCU++; /*+1 for vertical incomplete MCU */ - } - - numberMCU = (hMCU * vMCU) - 1; /* Bit Field JPEG_CONFR2_NMCU shall be set to NB_MCU - 1*/ - /* Set the number of MCU*/ - hjpeg->Instance->CONFR2 = (numberMCU & JPEG_CONFR2_NMCU); - - hjpeg->Context |= JPEG_CONTEXT_CONF_ENCODING; - - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /* Set the JPEG State to ready */ - hjpeg->State = HAL_JPEG_STATE_READY; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /* Return function status */ - return HAL_BUSY; - } - } -} - -/** - * @brief Extract the image configuration from the JPEG header during the decoding - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param pInfo: pointer to a JPEG_ConfTypeDef structure that contains - * The JPEG decoded header informations - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo) -{ - uint32_t yblockNb, cBblockNb, cRblockNb; - - /* Check the JPEG handle allocation */ - if((hjpeg == NULL) || (pInfo == NULL)) - { - return HAL_ERROR; - } - - /*Read the conf parameters */ - if((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF_1) - { - pInfo->ColorSpace = JPEG_YCBCR_COLORSPACE; - } - else if((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == 0) - { - pInfo->ColorSpace = JPEG_GRAYSCALE_COLORSPACE; - } - else if((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF) - { - pInfo->ColorSpace = JPEG_CMYK_COLORSPACE; - } - - pInfo->ImageHeight = (hjpeg->Instance->CONFR1 & 0xFFFF0000U) >> 16; - pInfo->ImageWidth = (hjpeg->Instance->CONFR3 & 0xFFFF0000U) >> 16; - - if((pInfo->ColorSpace == JPEG_YCBCR_COLORSPACE) || (pInfo->ColorSpace == JPEG_CMYK_COLORSPACE)) - { - yblockNb = (hjpeg->Instance->CONFR4 & JPEG_CONFR4_NB) >> 4; - cBblockNb = (hjpeg->Instance->CONFR5 & JPEG_CONFR5_NB) >> 4; - cRblockNb = (hjpeg->Instance->CONFR6 & JPEG_CONFR6_NB) >> 4; - - if((yblockNb == 1) && (cBblockNb == 0) && (cRblockNb == 0)) - { - pInfo->ChromaSubsampling = JPEG_422_SUBSAMPLING; /*16x8 block*/ - } - else if((yblockNb == 0) && (cBblockNb == 0) && (cRblockNb == 0)) - { - pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING; - } - else if((yblockNb == 3) && (cBblockNb == 0) && (cRblockNb == 0)) - { - pInfo->ChromaSubsampling = JPEG_420_SUBSAMPLING; - } - else /*Default is 4:4:4*/ - { - pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING; - } - } - else - { - pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING; - } - - pInfo->ImageQuality = JPEG_GetQuality(hjpeg); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Enable JPEG Header parsing for decoding - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for the JPEG. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg) -{ - /* Process locked */ - __HAL_LOCK(hjpeg); - - if(hjpeg->State == HAL_JPEG_STATE_READY) - { - /* Change the JPEG state */ - hjpeg->State = HAL_JPEG_STATE_BUSY; - - /* Enable header processing*/ - hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR; - - /* Process unlocked */ - __HAL_UNLOCK(hjpeg); - - /* Change the JPEG state */ - hjpeg->State = HAL_JPEG_STATE_READY; - - return HAL_OK; - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_BUSY; - } -} - -/** - * @brief Disable JPEG Header parsing for decoding - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for the JPEG. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg) -{ - /* Process locked */ - __HAL_LOCK(hjpeg); - - if(hjpeg->State == HAL_JPEG_STATE_READY) - { - /* Change the JPEG state */ - hjpeg->State = HAL_JPEG_STATE_BUSY; - - /* Disable header processing*/ - hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_HDR; - - /* Process unlocked */ - __HAL_UNLOCK(hjpeg); - - /* Change the JPEG state */ - hjpeg->State = HAL_JPEG_STATE_READY; - - return HAL_OK; - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_BUSY; - } -} - -/** - * @brief Modify the default Quantization tables used for JPEG encoding. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param QTable0 : pointer to uint8_t , define the user quantification table for color component 1. - * If NULL assume no need to update the table and no error return - * @param QTable1 : pointer to uint8_t , define the user quantification table for color component 2. - * If NULL assume no need to update the table and no error return. - * @param QTable2 : pointer to uint8_t , define the user quantification table for color component 3, - * If NULL assume no need to update the table and no error return. - * @param QTable3 : pointer to uint8_t , define the user quantification table for color component 4. - * If NULL assume no need to update the table and no error return. - * - * @retval HAL status - */ - - -HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, uint8_t *QTable2, uint8_t *QTable3) -{ - /* Process Locked */ - __HAL_LOCK(hjpeg); - - if(hjpeg->State == HAL_JPEG_STATE_READY) - { - /* Change the DMA state */ - hjpeg->State = HAL_JPEG_STATE_BUSY; - - hjpeg->Context |= JPEG_CONTEXT_CUSTOM_TABLES; - - hjpeg->QuantTable0 = QTable0; - hjpeg->QuantTable1 = QTable1; - hjpeg->QuantTable2 = QTable2; - hjpeg->QuantTable3 = QTable3; - - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /* Change the DMA state */ - hjpeg->State = HAL_JPEG_STATE_READY; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_BUSY; - } -} - -/** - * @} - */ - -/** @defgroup JPEG_Exported_Functions_Group3 encoding/decoding processing functions - * @brief processing functions. - * -@verbatim - ============================================================================== - ##### JPEG processing functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) HAL_JPEG_Encode() : JPEG encoding with polling process - (+) HAL_JPEG_Decode() : JPEG decoding with polling process - (+) HAL_JPEG_Encode_IT() : JPEG encoding with interrupt process - (+) HAL_JPEG_Decode_IT() : JPEG decoding with interrupt process - (+) HAL_JPEG_Encode_DMA() : JPEG encoding with DMA process - (+) HAL_JPEG_Decode_DMA() : JPEG decoding with DMA process - (+) HAL_JPEG_Pause() : Pause the Input/Output processing - (+) HAL_JPEG_Resume() : Resume the JPEG Input/Output processing - (+) HAL_JPEG_ConfigInputBuffer() : Config Encoding/Decoding Input Buffer - (+) HAL_JPEG_ConfigOutputBuffer() : Config Encoding/Decoding Output Buffer - (+) HAL_JPEG_Abort() : Aborts the JPEG Encoding/Decoding - -@endverbatim - * @{ - */ - -/** - * @brief Starts JPEG encoding with polling processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param pDataInMCU: Pointer to the Input buffer - * @param InDataLength: size in bytes Input buffer - * @param pDataOut: Pointer to the jpeg output data buffer - * @param OutDataLength: size in bytes of the Output buffer - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param((InDataLength >= 4)); - assert_param((OutDataLength >= 4)); - - /* Check In/out buffer allocation and size */ - if((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL) || \ - (InDataLength == 0) || (OutDataLength == 0)) - { - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hjpeg); - - if(hjpeg->State != HAL_JPEG_STATE_READY) - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_BUSY; - } - - if(hjpeg->State == HAL_JPEG_STATE_READY) - { - if((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING ) - { - /*Change JPEG state*/ - hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING; - - /*Set the Context to Encode with Polling*/ - hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); - hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_POLLING); - - /* Get tick */ - tickstart = HAL_GetTick(); - /*In/Out Data length must be multiple of 4 Bytes (1 word)*/ - InDataLength = InDataLength - (InDataLength % 4); - OutDataLength = OutDataLength - (OutDataLength % 4); - - /*Store In/out buffers pointers and size*/ - hjpeg->pJpegInBuffPtr = pDataInMCU; - hjpeg->pJpegOutBuffPtr = pDataOut; - hjpeg->InDataLength = InDataLength; - hjpeg->OutDataLength = OutDataLength; - - /*Reset In/out data counter */ - hjpeg->JpegInCount = 0; - hjpeg->JpegOutCount = 0; - - /*Init decoding process*/ - JPEG_Init_Process(hjpeg); - - /*JPEG data processing : In/Out FIFO transfer*/ - while((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING)) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - - /* Update error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /*Change JPEG state*/ - hjpeg->State= HAL_JPEG_STATE_READY; - - return HAL_TIMEOUT; - } - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /*Change JPEG state*/ - hjpeg->State= HAL_JPEG_STATE_READY; - - }else - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_ERROR; - } - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts JPEG decoding with polling processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param pDataIn: Pointer to the input data buffer - * @param InDataLength: size in bytes Input buffer - * @param pDataOutMCU: Pointer to the Output data buffer - * @param OutDataLength: size in bytes of the Output buffer - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param((InDataLength >= 4)); - assert_param((OutDataLength >= 4)); - - /* Check In/out buffer allocation and size */ - if((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL) || \ - (InDataLength == 0) || (OutDataLength == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hjpeg); - - /* Get tick */ - tickstart = HAL_GetTick(); - - if(hjpeg->State == HAL_JPEG_STATE_READY) - { - /*Change JPEG state*/ - hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING; - - /*Set the Context to Decode with Polling*/ - /*Set the Context to Encode with Polling*/ - hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); - hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_POLLING); - - /*In/Out Data length must be multiple of 4 Bytes (1 word)*/ - InDataLength = InDataLength - (InDataLength % 4); - OutDataLength = OutDataLength - (OutDataLength % 4); - - /*Store In/out buffers pointers and size*/ - hjpeg->pJpegInBuffPtr = pDataIn; - hjpeg->pJpegOutBuffPtr = pDataOutMCU; - hjpeg->InDataLength = InDataLength; - hjpeg->OutDataLength = OutDataLength; - - /*Reset In/out data counter */ - hjpeg->JpegInCount = 0; - hjpeg->JpegOutCount = 0; - - /*Init decoding process*/ - JPEG_Init_Process(hjpeg); - - /*JPEG data processing : In/Out FIFO transfer*/ - while((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING)) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - - /* Update error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /*Change JPEG state*/ - hjpeg->State= HAL_JPEG_STATE_READY; - - return HAL_TIMEOUT; - } - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /*Change JPEG state*/ - hjpeg->State= HAL_JPEG_STATE_READY; - - }else - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_BUSY; - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts JPEG encoding with interrupt processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param pDataInMCU: Pointer to the Input buffer - * @param InDataLength: size in bytes Input buffer - * @param pDataOut: Pointer to the jpeg output data buffer - * @param OutDataLength: size in bytes of the Output buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength) -{ - /* Check the parameters */ - assert_param((InDataLength >= 4)); - assert_param((OutDataLength >= 4)); - - /* Check In/out buffer allocation and size */ - if((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL) || \ - (InDataLength == 0) || (OutDataLength == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hjpeg); - - if(hjpeg->State != HAL_JPEG_STATE_READY) - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_BUSY; - } - else - { - if((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING ) - { - /*Change JPEG state*/ - hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING; - - /*Set the Context to Encode with IT*/ - hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); - hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_IT); - - /*In/Out Data length must be multiple of 4 Bytes (1 word)*/ - InDataLength = InDataLength - (InDataLength % 4); - OutDataLength = OutDataLength - (OutDataLength % 4); - - /*Store In/out buffers pointers and size*/ - hjpeg->pJpegInBuffPtr = pDataInMCU; - hjpeg->pJpegOutBuffPtr = pDataOut; - hjpeg->InDataLength = InDataLength; - hjpeg->OutDataLength = OutDataLength; - - /*Reset In/out data counter */ - hjpeg->JpegInCount = 0; - hjpeg->JpegOutCount = 0; - - /*Init decoding process*/ - JPEG_Init_Process(hjpeg); - - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_ERROR; - } - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts JPEG decoding with interrupt processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param pDataIn: Pointer to the input data buffer - * @param InDataLength: size in bytes Input buffer - * @param pDataOutMCU: Pointer to the Output data buffer - * @param OutDataLength: size in bytes of the Output buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength) -{ - /* Check the parameters */ - assert_param((InDataLength >= 4)); - assert_param((OutDataLength >= 4)); - - /* Check In/out buffer allocation and size */ - if((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL) || \ - (InDataLength == 0) || (OutDataLength == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hjpeg); - - if(hjpeg->State == HAL_JPEG_STATE_READY) - { - /*Change JPEG state*/ - hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING; - - /*Set the Context to Decode with IT*/ - hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); - hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_IT); - - /*In/Out Data length must be multiple of 4 Bytes (1 word)*/ - InDataLength = InDataLength - (InDataLength % 4); - OutDataLength = OutDataLength - (OutDataLength % 4); - - /*Store In/out buffers pointers and size*/ - hjpeg->pJpegInBuffPtr = pDataIn; - hjpeg->pJpegOutBuffPtr = pDataOutMCU; - hjpeg->InDataLength = InDataLength; - hjpeg->OutDataLength = OutDataLength; - - /*Reset In/out data counter */ - hjpeg->JpegInCount = 0; - hjpeg->JpegOutCount = 0; - - /*Init decoding process*/ - JPEG_Init_Process(hjpeg); - - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_BUSY; - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts JPEG encoding with DMA processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param pDataInMCU: Pointer to the Input buffer - * @param InDataLength: size in bytes Input buffer - * @param pDataOut: Pointer to the jpeg output data buffer - * @param OutDataLength: size in bytes of the Output buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength) -{ - /* Check the parameters */ - assert_param((InDataLength >= 4)); - assert_param((OutDataLength >= 4)); - - /* Check In/out buffer allocation and size */ - if((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL) || \ - (InDataLength == 0) || (OutDataLength == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hjpeg); - - if(hjpeg->State != HAL_JPEG_STATE_READY) - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_BUSY; - } - else - { - if((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING ) - { - /*Change JPEG state*/ - hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING; - - /*Set the Context to Encode with DMA*/ - hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); - hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_DMA); - - /*Store In/out buffers pointers and size*/ - hjpeg->pJpegInBuffPtr = pDataInMCU; - hjpeg->pJpegOutBuffPtr = pDataOut; - hjpeg->InDataLength = InDataLength; - hjpeg->OutDataLength = OutDataLength; - - /*Reset In/out data counter */ - hjpeg->JpegInCount = 0; - hjpeg->JpegOutCount = 0; - - /*Init decoding process*/ - JPEG_Init_Process(hjpeg); - - /* JPEG encoding process using DMA */ - JPEG_DMA_StartProcess(hjpeg); - - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_ERROR; - } - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts JPEG decoding with DMA processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param pDataIn: Pointer to the input data buffer - * @param InDataLength: size in bytes Input buffer - * @param pDataOutMCU: Pointer to the Output data buffer - * @param OutDataLength: size in bytes of the Output buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength) -{ - /* Check the parameters */ - assert_param((InDataLength >= 4)); - assert_param((OutDataLength >= 4)); - - /* Check In/out buffer allocation and size */ - if((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL) || \ - (InDataLength == 0) || (OutDataLength == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hjpeg); - - if(hjpeg->State == HAL_JPEG_STATE_READY) - { - /*Change JPEG state*/ - hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING; - - /*Set the Context to Decode with DMA*/ - hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); - hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_DMA); - - /*Store In/out buffers pointers and size*/ - hjpeg->pJpegInBuffPtr = pDataIn; - hjpeg->pJpegOutBuffPtr = pDataOutMCU; - hjpeg->InDataLength = InDataLength; - hjpeg->OutDataLength = OutDataLength; - - /*Reset In/out data counter */ - hjpeg->JpegInCount = 0; - hjpeg->JpegOutCount = 0; - - /*Init decoding process*/ - JPEG_Init_Process(hjpeg); - - /* JPEG decoding process using DMA */ - JPEG_DMA_StartProcess(hjpeg); - - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_BUSY; - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Pause the JPEG Input/Output processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param XferSelection: This parameter can be one of the following values : - * JPEG_PAUSE_RESUME_INPUT : Pause Input processing - * JPEG_PAUSE_RESUME_OUTPUT: Pause Output processing - * JPEG_PAUSE_RESUME_INPUT_OUTPUT: Pause Input and Output processing - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection) -{ - uint32_t mask = 0; - - assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection)); - - if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) - { - if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT) - { - hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT; - mask |= JPEG_DMA_IDMA; - } - if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT) - { - hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT; - mask |= JPEG_DMA_ODMA; - } - JPEG_DISABLE_DMA(hjpeg,mask); - - } - else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) - { - - if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT) - { - hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT; - mask |= (JPEG_IT_IFT | JPEG_IT_IFNF); - } - if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT) - { - hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT; - mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC); - } - __HAL_JPEG_DISABLE_IT(hjpeg,mask); - - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Resume the JPEG Input/Output processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param XferSelection: This parameter can be one of the following values : - * JPEG_PAUSE_RESUME_INPUT : Resume Input processing - * JPEG_PAUSE_RESUME_OUTPUT: Resume Output processing - * JPEG_PAUSE_RESUME_INPUT_OUTPUT: Resume Input and Output processing - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection) -{ - uint32_t mask = 0; - - assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection)); - - if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) - { - - if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT) - { - hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT); - mask |= JPEG_DMA_IDMA; - - /*JPEG Input DMA transfer data number must be multiple of DMA buffer size - as the destination is a 32 bits register */ - hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4); - - if(hjpeg->InDataLength > 0) - { - /* Start DMA FIFO In transfer */ - HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, hjpeg->InDataLength >> 2); - } - - } - if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT) - { - hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT); - mask |= JPEG_DMA_ODMA; - - /* Start DMA FIFO Out transfer */ - HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength >> 2); - } - JPEG_ENABLE_DMA(hjpeg,mask); - - } - else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) - { - if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT) - { - hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT); - mask |= (JPEG_IT_IFT | JPEG_IT_IFNF); - } - if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT) - { - hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT); - mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC); - } - __HAL_JPEG_ENABLE_IT(hjpeg,mask); - - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Config Encoding/Decoding Input Buffer. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module. - * @param pNewInputBuffer: Pointer to the new input data buffer - * @param InDataLength: Size in bytes of the new Input data buffer - * @retval HAL status - */ -void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength) -{ - hjpeg->pJpegInBuffPtr = pNewInputBuffer; - hjpeg->InDataLength = InDataLength; -} - -/** - * @brief Config Encoding/Decoding Output Buffer. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module. - * @param pNewOutputBuffer: Pointer to the new output data buffer - * @param OutDataLength: Size in bytes of the new Output data buffer - * @retval HAL status - */ -void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength) -{ - hjpeg->pJpegOutBuffPtr = pNewOutputBuffer; - hjpeg->OutDataLength = OutDataLength; -} - -/** - * @brief Aborts the JPEG Encoding/Decoding. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg) -{ - uint32_t tickstart, tmpContext; - - tmpContext = hjpeg->Context; - - /*Reset the Context operation and method*/ - hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA); - - if((tmpContext & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) - { - /* Stop the DMA In/out Xfer*/ - HAL_DMA_Abort(hjpeg->hdmaout); - HAL_DMA_Abort(hjpeg->hdmain); - } - - /* Stop the JPEG encoding/decoding process*/ - hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check if the JPEG Codec is effectively disabled */ - while(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_COF) != RESET) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > JPEG_TIMEOUT_VALUE) - { - /* Update error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT; - - /* Change the DMA state */ - hjpeg->State = HAL_JPEG_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_TIMEOUT; - } - } - - /* Disable All Interrupts */ - __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK); - - /* Disable All DMA requests */ - JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_MASK); - - /* Flush input and output FIFOs*/ - hjpeg->Instance->CR |= JPEG_CR_IFF; - hjpeg->Instance->CR |= JPEG_CR_OFF; - - /* Clear all flags */ - __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL); - - /* Reset JpegInCount and JpegOutCount */ - hjpeg->JpegInCount = 0; - hjpeg->JpegOutCount = 0; - - /*Reset the Context Pause*/ - hjpeg->Context &= ~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT); - - /* Change the DMA state*/ - hjpeg->State = HAL_JPEG_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /* Return function status */ - return HAL_OK; -} - - -/** - * @} - */ - -/** @defgroup JPEG_Exported_Functions_Group4 JPEG Decode/Encode callback functions - * @brief JPEG process callback functions. - * -@verbatim - ============================================================================== - ##### JPEG Decode/Encode callback functions ##### - ============================================================================== - [..] This section provides callback functions: - (+) HAL_JPEG_InfoReadyCallback() : Decoding JPEG Info ready callback - (+) HAL_JPEG_EncodeCpltCallback() : Encoding complete callback. - (+) HAL_JPEG_DecodeCpltCallback() : Decoding complete callback. - (+) HAL_JPEG_ErrorCallback() : JPEG error callback. - (+) HAL_JPEG_GetDataCallback() : Get New Data chunk callback. - (+) HAL_JPEG_DataReadyCallback() : Decoded/Encoded Data ready callback. - -@endverbatim - * @{ - */ - -/** - * @brief Decoding JPEG Info ready callback. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param pInfo: pointer to a JPEG_ConfTypeDef structure that contains - * The JPEG decoded header informations - * @retval None - */ -__weak void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg,JPEG_ConfTypeDef *pInfo) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hjpeg); - UNUSED(pInfo); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_JPEG_HeaderParsingCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Encoding complete callback. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ -__weak void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hjpeg); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_JPEG_EncodeCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Decoding complete callback. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ -__weak void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hjpeg); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_JPEG_EncodeCpltCallback could be implemented in the user file - */ -} - -/** - * @brief JPEG error callback. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ - __weak void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hjpeg); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_JPEG_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief Get New Data chunk callback. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param NbDecodedData: Number of consummed data in the previous chunk in bytes - * @retval None - */ - __weak void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hjpeg); - UNUSED(NbDecodedData); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_JPEG_GetDataCallback could be implemented in the user file - */ -} - -/** - * @brief Decoded/Encoded Data ready callback. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param pDataOut: pointer to the output data buffer - * @param OutDataLength: number in bytes of data available in the specified output buffer - * @retval None - */ -__weak void HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hjpeg); - UNUSED(pDataOut); - UNUSED(OutDataLength); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_JPEG_DataReadyCallback could be implemented in the user file - */ -} - -/** - * @} - */ - - -/** @defgroup JPEG_Exported_Functions_Group5 JPEG IRQ handler management - * @brief JPEG IRQ handler. - * -@verbatim - ============================================================================== - ##### JPEG IRQ handler management ##### - ============================================================================== - [..] This section provides JPEG IRQ handler function. - (+) HAL_JPEG_IRQHandler() : handles JPEG interrupt request - -@endverbatim - * @{ - */ - -/** - * @brief This function handles JPEG interrupt request. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ -void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg) -{ - switch(hjpeg->State) - { - case HAL_JPEG_STATE_BUSY_ENCODING: - case HAL_JPEG_STATE_BUSY_DECODING: - /* continue JPEG data encoding/Decoding*/ - /* JPEG data processing : In/Out FIFO transfer*/ - if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) - { - JPEG_Process(hjpeg); - } - else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) - { - JPEG_DMA_ContinueProcess(hjpeg); - - } - - break; - - default: - break; - } -} - -/** - * @} - */ - -/** @defgroup JPEG_Exported_Functions_Group6 Peripheral State functions - * @brief Peripheral State functions. - * -@verbatim - ============================================================================== - ##### Peripheral State and Error functions ##### - ============================================================================== - [..] This section provides JPEG State and Errors function. - (+) HAL_JPEG_GetState() : permits to get in run-time the JPEG state. - (+) HAL_JPEG_GetError() : Returns the JPEG error code if any. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the JPEG state. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval JPEG state - */ -HAL_JPEG_STATETypeDef HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg) -{ - return hjpeg->State; -} - -/** -* @brief Return the JPEG error code -* @param hjpeg : pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for the specified JPEG. -* @retval JPEG Error Code -*/ -uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg) -{ - return hjpeg->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - - -/** @addtogroup JPEG_Private_Functions - * @{ - */ - -/** - * @brief Generates Huffman sizes/Codes Table from Bits/vals Table - * @param Bits: pointer to bits table - * @param Huffsize: pointer to sizes table - * @param Huffcode: pointer to codes table - * @param LastK: pointer to last Coeff (table dimmension) - * @retval HAL status - */ -static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK) -{ - uint32_t i, p, l, code, si; - - /* Figure C.1 – Generation of table of Huffman code sizes */ - p = 0; - for (l = 0; l < 16; l++) - { - i = (uint32_t)Bits[l]; - if ( (p + i) > 256) - { /* check for table overflow */ - return HAL_ERROR; - } - while (i != 0) - { - Huffsize[p++] = (uint8_t) l+1; - i--; - } - } - Huffsize[p] = 0; - *LastK = p; - - /* Figure C.2 – Generation of table of Huffman codes */ - code = 0; - si = Huffsize[0]; - p = 0; - while (Huffsize[p] != 0) - { - while (((uint32_t) Huffsize[p]) == si) - { - Huffcode[p++] = code; - code++; - } - /* code must fit in "size" bits (si), no code is allowed to be all ones*/ - if (((uint32_t) code) >= (((uint32_t) 1) << si)) - { - return HAL_ERROR; - } - code <<= 1; - si++; - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Transform a Bits/Vals AC Huffman table to sizes/Codes huffman Table - * that can programmed to the JPEG encoder registers - * @param AC_BitsValsTable: pointer to AC huffman bits/vals table - * @param AC_SizeCodesTable: pointer to AC huffman Sizes/Codes table - * @retval HAL status - */ -static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable) -{ - HAL_StatusTypeDef error; - uint8_t huffsize[257]; - uint32_t huffcode[257]; - uint32_t k; - uint32_t l,lsb, msb; - uint32_t lastK; - - error = JPEG_Bits_To_SizeCodes(AC_BitsValsTable->Bits, huffsize, huffcode, &lastK); - if(error != HAL_OK) - { - return error; - } - - /* Figure C.3 – Ordering procedure for encoding procedure code tables */ - k=0; - - while(k < lastK) - { - l = AC_BitsValsTable->HuffVal[k]; - if(l == 0) - { - l = 160; /*l = 0x00 EOB code*/ - } - else if(l == 0xF0)/* l = 0xF0 ZRL code*/ - { - l = 161; - } - else - { - msb = (l & 0xF0) >> 4; - lsb = (l & 0x0F); - l = (msb * 10) + lsb - 1; - } - if(l >= JPEG_AC_HUFF_TABLE_SIZE) - { - return HAL_ERROR; /* Huffman Table overflow error*/ - } - else - { - AC_SizeCodesTable->HuffmanCode[l] = huffcode[k]; - AC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1; - k++; - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Transform a Bits/Vals DC Huffman table to sizes/Codes huffman Table - * that can programmed to the JPEG encoder registers - * @param DC_BitsValsTable: pointer to DC huffman bits/vals table - * @param DC_SizeCodesTable: pointer to DC huffman Sizes/Codes table - * @retval HAL status - */ -static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable) -{ - HAL_StatusTypeDef error; - - uint32_t k; - uint32_t l; - uint32_t lastK; - uint8_t huffsize[257]; - uint32_t huffcode[257]; - error = JPEG_Bits_To_SizeCodes(DC_BitsValsTable->Bits, huffsize, huffcode, &lastK); - if(error != HAL_OK) - { - return error; - } - /* Figure C.3: ordering procedure for encoding procedure code tables */ - k=0; - - while(k < lastK) - { - l = DC_BitsValsTable->HuffVal[k]; - if(l >= JPEG_DC_HUFF_TABLE_SIZE) - { - return HAL_ERROR; /* Huffman Table overflow error*/ - } - else - { - DC_SizeCodesTable->HuffmanCode[l] = huffcode[k]; - DC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1; - k++; - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Set the JPEG register with an DC huffman table at the given DC table address - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param HuffTableDC: pointer to DC huffman table - * @param DCTableAddress: Encoder DC huffman table address it could be HUFFENC_DC0 or HUFFENC_DC1. - * @retval HAL status - */ -static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, uint32_t *DCTableAddress) -{ - HAL_StatusTypeDef error = HAL_OK; - JPEG_DC_HuffCodeTableTypeDef dcSizeCodesTable; - uint32_t i, lsb, msb; - __IO uint32_t *address, *addressDef; - - if(DCTableAddress == (uint32_t *)(hjpeg->Instance->HUFFENC_DC0)) - { - address = (hjpeg->Instance->HUFFENC_DC0 + (JPEG_DC_HUFF_TABLE_SIZE/2)); - } - else if (DCTableAddress == (uint32_t *)(hjpeg->Instance->HUFFENC_DC1)) - { - address = (hjpeg->Instance->HUFFENC_DC1 + (JPEG_DC_HUFF_TABLE_SIZE/2)); - } - else - { - return HAL_ERROR; - } - - if(HuffTableDC != NULL) - { - error = JPEG_DCHuff_BitsVals_To_SizeCodes(HuffTableDC, &dcSizeCodesTable); - if(error != HAL_OK) - { - return error; - } - addressDef = address; - *addressDef = 0x0FFF0FFF; - addressDef++; - *addressDef = 0x0FFF0FFF; - - i = JPEG_DC_HUFF_TABLE_SIZE; - while(i>0) - { - i--; - address --; - msb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & 0xFF); - i--; - lsb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & 0xFF); - - *address = lsb | (msb << 16); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Set the JPEG register with an AC huffman table at the given AC table address - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param HuffTableAC: pointer to AC huffman table - * @param ACTableAddress: Encoder AC huffman table address it could be HUFFENC_AC0 or HUFFENC_AC1. - * @retval HAL status - */ -static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, uint32_t *ACTableAddress) -{ - HAL_StatusTypeDef error = HAL_OK; - JPEG_AC_HuffCodeTableTypeDef acSizeCodesTable; - uint32_t i, lsb, msb; - __IO uint32_t *address, *addressDef; - - if(ACTableAddress == (uint32_t *)(hjpeg->Instance->HUFFENC_AC0)) - { - address = (hjpeg->Instance->HUFFENC_AC0 + (JPEG_AC_HUFF_TABLE_SIZE/2)); - } - else if (ACTableAddress == (uint32_t *)(hjpeg->Instance->HUFFENC_AC1)) - { - address = (hjpeg->Instance->HUFFENC_AC1 + (JPEG_AC_HUFF_TABLE_SIZE/2)); - } - else - { - return HAL_ERROR; - } - - if(HuffTableAC != NULL) - { - error = JPEG_ACHuff_BitsVals_To_SizeCodes(HuffTableAC, &acSizeCodesTable); - if(error != HAL_OK) - { - return error; - } - /* Default values settings : 162–167 FFFh , 168–175 FD0h–FD7h */ - /* Locations 162:175 of each AC table contain information used internally by the core */ - - addressDef = address; - for(i=0; i<3; i++) - { - *addressDef = 0x0FFF0FFF; - addressDef++; - } - *addressDef = 0x0FD10FD0; - addressDef++; - *addressDef = 0x0FD30FD2; - addressDef++; - *addressDef = 0x0FD50FD4; - addressDef++; - *addressDef = 0x0FD70FD6; - /* end of Locations 162:175 */ - - - i = JPEG_AC_HUFF_TABLE_SIZE; - while (i > 0) - { - i--; - address--; - msb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] & 0xFF); - i--; - lsb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] & 0xFF); - - *address = lsb | (msb << 16); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configure the JPEG encoder register huffman tables to used during - * the encdoing operation - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param HuffTableAC0: AC0 huffman table - * @param HuffTableDC0: DC0 huffman table - * @param HuffTableAC1: AC1 huffman table - * @param HuffTableDC1: DC1 huffman table - * @retval None - */ -static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1) -{ - HAL_StatusTypeDef error = HAL_OK; - - JPEG_Set_Huff_DHTMem(hjpeg, HuffTableAC0, HuffTableDC0, HuffTableAC1, HuffTableDC1); - - if(HuffTableAC0 != NULL) - { - error = JPEG_Set_HuffAC_Mem(hjpeg, HuffTableAC0, (uint32_t *)(hjpeg->Instance->HUFFENC_AC0)); - if(error != HAL_OK) - { - return error; - } - } - - if(HuffTableAC1 != NULL) - { - error = JPEG_Set_HuffAC_Mem(hjpeg, HuffTableAC1, (uint32_t *)(hjpeg->Instance->HUFFENC_AC1)); - if(error != HAL_OK) - { - return error; - } - } - - if(HuffTableDC0 != NULL) - { - error = JPEG_Set_HuffDC_Mem(hjpeg, HuffTableDC0, (uint32_t *)hjpeg->Instance->HUFFENC_DC0); - if(error != HAL_OK) - { - return error; - } - } - - if(HuffTableDC1 != NULL) - { - error = JPEG_Set_HuffDC_Mem(hjpeg, HuffTableDC1, (uint32_t *)hjpeg->Instance->HUFFENC_DC1); - if(error != HAL_OK) - { - return error; - } - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configure the JPEG register huffman tables to be included in the JPEG - * file header (used for encoding only) - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param HuffTableAC0: AC0 huffman table - * @param HuffTableDC0: DC0 huffman table - * @param HuffTableAC1: AC1 huffman table - * @param HuffTableDC1: DC1 huffman table - * @retval None - */ -static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1) -{ - uint32_t value, index; - __IO uint32_t *address; - if(HuffTableDC0 != NULL) - { - /* DC0 Huffman Table : BITS*/ - /* DC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address to DHTMEM + 3*/ - address = (hjpeg->Instance->DHTMEM + 3); - index = 16; - while(index > 0) - { - - *address = (((uint32_t)HuffTableDC0->Bits[index-1] & 0xFF) << 24)| - (((uint32_t)HuffTableDC0->Bits[index-2] & 0xFF) << 16)| - (((uint32_t)HuffTableDC0->Bits[index-3] & 0xFF) << 8) | - ((uint32_t)HuffTableDC0->Bits[index-4] & 0xFF); - address--; - index -=4; - - } - /* DC0 Huffman Table : Val*/ - /* DC0 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +4 to DHTMEM + 6 */ - address = (hjpeg->Instance->DHTMEM + 6); - index = 12; - while(index > 0) - { - *address = (((uint32_t)HuffTableDC0->HuffVal[index-1] & 0xFF) << 24)| - (((uint32_t)HuffTableDC0->HuffVal[index-2] & 0xFF) << 16)| - (((uint32_t)HuffTableDC0->HuffVal[index-3] & 0xFF) << 8) | - ((uint32_t)HuffTableDC0->HuffVal[index-4] & 0xFF); - address--; - index -=4; - } - } - - if(HuffTableAC0 != NULL) - { - /* AC0 Huffman Table : BITS*/ - /* AC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 7 to DHTMEM + 10*/ - address = (hjpeg->Instance->DHTMEM + 10); - index = 16; - while(index > 0) - { - - *address = (((uint32_t)HuffTableAC0->Bits[index-1] & 0xFF) << 24)| - (((uint32_t)HuffTableAC0->Bits[index-2] & 0xFF) << 16)| - (((uint32_t)HuffTableAC0->Bits[index-3] & 0xFF) << 8) | - ((uint32_t)HuffTableAC0->Bits[index-4] & 0xFF); - address--; - index -=4; - - } - /* AC0 Huffman Table : Val*/ - /* AC0 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 11 to DHTMEM + 51 */ - /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 51) belong to AC0 VALS table */ - address = (hjpeg->Instance->DHTMEM + 51); - value = *address & 0xFFFF0000U; - value = value | (((uint32_t)HuffTableAC0->HuffVal[161] & 0xFF) << 8) | ((uint32_t)HuffTableAC0->HuffVal[160] & 0xFF); - *address = value; - - /*continue setting 160 AC0 huffman values */ - address--; /* address = hjpeg->Instance->DHTMEM + 50*/ - index = 160; - while(index > 0) - { - *address = (((uint32_t)HuffTableAC0->HuffVal[index-1] & 0xFF) << 24)| - (((uint32_t)HuffTableAC0->HuffVal[index-2] & 0xFF) << 16)| - (((uint32_t)HuffTableAC0->HuffVal[index-3] & 0xFF) << 8) | - ((uint32_t)HuffTableAC0->HuffVal[index-4] & 0xFF); - address--; - index -=4; - } - } - - if(HuffTableDC1 != NULL) - { - /* DC1 Huffman Table : BITS*/ - /* DC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM + 51 base address to DHTMEM + 55*/ - /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 51) belong to DC1 Bits table */ - address = (hjpeg->Instance->DHTMEM + 51); - value = *address & 0x0000FFFFU; - value = value | (((uint32_t)HuffTableDC1->Bits[1] & 0xFF) << 24) | (((uint32_t)HuffTableDC1->Bits[0] & 0xFF) << 16); - *address = value; - - /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 55) belong to DC1 Bits table */ - address = (hjpeg->Instance->DHTMEM + 55); - value = *address & 0xFFFF0000U; - value = value | (((uint32_t)HuffTableDC1->Bits[15] & 0xFF) << 8) | ((uint32_t)HuffTableDC1->Bits[14] & 0xFF); - *address = value; - - /*continue setting 12 DC1 huffman Bits from DHTMEM + 54 down to DHTMEM + 52*/ - address--; - index = 12; - while(index > 0) - { - - *address = (((uint32_t)HuffTableDC1->Bits[index+1] & 0xFF) << 24)| - (((uint32_t)HuffTableDC1->Bits[index] & 0xFF) << 16)| - (((uint32_t)HuffTableDC1->Bits[index-1] & 0xFF) << 8) | - ((uint32_t)HuffTableDC1->Bits[index-2] & 0xFF); - address--; - index -=4; - - } - /* DC1 Huffman Table : Val*/ - /* DC1 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +55 to DHTMEM + 58 */ - /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 55) belong to DC1 Val table */ - address = (hjpeg->Instance->DHTMEM + 55); - value = *address & 0x0000FFFF; - value = value | (((uint32_t)HuffTableDC1->HuffVal[1] & 0xFF) << 24) | (((uint32_t)HuffTableDC1->HuffVal[0] & 0xFF) << 16); - *address = value; - - /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 58) belong to DC1 Val table */ - address = (hjpeg->Instance->DHTMEM + 58); - value = *address & 0xFFFF0000U; - value = value | (((uint32_t)HuffTableDC1->HuffVal[11] & 0xFF) << 8) | ((uint32_t)HuffTableDC1->HuffVal[10] & 0xFF); - *address = value; - - /*continue setting 8 DC1 huffman val from DHTMEM + 57 down to DHTMEM + 56*/ - address--; - index = 8; - while(index > 0) - { - *address = (((uint32_t)HuffTableDC1->HuffVal[index+1] & 0xFF) << 24)| - (((uint32_t)HuffTableDC1->HuffVal[index] & 0xFF) << 16)| - (((uint32_t)HuffTableDC1->HuffVal[index-1] & 0xFF) << 8) | - ((uint32_t)HuffTableDC1->HuffVal[index-2] & 0xFF); - address--; - index -=4; - } - } - - if(HuffTableAC1 != NULL) - { - /* AC1 Huffman Table : BITS*/ - /* AC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 58 to DHTMEM + 62*/ - /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 58) belong to AC1 Bits table */ - address = (hjpeg->Instance->DHTMEM + 58); - value = *address & 0x0000FFFFU; - value = value | (((uint32_t)HuffTableAC1->Bits[1] & 0xFF) << 24) | (((uint32_t)HuffTableAC1->Bits[0] & 0xFF) << 16); - *address = value; - - /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 62) belong to Bits Val table */ - address = (hjpeg->Instance->DHTMEM + 62); - value = *address & 0xFFFF0000U; - value = value | (((uint32_t)HuffTableAC1->Bits[15] & 0xFF) << 8) | ((uint32_t)HuffTableAC1->Bits[14] & 0xFF); - *address = value; - - /*continue setting 12 AC1 huffman Bits from DHTMEM + 61 down to DHTMEM + 59*/ - address--; - index = 12; - while(index > 0) - { - - *address = (((uint32_t)HuffTableAC1->Bits[index+1] & 0xFF) << 24)| - (((uint32_t)HuffTableAC1->Bits[index] & 0xFF) << 16)| - (((uint32_t)HuffTableAC1->Bits[index-1] & 0xFF) << 8) | - ((uint32_t)HuffTableAC1->Bits[index-2] & 0xFF); - address--; - index -=4; - - } - /* AC1 Huffman Table : Val*/ - /* AC1 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 62 to DHTMEM + 102 */ - /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 62) belong to AC1 VALS table */ - address = (hjpeg->Instance->DHTMEM + 62); - value = *address & 0x0000FFFF; - value = value | (((uint32_t)HuffTableAC1->HuffVal[1] & 0xFF) << 24) | (((uint32_t)HuffTableAC1->HuffVal[0] & 0xFF) << 16); - *address = value; - - /*continue setting 160 AC1 huffman values from DHTMEM + 63 to DHTMEM+102 */ - address = (hjpeg->Instance->DHTMEM + 102); - index = 160; - while(index > 0) - { - *address = (((uint32_t)HuffTableAC1->HuffVal[index+1] & 0xFF) << 24)| - (((uint32_t)HuffTableAC1->HuffVal[index] & 0xFF) << 16)| - (((uint32_t)HuffTableAC1->HuffVal[index-1] & 0xFF) << 8) | - ((uint32_t)HuffTableAC1->HuffVal[index-2] & 0xFF); - address--; - index -=4; - } - } -} - -/** - * @brief Configure the JPEG registers with a given quantization table - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param QTable: pointer to an array of 64 bytes giving the quantization table - * @param QTableAddress: destination quantization address in the JPEG peripheral - * it could be QMEM0, QMEM1, QMEM2 or QMEM3 - * @retval None - */ -static HAL_StatusTypeDef JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, uint32_t *QTableAddress) -{ - uint32_t i, j, *tableAddress, quantRow, quantVal, ScaleFactor; - - if((QTableAddress == ((uint32_t *)(hjpeg->Instance->QMEM0))) || - (QTableAddress == ((uint32_t *)(hjpeg->Instance->QMEM1))) || - (QTableAddress == ((uint32_t *)(hjpeg->Instance->QMEM2))) || - (QTableAddress == ((uint32_t *)(hjpeg->Instance->QMEM3)))) - { - tableAddress = QTableAddress; - } - else - { - return HAL_ERROR; - } - - if ((hjpeg->Conf.ImageQuality >= 50) && (hjpeg->Conf.ImageQuality <= 100)) - { - ScaleFactor = 200 - (hjpeg->Conf.ImageQuality * 2); - } - else if (hjpeg->Conf.ImageQuality > 0) - { - ScaleFactor = ((uint32_t) 5000) / ((uint32_t) hjpeg->Conf.ImageQuality); - } - else - { - return HAL_ERROR; - } - - /*Quantization_table = (Standard_quanization_table * ScaleFactor + 50) / 100*/ - i = 0; - while( i < JPEG_QUANT_TABLE_SIZE) - { - quantRow = 0; - for(j=0; j<4; j++) - { - /* Note that the quantization coefficients must be specified in the table in zigzag order */ - quantVal = ((((uint32_t) QTable[JPEG_ZIGZAG_ORDER[i+j]]) * ScaleFactor) + 50) / 100; - - if(quantVal == 0) - { - quantVal = 1; - } - else if (quantVal > 255) - { - quantVal = 255; - } - - quantRow |= ((quantVal & 0xFF) << (8 * j)); - } - - i += 4; - *tableAddress = quantRow; - tableAddress ++; - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configure the JPEG registers for YCbCr color space - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ -static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg) -{ - uint32_t ySamplingH; - uint32_t ySamplingV; - uint32_t yblockNb; - - /*Set Number of color components to 3*/ - hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_NF; - hjpeg->Instance->CONFR1 |= JPEG_CONFR1_NF_1; - - /* compute MCU block size and Y, Cb ,Cr sampling factors*/ - if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) - { - ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ - ySamplingV = JPEG_CONFR4_VSF_1; /* Vs = 2*/ - - yblockNb = 0x30; /* 4 blocks of 8x8*/ - } - else if(hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) - { - ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ - ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/ - - yblockNb = 0x10; /* 2 blocks of 8x8*/ - } - else /*JPEG_444_SUBSAMPLING and default*/ - { - ySamplingH = JPEG_CONFR4_HSF_0; /* Hs = 1*/ - ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/ - - yblockNb = 0; /* 1 block of 8x8*/ - } - - hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS); - hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF_1 | JPEG_CONFR1_NS_1); - - /*Reset CONFR4 register*/ - hjpeg->Instance->CONFR4 = 0; - /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/ - hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB) ); - - /*Reset CONFR5 register*/ - hjpeg->Instance->CONFR5 = 0; - /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 1*/ - hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0 | JPEG_CONFR5_QT_0 | JPEG_CONFR5_HA | JPEG_CONFR5_HD); - - /*Reset CONFR6 register*/ - hjpeg->Instance->CONFR6 = 0; - /*Set Horizental and Vertical sampling factor and number of blocks for component 2*/ - /* In YCBCR , by default, both chrominance components (component 1 and component 2) use the same Quantization table (table 1) */ - /* In YCBCR , both chrominance components (component 1 and component 2) use the same Huffman tables (table 1) */ - hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0 | JPEG_CONFR6_QT_0 | JPEG_CONFR6_HA | JPEG_CONFR6_HD); - -} - -/** - * @brief Configure the JPEG registers for GrayScale color space - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ -static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg) -{ - /*Set Number of color components to 1*/ - hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS); - - /*in GrayScale use 1 single Quantization table (Table 0)*/ - /*in GrayScale use only one couple of AC/DC huffman table (table 0)*/ - - /*Reset CONFR4 register*/ - hjpeg->Instance->CONFR4 = 0; - /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/ - hjpeg->Instance->CONFR4 |= JPEG_CONFR4_HSF_0 | JPEG_CONFR4_VSF_0 ; -} - -/** - * @brief Configure the JPEG registers for CMYK color space - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ -static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg) -{ - uint32_t ySamplingH; - uint32_t ySamplingV; - uint32_t yblockNb; - - /*Set Number of color components to 4*/ - hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF | JPEG_CONFR1_NS); - - /* compute MCU block size and Y, Cb ,Cr sampling factors*/ - if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) - { - ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ - ySamplingV = JPEG_CONFR4_VSF_1; /* Vs = 2*/ - - yblockNb = 0x30; /* 4 blocks of 8x8*/ - } - else if(hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) - { - ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ - ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/ - - yblockNb = 0x10; /* 2 blocks of 8x8*/ - } - else /*JPEG_444_SUBSAMPLING and default*/ - { - ySamplingH = JPEG_CONFR4_HSF_0; /* Hs = 1*/ - ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/ - - yblockNb = 0; /* 1 block of 8x8*/ - } - - /*Reset CONFR4 register*/ - hjpeg->Instance->CONFR4 = 0; - /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/ - hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB) ); - - /*Reset CONFR5 register*/ - hjpeg->Instance->CONFR5 = 0; - /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 1*/ - hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0); - - /*Reset CONFR6 register*/ - hjpeg->Instance->CONFR6 = 0; - /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 2*/ - hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0); - - /*Reset CONFR7 register*/ - hjpeg->Instance->CONFR7 = 0; - /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 3*/ - hjpeg->Instance->CONFR7 |= (JPEG_CONFR7_HSF_0 | JPEG_CONFR7_VSF_0); -} - -/** - * @brief Init the JPEG encoding/decoding process in case of Polling or Interrupt and DMA - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ -static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg) -{ - /*Reset pause*/ - hjpeg->Context &= (~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT)); - - if((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) - { - /*Set JPEG Codec to Decoding mode */ - hjpeg->Instance->CONFR1 |= JPEG_CONFR1_DE; - } - else if((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE) - { - /*Set JPEG Codec to Encoding mode */ - hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_DE; - } - - /*Stop JPEG processing */ - hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; - - /* Disable All Interrupts */ - __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK); - - /* Disable All DMA requests */ - JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_MASK); - - /* Flush input and output FIFOs*/ - hjpeg->Instance->CR |= JPEG_CR_IFF; - hjpeg->Instance->CR |= JPEG_CR_OFF; - - /* Clear all flags */ - __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL); - - /*Start Encoding/Decoding*/ - hjpeg->Instance->CONFR0 |= JPEG_CONFR0_START; - - if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) - { - /*Enable IN/OUT, end of Conversation, and end of header parsing interruptions*/ - __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_IFT | JPEG_IT_IFNF | JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC |JPEG_IT_HPD); - } - else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) - { - /*Enable End Of Conversation, and End Of Header parsing interruptions*/ - __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC |JPEG_IT_HPD); - - } -} - -/** - * @brief JPEG encoding/decoding process in case of Polling or Interrupt - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval JPEG_PROCESS_DONE if the process has ends else JPEG_PROCESS_ONGOING - */ -static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg) -{ - uint32_t tmpContext; - - /*End of header processing flag rised*/ - if(((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) && (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != RESET)) - { - /*Call Header parsing complet callback */ - HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf); - /* Reset the ImageQuality */ - hjpeg->Conf.ImageQuality = 0; - /* Note : the image quality is only available at the end of the decoding operation */ - /* at the current stage the calculated image quality is not correct so reset it */ - - /*Call Info Ready callback */ - HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf); - - __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_IT_HPD); - - /* Clear header processing done flag */ - __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_HPDF); - } - - /*Input FIFO status handling*/ - if((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0) - { - if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFTF) != RESET) - { - /*Input FIFO threshold flag rised*/ - /*4 words (16 bytes) can be written in */ - JPEG_ReadInputData(hjpeg,4); - } - else if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFNFF) != RESET) - { - /*Input FIFO Not Full flag rised*/ - /*32-bit value can be written in */ - JPEG_ReadInputData(hjpeg,1); - } - } - - - /*Output FIFO flag handling*/ - if((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0) - { - if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFTF) != RESET) - { - /*Output FIFO threshold flag rised*/ - /*4 words (16 bytes) can be read out */ - JPEG_StoreOutputData(hjpeg, 4); - } - else if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != RESET) - { - /*Output FIFO Not Empty flag rised*/ - /*32-bit value can be read out */ - JPEG_StoreOutputData(hjpeg, 1); - } - } - - /*End of Conversion handling :i.e EOC flag is high and OFTF low and OFNEF low*/ - if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF | JPEG_FLAG_OFTF | JPEG_FLAG_OFNEF) == JPEG_FLAG_EOCF) - { - /*Stop Encoding/Decoding*/ - hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; - - if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) - { - /* Disable All Interrupts */ - __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK); - } - - /* Clear all flags */ - __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL); - - /*Call End of conversion callback */ - if(hjpeg->JpegOutCount > 0) - { - /*Output Buffer is not empty, call DecodedDataReadyCallback*/ - HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); - hjpeg->JpegOutCount = 0; - } - - /*Reset Context Operation*/ - tmpContext = hjpeg->Context; - /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/ - hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES); - - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /* Change the JPEG state */ - hjpeg->State = HAL_JPEG_STATE_READY; - - /*Call End of Encoding/Decoding callback */ - if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) - { - HAL_JPEG_DecodeCpltCallback(hjpeg); - } - else if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE) - { - HAL_JPEG_EncodeCpltCallback(hjpeg); - } - - return JPEG_PROCESS_DONE; - } - - - return JPEG_PROCESS_ONGOING; -} - -/** - * @brief Store some output data from the JPEG peripheral to the output buffer. - * This function is used when the JPEG peripheral has new data to output - * in case of Polling or Interrupt process - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param nbOutputWords: Number of output words (of 32 bits) ready from the JPEG peripheral - * @retval None - */ -static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords) -{ - uint32_t index, nBwords, nbBytes , dataword, *pOutData; - - pOutData = (uint32_t *)(((uint32_t *)hjpeg->pJpegOutBuffPtr) + (hjpeg->JpegOutCount/4)); - - if(hjpeg->OutDataLength >= (hjpeg->JpegOutCount + (nbOutputWords*4))) - { - for(index = 0; index < nbOutputWords; index++) - { - /*Transfer 32 bits from the JPEG output FIFO*/ - *pOutData = hjpeg->Instance->DOR; - pOutData++; - hjpeg->JpegOutCount += 4; - } - if(hjpeg->OutDataLength == hjpeg->JpegOutCount) - { - /*Output Buffer is full, call DecodedDataReadyCallback*/ - HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); - hjpeg->JpegOutCount = 0; - } - } - else if(hjpeg->OutDataLength > hjpeg->JpegOutCount) - { - nBwords = (hjpeg->OutDataLength - hjpeg->JpegOutCount)/4; - for(index = 0; index < nBwords; index++) - { - /*Transfer 32 bits from the JPEG output FIFO*/ - *pOutData = hjpeg->Instance->DOR; - pOutData++; - hjpeg->JpegOutCount += 4; - } - if(hjpeg->OutDataLength == hjpeg->JpegOutCount) - { - /*Output Buffer is full, call DecodedDataReadyCallback*/ - HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); - hjpeg->JpegOutCount = 0; - } - else - { - nbBytes = hjpeg->OutDataLength - hjpeg->JpegOutCount; - dataword = hjpeg->Instance->DOR; - for(index = 0; index < nbBytes; index++) - { - hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (dataword >> (8*index)) & 0xFF; - hjpeg->JpegOutCount++; - } - /*Output Buffer is full, call DecodedDataReadyCallback*/ - HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); - hjpeg->JpegOutCount = 0; - - nbBytes = 4 - nbBytes; - for(index = nbBytes; index < 4; index++) - { - hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (dataword >> (8*index)) & 0xFF; - hjpeg->JpegOutCount++; - } - } - } -} - -/** - * @brief Read some input Data from the input buffer. - * This function is used when the JPEG peripheral needs new data - * in case of Polling or Interrupt process - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param nbRequestWords: Number of input words (of 32 bits) that the JPE peripheral request - * @retval None - */ -static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords) -{ - uint32_t nbBytes = 0, nBwords, index, Dataword; - - if((hjpeg->InDataLength == 0) || (nbRequestWords == 0)) - { - /* No more Input data : nothing to do*/ - HAL_JPEG_Pause(hjpeg, JPEG_PAUSE_RESUME_INPUT); - } - else if(hjpeg->InDataLength > hjpeg->JpegInCount) - { - nbBytes = hjpeg->InDataLength - hjpeg->JpegInCount; - } - else if(hjpeg->InDataLength == hjpeg->JpegInCount) - { - /*Call HAL_JPEG_GetDataCallback to get new data */ - HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount); - if(hjpeg->InDataLength > 4) - { - hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4); - } - hjpeg->JpegInCount = 0; - nbBytes = hjpeg->InDataLength; - } - if((nbBytes > 0) && ((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0)) - { - nBwords = nbBytes / 4; - if(nBwords >= nbRequestWords) - { - for(index = 0; index < nbRequestWords; index++) - { - hjpeg->Instance->DIR = *((uint32_t *)(((uint32_t *)hjpeg->pJpegInBuffPtr) + (hjpeg->JpegInCount/4))); - - hjpeg->JpegInCount += 4; - } - } - else /*nBwords < nbRequestWords*/ - { - if(nBwords > 0) - { - for(index = 0; index < nBwords; index++) - { - hjpeg->Instance->DIR = *((uint32_t *)(((uint32_t *)hjpeg->pJpegInBuffPtr) + (hjpeg->JpegInCount/4))); - - hjpeg->JpegInCount += 4; - } - } - else - { - /* end of file*/ - Dataword = 0; - for(index=0; index< nbBytes; index++) - { - Dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8 * index); - hjpeg->JpegInCount++; - } - hjpeg->Instance->DIR = Dataword; - } - } - } -} - -/** - * @brief Start the JPEG DMA process (encoding/decoding) - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING - */ -static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg) -{ - if((hjpeg->InDataLength < 4) || (hjpeg->OutDataLength < 4)) - { - return HAL_ERROR; - } - /* Reset Ending DMA internal context flag*/ - hjpeg->Context &= ~JPEG_CONTEXT_ENDING_DMA; - - /* Disable DMA In/Out Request*/ - JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_ODMA | JPEG_DMA_IDMA); - - /* Set the JPEG DMA In transfer complete callback */ - hjpeg->hdmain->XferCpltCallback = JPEG_DMAInCpltCallback; - /* Set the DMA In error callback */ - hjpeg->hdmain->XferErrorCallback = JPEG_DMAErrorCallback; - - /* Set the JPEG DMA Out transfer complete callback */ - hjpeg->hdmaout->XferCpltCallback = JPEG_DMAOutCpltCallback; - /* Set the DMA Out error callback */ - hjpeg->hdmaout->XferErrorCallback = JPEG_DMAErrorCallback; - /* Set the DMA Out Abort callback */ - hjpeg->hdmaout->XferAbortCallback = JPEG_DMAOutAbortCallback; - - /*DMA transfer size must be a multiple of 4 bytes i.e mutliple of 32bits words*/ - hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4); - - /*DMA transfer size must be a multiple of 4 bytes i.e mutliple of 32bits words*/ - hjpeg->OutDataLength = hjpeg->OutDataLength - (hjpeg->OutDataLength % 4); - - /* Start DMA FIFO In transfer */ - HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, hjpeg->InDataLength >> 2); - - /* Start DMA FIFO Out transfer */ - HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength >> 2); - - /* Enable JPEG In/Out DMA requests*/ - JPEG_ENABLE_DMA(hjpeg,JPEG_DMA_IDMA | JPEG_DMA_ODMA); - - return HAL_OK; -} - -/** - * @brief Continue the current JPEG DMA process (encoding/decoding) - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING - */ -static uint32_t JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg) -{ - /*End of header processing flag rises*/ - if(((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) && (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != RESET)) - { - /*Call Header parsing complete callback */ - HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf); - - /* Reset the ImageQuality */ - hjpeg->Conf.ImageQuality = 0; - /* Note : the image quality is only available at the end of the decoding operation */ - /* at the current stage the calculated image quality is not correct so reset it */ - - /*Call Info Ready callback */ - HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf); - - __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_IT_HPD); - - /* Clear header processing done flag */ - __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_HPDF); - } - - /*End of Conversion handling*/ - if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) != RESET) - { - /*Disabkle JPEG In/Out DMA Requests*/ - JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_ODMA | JPEG_DMA_IDMA); - - hjpeg->Context |= JPEG_CONTEXT_ENDING_DMA; - - /*Stop Encoding/Decoding*/ - hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; - - __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK); - - /* Clear all flags */ - __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL); - - if(hjpeg->hdmain->State == HAL_DMA_STATE_BUSY) - { - /* Stop the DMA In Xfer*/ - HAL_DMA_Abort_IT(hjpeg->hdmain); - } - - if(hjpeg->hdmaout->State == HAL_DMA_STATE_BUSY) - { - /* Stop the DMA out Xfer*/ - HAL_DMA_Abort_IT(hjpeg->hdmaout); - } - else - { - return JPEG_DMA_EndProcess(hjpeg); - } - } - - return JPEG_PROCESS_ONGOING; -} - -/** - * @brief Finalize the current JPEG DMA process (encoding/decoding) - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval JPEG_PROCESS_DONE - */ -static uint32_t JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg) -{ - uint32_t tmpContext, count = JPEG_FIFO_SIZE, *pDataOut; - - hjpeg->JpegOutCount = hjpeg->OutDataLength - ((hjpeg->hdmaout->Instance->NDTR & DMA_SxNDT) << 2); - - /*if Output Buffer is full, call HAL_JPEG_DataReadyCallback*/ - if(hjpeg->JpegOutCount == hjpeg->OutDataLength) - { - HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); - hjpeg->JpegOutCount = 0; - } - - pDataOut = (uint32_t *)(hjpeg->pJpegOutBuffPtr + hjpeg->JpegOutCount); - - while((__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0) && (count > 0)) - { - count--; - - *pDataOut = hjpeg->Instance->DOR; - pDataOut++; - hjpeg->JpegOutCount += 4; - - if(hjpeg->JpegOutCount == hjpeg->OutDataLength) - { - /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/ - HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); - hjpeg->JpegOutCount = 0; - } - } - - /*Stop Encoding/Decoding*/ - hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; - - if(hjpeg->JpegOutCount > 0) - { - /*Output Buffer is not empty, call DecodedDataReadyCallback*/ - HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); - hjpeg->JpegOutCount = 0; - } - - tmpContext = hjpeg->Context; - /*Clear all context fileds execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/ - hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES); - - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /* Change the JPEG state */ - hjpeg->State = HAL_JPEG_STATE_READY; - - /*Call End of Encoding/Decoding callback */ - if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) - { - HAL_JPEG_DecodeCpltCallback(hjpeg); - } - else if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE) - { - HAL_JPEG_EncodeCpltCallback(hjpeg); - } - - - return JPEG_PROCESS_DONE; -} - -/** - * @brief DMA input transfer complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure. - * @retval None - */ -static void JPEG_DMAInCpltCallback(DMA_HandleTypeDef *hdma) -{ - JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Disable The JPEG IT so the DMA Input Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */ - __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK); - - if(((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) && ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) == 0)) - { - JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_IDMA); - - hjpeg->JpegInCount = hjpeg->InDataLength - ((hdma->Instance->NDTR & DMA_SxNDT) << 2); - - /*Call HAL_JPEG_GetDataCallback to get new data */ - HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount); - - if(hjpeg->InDataLength >= 4) - { - /*JPEG Input DMA transfer data number must be multiple of 32 bits word - as the destination is a 32 bits (4 bytes) register */ - hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4); - } - else if(hjpeg->InDataLength > 0) - { - /*Transfer last data word (i.e last 4 bytes)*/ - hjpeg->InDataLength = 4; - } - - if(((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0) && (hjpeg->InDataLength > 0)) - { - /* Start DMA FIFO In transfer */ - HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, hjpeg->InDataLength >> 2); - JPEG_ENABLE_DMA(hjpeg,JPEG_DMA_IDMA); - } - - /* JPEG Conversion still on going : Enable the JPEG IT */ - __HAL_JPEG_ENABLE_IT(hjpeg,JPEG_IT_EOC |JPEG_IT_HPD); - } -} - -/** - * @brief DMA output transfer complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure. - * @retval None - */ -static void JPEG_DMAOutCpltCallback(DMA_HandleTypeDef *hdma) -{ - JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Disable The JPEG IT so the DMA Output Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */ - __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK); - - if(((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) && ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) == 0)) - { - if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) == 0) - { - JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_ODMA); - hjpeg->JpegOutCount = hjpeg->OutDataLength - ((hdma->Instance->NDTR & DMA_SxNDT) << 2); - - /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/ - HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); - - if((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0) - { - /* Start DMA FIFO Out transfer */ - HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength >> 2); - JPEG_ENABLE_DMA(hjpeg,JPEG_DMA_ODMA); - } - } - - /* JPEG Conversion still on going : Enable the JPEG IT */ - __HAL_JPEG_ENABLE_IT(hjpeg,JPEG_IT_EOC |JPEG_IT_HPD); - } -} - -/** - * @brief DMA Transfer error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure. - * @retval None - */ -static void JPEG_DMAErrorCallback(DMA_HandleTypeDef *hdma) -{ - JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* if DMA error is FIFO error ignore it */ - if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) - { - /*Stop Encoding/Decoding*/ - hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; - - /* Disable All Interrupts */ - __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK); - - /* Disable All DMA requests */ - JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_MASK); - - hjpeg->State= HAL_JPEG_STATE_READY; - hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; - HAL_JPEG_ErrorCallback(hjpeg); - } -} - -/** - * @brief DMA output Abort callback - * @param hdma: pointer to a DMA_HandleTypeDef structure. - * @retval None - */ -static void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma) -{ - JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - if((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0) - { - JPEG_DMA_EndProcess(hjpeg); - } -} - -/** - * @brief Calculate the decoded image quality (from 1 to 100) - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval JPEG image quality from 1 to 100. - */ -static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg) -{ - uint32_t quality = 0; - uint32_t quantRow, quantVal,scale, i, j; - uint32_t *tableAddress = (uint32_t *)hjpeg->Instance->QMEM0; - - i = 0; - while( i < JPEG_QUANT_TABLE_SIZE) - { - quantRow = *tableAddress; - for(j=0; j<4; j++) - { - quantVal = (quantRow >> (8 * j)) & 0xFF; - if(quantVal == 1) - { - /* if Quantization value = 1 then quality is 100%*/ - quality += 100; - } - else - { - /* Note that the quantization coefficients must be specified in the table in zigzag order */ - scale = (quantVal*100)/((uint32_t) JPEG_LUM_QuantTable[JPEG_ZIGZAG_ORDER[i+j]]); - - if(scale <= 100) - { - quality += (200 - scale)/2; - } - else - { - quality += 5000/scale; - } - } - } - - i += 4; - tableAddress ++; - } - - return (quality/((uint32_t)64)); -} -/** - * @} - */ - -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#endif /* HAL_JPEG_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_lptim.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_lptim.c deleted file mode 100644 index f0d2a27..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_lptim.c +++ /dev/null @@ -1,1705 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_lptim.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief LPTIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Low Power Timer (LPTIM) peripheral: - * + Initialization and de-initialization functions. - * + Start/Stop operation functions in polling mode. - * + Start/Stop operation functions in interrupt mode. - * + Reading operation functions. - * + Peripheral State functions. - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LPTIM HAL driver can be used as follows: - - (#)Initialize the LPTIM low level resources by implementing the - HAL_LPTIM_MspInit(): - (##) Enable the LPTIM interface clock using __LPTIMx_CLK_ENABLE(). - (##) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()): - (+) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority(). - (+) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ(). - (+) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler(). - - (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function - configures mainly: - (##) The instance: LPTIM1. - (##) Clock: the counter clock. - - Source : it can be either the ULPTIM input (IN1) or one of - the internal clock; (APB, LSE, LSI or MSI). - - Prescaler: select the clock divider. - (##) UltraLowPowerClock : To be used only if the ULPTIM is selected - as counter clock source. - - Polarity: polarity of the active edge for the counter unit - if the ULPTIM input is selected. - - SampleTime: clock sampling time to configure the clock glitch - filter. - (##) Trigger: How the counter start. - - Source: trigger can be software or one of the hardware triggers. - - ActiveEdge : only for hardware trigger. - - SampleTime : trigger sampling time to configure the trigger - glitch filter. - (##) OutputPolarity : 2 opposite polarities are possibles. - (##) UpdateMode: specifies whether the update of the autoreload and - the compare values is done immediately or after the end of current - period. - - (#)Six modes are available: - - (##) PWM Mode: To generate a PWM signal with specified period and pulse, - call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption - mode. - - (##) One Pulse Mode: To generate pulse with specified width in response - to a stimulus, call HAL_LPTIM_OnePulse_Start() or - HAL_LPTIM_OnePulse_Start_IT() for interruption mode. - - (##) Set once Mode: In this mode, the output changes the level (from - low level to high level if the output polarity is configured high, else - the opposite) when a compare match occurs. To start this mode, call - HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for - interruption mode. - - (##) Encoder Mode: To use the encoder interface call - HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for - interruption mode. - - (##) Time out Mode: an active edge on one selected trigger input rests - the counter. The first trigger event will start the timer, any - successive trigger event will reset the counter and the timer will - restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or - HAL_LPTIM_TimeOut_Start_IT() for interruption mode. - - (##) Counter Mode: counter can be used to count external events on - the LPTIM Input1 or it can be used to count internal clock cycles. - To start this mode, call HAL_LPTIM_Counter_Start() or - HAL_LPTIM_Counter_Start_IT() for interruption mode. - - - (#) User can stop any process by calling the corresponding API: - HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is - already started in interruption mode. - - (#)Call HAL_LPTIM_DeInit() to deinitialize the LPTIM peripheral. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup LPTIM LPTIM - * @brief LPTIM HAL module driver. - * @{ - */ - -#ifdef HAL_LPTIM_MODULE_ENABLED -/* Private types -------------------------------------------------------------*/ -/** @defgroup LPTIM_Private_Types LPTIM Private Types - * @{ - */ - -/** - * @} - */ - -/* Private defines -----------------------------------------------------------*/ -/** @defgroup LPTIM_Private_Defines LPTIM Private Defines - * @{ - */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @addtogroup LPTIM_Private_Variables LPTIM Private Variables - * @{ - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup LPTIM_Private_Constants LPTIM Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup LPTIM_Private_Macros LPTIM Private Macros - * @{ - */ - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup LPTIM_Private_Functions_Prototypes LPTIM Private Functions Prototypes - * @{ - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup LPTIM_Private_Functions LPTIM Private Functions - * @{ - */ - -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ -/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions - * @{ - */ - -/** @defgroup LPTIM_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions. - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the LPTIM according to the specified parameters in the - LPTIM_InitTypeDef and creates the associated handle. - (+) DeInitialize the LPTIM peripheral. - (+) Initialize the LPTIM MSP. - (+) DeInitialize LPTIM MSP. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the LPTIM according to the specified parameters in the - * LPTIM_InitTypeDef and creates the associated handle. - * @param hlptim: LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) -{ - uint32_t tmpcfgr = 0; - - /* Check the LPTIM handle allocation */ - if(hlptim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); - assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); - if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) - { - assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); - assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); - } - assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source)); - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) - { - assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); - assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge)); - } - assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); - assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); - assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource)); - - if(hlptim->State == HAL_LPTIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hlptim->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ - HAL_LPTIM_MspInit(hlptim); - } - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Get the LPTIMx CFGR value */ - tmpcfgr = hlptim->Instance->CFGR; - - if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) - { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); - } - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) - { - tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); - } - - /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | - LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE )); - - /* Set initialization parameters */ - tmpcfgr |= (hlptim->Init.Clock.Source | - hlptim->Init.Clock.Prescaler | - hlptim->Init.OutputPolarity | - hlptim->Init.UpdateMode | - hlptim->Init.CounterSource); - - if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) - { - tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | - hlptim->Init.UltraLowPowerClock.SampleTime); - } - - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) - { - /* Enable External trigger and set the trigger source */ - tmpcfgr |= (hlptim->Init.Trigger.Source | - hlptim->Init.Trigger.ActiveEdge | - hlptim->Init.Trigger.SampleTime); - } - - /* Write to LPTIMx CFGR */ - hlptim->Instance->CFGR = tmpcfgr; - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief DeInitializes the LPTIM peripheral. - * @param hlptim: LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the LPTIM handle allocation */ - if(hlptim == NULL) - { - return HAL_ERROR; - } - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Disable the LPTIM Peripheral Clock */ - __HAL_LPTIM_DISABLE(hlptim); - - /* DeInit the low level hardware: CLOCK, NVIC.*/ - HAL_LPTIM_MspDeInit(hlptim); - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hlptim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the LPTIM MSP. - * @param hlptim: LPTIM handle - * @retval None - */ -__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hlptim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_LPTIM_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes LPTIM MSP. - * @param hlptim: LPTIM handle - * @retval None - */ -__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hlptim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_LPTIM_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup LPTIM_Group2 LPTIM Start-Stop operation functions - * @brief Start-Stop operation functions. - * -@verbatim - ============================================================================== - ##### LPTIM Start Stop operation functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Start the PWM mode. - (+) Stop the PWM mode. - (+) Start the One pulse mode. - (+) Stop the One pulse mode. - (+) Start the Set once mode. - (+) Stop the Set once mode. - (+) Start the Encoder mode. - (+) Stop the Encoder mode. - (+) Start the Timeout mode. - (+) Stop the Timeout mode. - (+) Start the Counter mode. - (+) Stop the Counter mode. - - -@endverbatim - * @{ - */ - -/** - * @brief Starts the LPTIM PWM generation. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse : Specifies the compare value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - assert_param(IS_LPTIM_PULSE(Pulse)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Reset WAVE bit to set PWM mode */ - hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - - /* Start timer in continuous mode */ - __HAL_LPTIM_START_CONTINUOUS(hlptim); - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the LPTIM PWM generation. - * @param hlptim : LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the LPTIM PWM generation in interrupt mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF - * @param Pulse : Specifies the compare value. - * This parameter must be a value between 0x0000 and 0xFFFF - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - assert_param(IS_LPTIM_PULSE(Pulse)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Reset WAVE bit to set PWM mode */ - hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; - - /* Enable Autoreload write complete interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); - - /* Enable Compare write complete interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK); - - /* Enable Autoreload match interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); - - /* Enable Compare match interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); - - /* If external trigger source is used, then enable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) - { - /* Enable external trigger interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); - } - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - - /* Start timer in continuous mode */ - __HAL_LPTIM_START_CONTINUOUS(hlptim); - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the LPTIM PWM generation in interrupt mode. - * @param hlptim : LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - /* Disable Autoreload write complete interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); - - /* Disable Compare write complete interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK); - - /* Disable Autoreload match interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - - /* Disable Compare match interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); - - /* If external trigger source is used, then disable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) - { - /* Disable external trigger interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); - } - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the LPTIM One pulse generation. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse : Specifies the compare value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - assert_param(IS_LPTIM_PULSE(Pulse)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Reset WAVE bit to set one pulse mode */ - hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - - /* Start timer in continuous mode */ - __HAL_LPTIM_START_SINGLE(hlptim); - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the LPTIM One pulse generation. - * @param hlptim : LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the LPTIM One pulse generation in interrupt mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse : Specifies the compare value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - assert_param(IS_LPTIM_PULSE(Pulse)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Reset WAVE bit to set one pulse mode */ - hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; - - /* Enable Autoreload write complete interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); - - /* Enable Compare write complete interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK); - - /* Enable Autoreload match interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); - - /* Enable Compare match interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); - - /* If external trigger source is used, then enable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) - { - /* Enable external trigger interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); - } - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - - /* Start timer in continuous mode */ - __HAL_LPTIM_START_SINGLE(hlptim); - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the LPTIM One pulse generation in interrupt mode. - * @param hlptim : LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - /* Disable Autoreload write complete interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); - - /* Disable Compare write complete interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK); - - /* Disable Autoreload match interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - - /* Disable Compare match interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); - - /* If external trigger source is used, then disable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) - { - /* Disable external trigger interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); - } - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the LPTIM in Set once mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse : Specifies the compare value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - assert_param(IS_LPTIM_PULSE(Pulse)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Set WAVE bit to enable the set once mode */ - hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - - /* Start timer in continuous mode */ - __HAL_LPTIM_START_SINGLE(hlptim); - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the LPTIM Set once mode. - * @param hlptim : LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the LPTIM Set once mode in interrupt mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse : Specifies the compare value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - assert_param(IS_LPTIM_PULSE(Pulse)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Set WAVE bit to enable the set once mode */ - hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; - - /* Enable Autoreload write complete interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); - - /* Enable Compare write complete interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK); - - /* Enable Autoreload match interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); - - /* Enable Compare match interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); - - /* If external trigger source is used, then enable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) - { - /* Enable external trigger interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); - } - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - - /* Start timer in continuous mode */ - __HAL_LPTIM_START_SINGLE(hlptim); - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the LPTIM Set once mode in interrupt mode. - * @param hlptim : LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - /* Disable Autoreload write complete interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); - - /* Disable Compare write complete interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK); - - /* Disable Autoreload match interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - - /* Disable Compare match interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); - - /* If external trigger source is used, then disable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) - { - /* Disable external trigger interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); - } - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the Encoder interface. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period) -{ - uint32_t tmpcfgr = 0; - - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC); - assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1); - assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Get the LPTIMx CFGR value */ - tmpcfgr = hlptim->Instance->CFGR; - - /* Clear CKPOL bits */ - tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL); - - /* Set Input polarity */ - tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity; - - /* Write to LPTIMx CFGR */ - hlptim->Instance->CFGR = tmpcfgr; - - /* Set ENC bit to enable the encoder interface */ - hlptim->Instance->CFGR |= LPTIM_CFGR_ENC; - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Start timer in continuous mode */ - __HAL_LPTIM_START_CONTINUOUS(hlptim); - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the Encoder interface. - * @param hlptim : LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - /* Reset ENC bit to disable the encoder interface */ - hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the Encoder interface in interrupt mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period) -{ - uint32_t tmpcfgr = 0; - - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC); - assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1); - assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Configure edge sensitivity for encoder mode */ - /* Get the LPTIMx CFGR value */ - tmpcfgr = hlptim->Instance->CFGR; - - /* Clear CKPOL bits */ - tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL); - - /* Set Input polarity */ - tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity; - - /* Write to LPTIMx CFGR */ - hlptim->Instance->CFGR = tmpcfgr; - - /* Set ENC bit to enable the encoder interface */ - hlptim->Instance->CFGR |= LPTIM_CFGR_ENC; - - /* Enable "switch to down direction" interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN); - - /* Enable "switch to up direction" interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP); - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Start timer in continuous mode */ - __HAL_LPTIM_START_CONTINUOUS(hlptim); - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the Encoder interface in interrupt mode. - * @param hlptim : LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - /* Reset ENC bit to disable the encoder interface */ - hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; - - /* Disable "switch to down direction" interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN); - - /* Disable "switch to up direction" interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP); - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the Timeout function. The first trigger event will start the - * timer, any successive trigger event will reset the counter and - * the timer restarts. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Timeout : Specifies the TimeOut value to rest the counter. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - assert_param(IS_LPTIM_PULSE(Timeout)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Set TIMOUT bit to enable the timeout function */ - hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Load the Timeout value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Timeout); - - /* Start timer in continuous mode */ - __HAL_LPTIM_START_CONTINUOUS(hlptim); - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the Timeout function. - * @param hlptim : LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - /* Reset TIMOUT bit to enable the timeout function */ - hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the Timeout function in interrupt mode. The first trigger - * event will start the timer, any successive trigger event will reset - * the counter and the timer restarts. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Timeout : Specifies the TimeOut value to rest the counter. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - assert_param(IS_LPTIM_PULSE(Timeout)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */ - __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); - - /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */ - __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); - - /* Set TIMOUT bit to enable the timeout function */ - hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; - - /* Enable Compare match interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Load the Timeout value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Timeout); - - /* Start timer in continuous mode */ - __HAL_LPTIM_START_CONTINUOUS(hlptim); - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the Timeout function in interrupt mode. - * @param hlptim : LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ - __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); - - /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ - __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - /* Reset TIMOUT bit to enable the timeout function */ - hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; - - /* Disable Compare match interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the Counter mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ - if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) - { - /* Check if clock is prescaled */ - assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); - /* Set clock prescaler to 0 */ - hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC; - } - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Start timer in continuous mode */ - __HAL_LPTIM_START_CONTINUOUS(hlptim); - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the Counter mode. - * @param hlptim : LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the Counter mode in interrupt mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */ - __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); - - /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */ - __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); - - /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ - if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) - { - /* Check if clock is prescaled */ - assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); - /* Set clock prescaler to 0 */ - hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC; - } - - /* Enable Autoreload write complete interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); - - /* Enable Autoreload match interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Start timer in continuous mode */ - __HAL_LPTIM_START_CONTINUOUS(hlptim); - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the Counter mode in interrupt mode. - * @param hlptim : LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - - /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ - __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); - - /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ - __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - /* Disable Autoreload write complete interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); - - /* Disable Autoreload match interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup LPTIM_Group3 LPTIM Read operation functions - * @brief Read operation functions. - * -@verbatim - ============================================================================== - ##### LPTIM Read operation functions ##### - ============================================================================== -[..] This section provides LPTIM Reading functions. - (+) Read the counter value. - (+) Read the period (Auto-reload) value. - (+) Read the pulse (Compare)value. -@endverbatim - * @{ - */ - -/** - * @brief This function returns the current counter value. - * @param hlptim: LPTIM handle - * @retval Counter value. - */ -uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - return (hlptim->Instance->CNT); -} - -/** - * @brief This function return the current Autoreload (Period) value. - * @param hlptim: LPTIM handle - * @retval Autoreload value. - */ -uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - return (hlptim->Instance->ARR); -} - -/** - * @brief This function return the current Compare (Pulse) value. - * @param hlptim: LPTIM handle - * @retval Compare value. - */ -uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - return (hlptim->Instance->CMP); -} - -/** - * @} - */ - - - -/** @defgroup LPTIM_Group4 LPTIM IRQ handler - * @brief LPTIM IRQ handler. - * -@verbatim - ============================================================================== - ##### LPTIM IRQ handler ##### - ============================================================================== -[..] This section provides LPTIM IRQ handler function. - -@endverbatim - * @{ - */ - -/** - * @brief This function handles LPTIM interrupt request. - * @param hlptim: LPTIM handle - * @retval None - */ -void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) -{ - /* Compare match interrupt */ - if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET) - { - if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) !=RESET) - { - /* Clear Compare match flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM); - /* Compare match Callback */ - HAL_LPTIM_CompareMatchCallback(hlptim); - } - } - - /* Autoreload match interrupt */ - if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET) - { - if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) !=RESET) - { - /* Clear Autoreload match flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM); - /* Autoreload match Callback */ - HAL_LPTIM_AutoReloadMatchCallback(hlptim); - } - } - - /* Trigger detected interrupt */ - if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET) - { - if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) !=RESET) - { - /* Clear Trigger detected flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG); - /* Trigger detected callback */ - HAL_LPTIM_TriggerCallback(hlptim); - } - } - - /* Compare write interrupt */ - if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET) - { - if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CMPM) !=RESET) - { - /* Clear Compare write flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); - /* Compare write Callback */ - HAL_LPTIM_CompareWriteCallback(hlptim); - } - } - - /* Autoreload write interrupt */ - if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET) - { - if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) !=RESET) - { - /* Clear Autoreload write flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); - /* Autoreload write Callback */ - HAL_LPTIM_AutoReloadWriteCallback(hlptim); - } - } - - /* Direction counter changed from Down to Up interrupt */ - if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET) - { - if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) !=RESET) - { - /* Clear Direction counter changed from Down to Up flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP); - /* Direction counter changed from Down to Up Callback */ - HAL_LPTIM_DirectionUpCallback(hlptim); - } - } - - /* Direction counter changed from Up to Down interrupt */ - if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET) - { - if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) !=RESET) - { - /* Clear Direction counter changed from Up to Down flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN); - /* Direction counter changed from Up to Down Callback */ - HAL_LPTIM_DirectionDownCallback(hlptim); - } - } - - __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG(); -} - -/** - * @brief Compare match callback in non blocking mode - * @param hlptim : LPTIM handle - * @retval None - */ -__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hlptim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_LPTIM_CompareMatchCallback could be implemented in the user file - */ -} - -/** - * @brief Autoreload match callback in non blocking mode - * @param hlptim : LPTIM handle - * @retval None - */ -__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hlptim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file - */ -} - -/** - * @brief Trigger detected callback in non blocking mode - * @param hlptim : LPTIM handle - * @retval None - */ -__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hlptim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_LPTIM_TriggerCallback could be implemented in the user file - */ -} - -/** - * @brief Compare write callback in non blocking mode - * @param hlptim : LPTIM handle - * @retval None - */ -__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hlptim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_LPTIM_CompareWriteCallback could be implemented in the user file - */ -} - -/** - * @brief Autoreload write callback in non blocking mode - * @param hlptim : LPTIM handle - * @retval None - */ -__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hlptim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file - */ -} - -/** - * @brief Direction counter changed from Down to Up callback in non blocking mode - * @param hlptim : LPTIM handle - * @retval None - */ -__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hlptim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_LPTIM_DirectionUpCallback could be implemented in the user file - */ -} - -/** - * @brief Direction counter changed from Up to Down callback in non blocking mode - * @param hlptim : LPTIM handle - * @retval None - */ -__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hlptim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_LPTIM_DirectionDownCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup LPTIM_Group5 Peripheral State functions - * @brief Peripheral State functions. - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the LPTIM state. - * @param hlptim: LPTIM handle - * @retval HAL state - */ -HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) -{ - return hlptim->State; -} - -/** - * @} - */ - - -/** - * @} - */ - -#endif /* HAL_LPTIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c deleted file mode 100644 index b4eb39f..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c +++ /dev/null @@ -1,1915 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_ltdc.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief LTDC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the LTDC peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Program the required configuration through the following parameters: - the LTDC timing, the horizontal and vertical polarity, - the pixel clock polarity, Data Enable polarity and the LTDC background color value - using HAL_LTDC_Init() function - - (#) Program the required configuration through the following parameters: - the pixel format, the blending factors, input alpha value, the window size - and the image size using HAL_LTDC_ConfigLayer() function for foreground - or/and background layer. - - (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and - HAL_LTDC_EnableCLUT functions. - - (#) Optionally, enable the Dither using HAL_LTDC_EnableDither(). - - (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying() - and HAL_LTDC_EnableColorKeying functions. - - (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent() - function - - (#) If needed, reconfigure and change the pixel format value, the alpha value - value, the window size, the window position and the layer start address - for foreground or/and background layer using respectively the following - functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(), - HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetAddress. - - (#) Variant functions with “_NoReload” post fix allows to set the LTDC configuration/settings without immediate reload. - This is useful in case when the program requires to modify serval LTDC settings (on one or both layers) - then applying(reload) these settings in one shot by calling the function “HAL_LTDC_Reload” - - After calling the “_NoReload” functions to set different color/format/layer settings, - the program can call the function “HAL_LTDC_Reload” To apply(Reload) these settings. - Function “HAL_LTDC_Reload” can be called with the parameter “ReloadType” - set to LTDC_RELOAD_IMMEDIATE if an immediate reload is required. - Function “HAL_LTDC_Reload” can be called with the parameter “ReloadType” - set to LTDC_RELOAD_VERTICAL_BLANKING if the reload should be done in the next vertical blanking period, - this option allows to avoid display flicker by applying the new settings during the vertical blanking period. - - - (#) To control LTDC state you can use the following function: HAL_LTDC_GetState() - - *** LTDC HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in LTDC HAL driver. - - (+) __HAL_LTDC_ENABLE: Enable the LTDC. - (+) __HAL_LTDC_DISABLE: Disable the LTDC. - (+) __HAL_LTDC_LAYER_ENABLE: Enable the LTDC Layer. - (+) __HAL_LTDC_LAYER_DISABLE: Disable the LTDC Layer. - (+) __HAL_LTDC_RELOAD_CONFIG: Reload Layer Configuration. - (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags. - (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags. - (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts. - (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts. - (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not. - - [..] - (@) You can refer to the LTDC HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - -/** @defgroup LTDC LTDC - * @brief LTDC HAL module driver - * @{ - */ - -#ifdef HAL_LTDC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup LTDC_Exported_Functions LTDC Exported Functions - * @{ - */ - -/** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the LTDC - (+) De-initialize the LTDC - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the LTDC according to the specified - * parameters in the LTDC_InitTypeDef and create the associated handle. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) -{ - uint32_t tmp = 0, tmp1 = 0; - - /* Check the LTDC peripheral state */ - if(hltdc == NULL) - { - return HAL_ERROR; - } - - /* Check function parameters */ - assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance)); - assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync)); - assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync)); - assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP)); - assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP)); - assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH)); - assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW)); - assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh)); - assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth)); - assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity)); - assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity)); - assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity)); - assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity)); - - if(hltdc->State == HAL_LTDC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hltdc->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ - HAL_LTDC_MspInit(hltdc); - } - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Configures the HS, VS, DE and PC polarity */ - hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL); - hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ - hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); - - /* Sets Synchronization size */ - hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); - tmp = (hltdc->Init.HorizontalSync << 16); - hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync); - - /* Sets Accumulated Back porch */ - hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); - tmp = (hltdc->Init.AccumulatedHBP << 16); - hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP); - - /* Sets Accumulated Active Width */ - hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); - tmp = (hltdc->Init.AccumulatedActiveW << 16); - hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH); - - /* Sets Total Width */ - hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); - tmp = (hltdc->Init.TotalWidth << 16); - hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh); - - /* Sets the background color value */ - tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8); - tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16); - hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED); - hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue); - - /* Enable the transfer Error interrupt */ - __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE); - - /* Enable the FIFO underrun interrupt */ - __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_FU); - - /* Enable LTDC by setting LTDCEN bit */ - __HAL_LTDC_ENABLE(hltdc); - - /* Initialize the error code */ - hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; - - /* Initialize the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Deinitializes the LTDC peripheral registers to their default reset - * values. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval None - */ - -HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc) -{ - /* DeInit the low level hardware */ - HAL_LTDC_MspDeInit(hltdc); - - /* Initialize the error code */ - hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; - - /* Initialize the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Initializes the LTDC MSP. - * @param hltdc : pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval None - */ -__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hltdc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_LTDC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the LTDC MSP. - * @param hltdc : pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval None - */ -__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hltdc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_LTDC_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides function allowing to: - (+) Handle LTDC interrupt request - -@endverbatim - * @{ - */ -/** - * @brief Handles LTDC interrupt request. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval HAL status - */ -void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) -{ - /* Transfer Error Interrupt management ***************************************/ - if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_TE) != RESET) - { - if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_TE) != RESET) - { - /* Disable the transfer Error interrupt */ - __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE); - - /* Clear the transfer error flag */ - __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE); - - /* Update error code */ - hltdc->ErrorCode |= HAL_LTDC_ERROR_TE; - - /* Change LTDC state */ - hltdc->State = HAL_LTDC_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - /* Transfer error Callback */ - HAL_LTDC_ErrorCallback(hltdc); - } - } - /* FIFO underrun Interrupt management ***************************************/ - if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_FU) != RESET) - { - if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_FU) != RESET) - { - /* Disable the FIFO underrun interrupt */ - __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU); - - /* Clear the FIFO underrun flag */ - __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU); - - /* Update error code */ - hltdc->ErrorCode |= HAL_LTDC_ERROR_FU; - - /* Change LTDC state */ - hltdc->State = HAL_LTDC_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - /* Transfer error Callback */ - HAL_LTDC_ErrorCallback(hltdc); - } - } - /* Line Interrupt management ************************************************/ - if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_LI) != RESET) - { - if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_LI) != RESET) - { - /* Disable the Line interrupt */ - __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); - - /* Clear the Line interrupt flag */ - __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI); - - /* Change LTDC state */ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - /* Line interrupt Callback */ - HAL_LTDC_LineEvenCallback(hltdc); - } - } - /* Register reload Interrupt management ***************************************/ - if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_RR) != RESET) - { - if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_RR) != RESET) - { - /* Disable the register reload interrupt */ - __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR); - - /* Clear the register reload flag */ - __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR); - - /* Change LTDC state */ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - /* Register reload interrupt Callback */ - HAL_LTDC_ReloadEventCallback(hltdc); - } - } -} - -/** - * @brief Error LTDC callback. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval None - */ -__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hltdc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_LTDC_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief Line Event callback. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval None - */ -__weak void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hltdc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_LTDC_LineEvenCallback could be implemented in the user file - */ -} - -/** - * @brief Reload Event callback. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval None - */ -__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hltdc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_LTDC_ReloadEvenCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the LTDC foreground or/and background parameters. - (+) Set the active layer. - (+) Configure the color keying. - (+) Configure the C-LUT. - (+) Enable / Disable the color keying. - (+) Enable / Disable the C-LUT. - (+) Update the layer position. - (+) Update the layer size. - (+) Update pixel format on the fly. - (+) Update transparency on the fly. - (+) Update address on the fly. - -@endverbatim - * @{ - */ - -/** - * @brief Configure the LTDC Layer according to the specified - * parameters in the LTDC_InitTypeDef and create the associated handle. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param pLayerCfg: pointer to a LTDC_LayerCfgTypeDef structure that contains - * the configuration information for the Layer. - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) -{ - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat)); - assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); - assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); - assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); - assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); - assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); - assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); - assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); - assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); - assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); - - /* Copy new layer configuration into handle structure */ - hltdc->LayerCfg[LayerIdx] = *pLayerCfg; - - /* Configure the LTDC Layer */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Sets the Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Initialize the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Configure the color keying. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param RGBValue: the color key value - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx) -{ - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Configures the default color values */ - LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); - LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue; - - /* Sets the Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Load the color lookup table. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param pCLUT: pointer to the color lookup table address. - * @param CLUTSize: the color lookup table size. - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx) -{ - uint32_t tmp = 0; - uint32_t counter = 0; - uint32_t pcounter = 0; - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - for(counter = 0; (counter < CLUTSize); counter++) - { - if(hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44) - { - tmp = (((counter + 16*counter) << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000)); - } - else - { - tmp = ((counter << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000)); - } - pcounter = (uint32_t)pCLUT + sizeof(*pCLUT); - pCLUT = (uint32_t *)pcounter; - - /* Specifies the C-LUT address and RGB value */ - LTDC_LAYER(hltdc, LayerIdx)->CLUTWR = tmp; - } - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Enable the color keying. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) -{ - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Enable LTDC color keying by setting COLKEN bit */ - LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN; - - /* Sets the Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Disable the color keying. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) -{ - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Disable LTDC color keying by setting COLKEN bit */ - LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; - - /* Sets the Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Enable the color lookup table. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) -{ - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Disable LTDC color lookup table by setting CLUTEN bit */ - LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN; - - /* Sets the Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Disable the color lookup table. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) -{ - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Disable LTDC color lookup table by setting CLUTEN bit */ - LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; - - /* Sets the Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Enables Dither. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc) -{ - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Enable Dither by setting DTEN bit */ - LTDC->GCR |= (uint32_t)LTDC_GCR_DEN; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Disables Dither. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc) -{ - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Disable Dither by setting DTEN bit */ - LTDC->GCR &= ~(uint32_t)LTDC_GCR_DEN; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Set the LTDC window size. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param XSize: LTDC Pixel per line - * @param YSize: LTDC Line number - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) -{ - LTDC_LayerCfgTypeDef *pLayerCfg; - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; - - /* Check the parameters (Layers parameters)*/ - assert_param(IS_LTDC_LAYER(LayerIdx)); - assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); - assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); - assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); - assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); - assert_param(IS_LTDC_CFBLL(XSize)); - assert_param(IS_LTDC_CFBLNBR(YSize)); - - /* update horizontal start/stop */ - pLayerCfg->WindowX0 = 0; - pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; - - /* update vertical start/stop */ - pLayerCfg->WindowY0 = 0; - pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; - - /* Reconfigures the color frame buffer pitch in byte */ - pLayerCfg->ImageWidth = XSize; - - /* Reconfigures the frame buffer line number */ - pLayerCfg->ImageHeight = YSize; - - /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Sets the Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Set the LTDC window position. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param X0: LTDC window X offset - * @param Y0: LTDC window Y offset - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) -{ - LTDC_LayerCfgTypeDef *pLayerCfg; - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); - assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); - assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); - assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); - - /* update horizontal start/stop */ - pLayerCfg->WindowX0 = X0; - pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth; - - /* update vertical start/stop */ - pLayerCfg->WindowY0 = Y0; - pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight; - - /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Sets the Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Reconfigure the pixel format. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param Pixelformat: new pixel format value. - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx) -{ - LTDC_LayerCfgTypeDef *pLayerCfg; - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat)); - - /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; - - /* Reconfigure the pixel format */ - pLayerCfg->PixelFormat = Pixelformat; - - /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Sets the Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Reconfigure the layer alpha value. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param Alpha: new alpha value. - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx) -{ - LTDC_LayerCfgTypeDef *pLayerCfg; - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_ALPHA(Alpha)); - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; - - /* Reconfigure the Alpha value */ - pLayerCfg->Alpha = Alpha; - - /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Sets the Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} -/** - * @brief Reconfigure the frame buffer Address. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param Address: new address value. - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx) -{ - LTDC_LayerCfgTypeDef *pLayerCfg; - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; - - /* Reconfigure the Address */ - pLayerCfg->FBStartAdress = Address; - - /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Sets the Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is - * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we - * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels - * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). - * Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch - * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param LinePitchInPixels: New line pitch in pixels to configure for LTDC layer 'LayerIdx'. - * @param LayerIdx: LTDC layer index concerned by the modification of line pitch. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) -{ - uint32_t tmp = 0; - uint32_t pitchUpdate = 0; - uint32_t pixelFormat = 0; - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* get LayerIdx used pixel format */ - pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; - - if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) - { - tmp = 4; - } - else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) - { - tmp = 3; - } - else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ - (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ - (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ - (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) - { - tmp = 2; - } - else - { - tmp = 1; - } - - pitchUpdate = ((LinePitchInPixels * tmp) << 16); - - /* Clear previously set standard pitch */ - LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; - - /* Sets the Reload type as immediate update of LTDC pitch configured above */ - LTDC->SRCR |= LTDC_SRCR_IMR; - - /* Set new line pitch value */ - LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; - - /* Sets the Reload type as immediate update of LTDC pitch configured above */ - LTDC->SRCR |= LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Define the position of the line interrupt. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param Line: Line Interrupt Position. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line) -{ - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_LIPOS(Line)); - - /* Enable the Line interrupt */ - __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI); - - /* Sets the Line Interrupt position */ - LTDC->LIPCR = (uint32_t)Line; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief LTDC configuration reload. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param ReloadType: This parameter can be one of the following values : - * LTDC_RELOAD_IMMEDIATE : Immediate Reload - * LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType) -{ - assert_param(IS_LTDC_RELAOD(ReloadType)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Enable the Reload interrupt */ - __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR); - - /* Apply Reload type */ - hltdc->Instance->SRCR = ReloadType; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Configure the LTDC Layer according to the specified without reloading - * parameters in the LTDC_InitTypeDef and create the associated handle. - * Variant of the function HAL_LTDC_ConfigLayer without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param pLayerCfg: pointer to a LTDC_LayerCfgTypeDef structure that contains - * the configuration information for the Layer. - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) -{ - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat)); - assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); - assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); - assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); - assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); - assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); - assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); - assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); - assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); - assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); - - /* Copy new layer configuration into handle structure */ - hltdc->LayerCfg[LayerIdx] = *pLayerCfg; - - /* Configure the LTDC Layer */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Do not Sets the Reload */ - - /* Initialize the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Set the LTDC window size without reloading. - * Variant of the function HAL_LTDC_SetWindowSize without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param XSize: LTDC Pixel per line - * @param YSize: LTDC Line number - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) -{ - LTDC_LayerCfgTypeDef *pLayerCfg; - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; - - /* Check the parameters (Layers parameters)*/ - assert_param(IS_LTDC_LAYER(LayerIdx)); - assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); - assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); - assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); - assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); - assert_param(IS_LTDC_CFBLL(XSize)); - assert_param(IS_LTDC_CFBLNBR(YSize)); - - /* update horizontal start/stop */ - pLayerCfg->WindowX0 = 0; - pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; - - /* update vertical start/stop */ - pLayerCfg->WindowY0 = 0; - pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; - - /* Reconfigures the color frame buffer pitch in byte */ - pLayerCfg->ImageWidth = XSize; - - /* Reconfigures the frame buffer line number */ - pLayerCfg->ImageHeight = YSize; - - /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Do not Sets the Reload */ - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Set the LTDC window position without reloading. - * Variant of the function HAL_LTDC_SetWindowPosition without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param X0: LTDC window X offset - * @param Y0: LTDC window Y offset - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) -{ - LTDC_LayerCfgTypeDef *pLayerCfg; - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); - assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); - assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); - assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); - - /* update horizontal start/stop */ - pLayerCfg->WindowX0 = X0; - pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth; - - /* update vertical start/stop */ - pLayerCfg->WindowY0 = Y0; - pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight; - - /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Do not Sets the Reload */ - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Reconfigure the pixel format without reloading. - * Variant of the function HAL_LTDC_SetPixelFormat without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDfef structure that contains - * the configuration information for the LTDC. - * @param Pixelformat: new pixel format value. - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx) -{ - LTDC_LayerCfgTypeDef *pLayerCfg; - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat)); - - /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; - - /* Reconfigure the pixel format */ - pLayerCfg->PixelFormat = Pixelformat; - - /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Do not Sets the Reload */ - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Reconfigure the layer alpha value without reloading. - * Variant of the function HAL_LTDC_SetAlpha without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param Alpha: new alpha value. - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx) -{ - LTDC_LayerCfgTypeDef *pLayerCfg; - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_ALPHA(Alpha)); - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; - - /* Reconfigure the Alpha value */ - pLayerCfg->Alpha = Alpha; - - /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Do not Sets the Reload */ - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Reconfigure the frame buffer Address without reloading. - * Variant of the function HAL_LTDC_SetAddress without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param Address: new address value. - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx) -{ - LTDC_LayerCfgTypeDef *pLayerCfg; - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; - - /* Reconfigure the Address */ - pLayerCfg->FBStartAdress = Address; - - /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Do not Sets the Reload */ - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is - * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we - * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels - * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). - * Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch - * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). - * Variant of the function HAL_LTDC_SetPitch without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param LinePitchInPixels: New line pitch in pixels to configure for LTDC layer 'LayerIdx'. - * @param LayerIdx: LTDC layer index concerned by the modification of line pitch. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) -{ - uint32_t tmp = 0; - uint32_t pitchUpdate = 0; - uint32_t pixelFormat = 0; - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* get LayerIdx used pixel format */ - pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; - - if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) - { - tmp = 4; - } - else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) - { - tmp = 3; - } - else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ - (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ - (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ - (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) - { - tmp = 2; - } - else - { - tmp = 1; - } - - pitchUpdate = ((LinePitchInPixels * tmp) << 16); - - /* Clear previously set standard pitch */ - LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; - - /* Set new line pitch value */ - LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; - - /* Do not Sets the Reload */ - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - - -/** - * @brief Configure the color keying without reloading. - * Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param RGBValue: the color key value - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx) -{ - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Configures the default color values */ - LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); - LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue; - - /* Do not Sets the Reload */ - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Enable the color keying without reloading. - * Variant of the function HAL_LTDC_EnableColorKeying without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) -{ - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Enable LTDC color keying by setting COLKEN bit */ - LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN; - - /* Do not Sets the Reload */ - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Disable the color keying without reloading. - * Variant of the function HAL_LTDC_DisableColorKeying without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) -{ - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Disable LTDC color keying by setting COLKEN bit */ - LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; - - /* Do not Sets the Reload */ - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Enable the color lookup table without reloading. - * Variant of the function HAL_LTDC_EnableCLUT without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) -{ - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Disable LTDC color lookup table by setting CLUTEN bit */ - LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN; - - /* Do not Sets the Reload */ - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Disable the color lookup table without reloading. - * Variant of the function HAL_LTDC_DisableCLUT without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: - * 0 or 1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) -{ - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Disable LTDC color lookup table by setting CLUTEN bit */ - LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; - - /* Do not Sets the Reload */ - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the LTDC state. - (+) Get error code. - -@endverbatim - * @{ - */ - -/** - * @brief Return the LTDC state - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval HAL state - */ -HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) -{ - return hltdc->State; -} - -/** -* @brief Return the LTDC error code -* @param hltdc : pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. -* @retval LTDC Error Code -*/ -uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc) -{ - return hltdc->ErrorCode; -} - -/** - * @} - */ - -/** - * @brief Configures the LTDC peripheral - * @param hltdc : Pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param pLayerCfg: Pointer LTDC Layer Configuration structure - * @param LayerIdx: LTDC Layer index. - * This parameter can be one of the following values: 0 or 1 - * @retval None - */ -static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) -{ - uint32_t tmp = 0; - uint32_t tmp1 = 0; - uint32_t tmp2 = 0; - - /* Configures the horizontal start and stop position */ - tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16)) << 16); - LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); - LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16) + 1) | tmp); - - /* Configures the vertical start and stop position */ - tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16); - LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); - LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1) | tmp); - - /* Specifies the pixel format */ - LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF); - LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat); - - /* Configures the default color values */ - tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8); - tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16); - tmp2 = (pLayerCfg->Alpha0 << 24); - LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA); - LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); - - /* Specifies the constant alpha value */ - LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA); - LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha); - - /* Specifies the blending factors */ - LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1); - LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2); - - /* Configures the color frame buffer start address */ - LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD); - LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress); - - if(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) - { - tmp = 4; - } - else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888) - { - tmp = 3; - } - else if((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ - (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ - (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ - (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88)) - { - tmp = 2; - } - else - { - tmp = 1; - } - - /* Configures the color frame buffer pitch in byte */ - LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); - LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3)); - - /* Configures the frame buffer line number */ - LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); - LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight); - - /* Enable LTDC_Layer by setting LEN bit */ - LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN; -} - -/** - * @} - */ - -#endif /* HAL_LTDC_MODULE_ENABLED */ - -/** - * @} - */ -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c deleted file mode 100644 index a57438d..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c +++ /dev/null @@ -1,164 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_ltdc_ex.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief LTDC Extension HAL module driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -/** @defgroup LTDCEx LTDCEx - * @brief LTDC HAL module driver - * @{ - */ - -#ifdef HAL_LTDC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions - * @{ - */ - -/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the LTDC - -@endverbatim - * @{ - */ -#if defined (STM32F769xx) || defined (STM32F779xx) -/** - * @brief Retrieve common parameters from DSI Video mode configuration structure - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains - * the DSI video mode configuration parameters - * @note The implementation of this function is taking into account the LTDC - * polarities inversion as described in the current LTDC specification - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg) -{ - /* Retrieve signal polarities from DSI */ - - /* The following polarities are inverted: - LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH - LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH - LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ - - /* Note 1 : Code in line w/ Current LTDC specification */ - hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; - hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; - hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; - - /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ - /* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29; - hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29; - hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */ - - /* Retrieve vertical timing parameters from DSI */ - hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1; - hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1; - hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1; - hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1; - - return HAL_OK; -} - -/** - * @brief Retrieve common parameters from DSI Adapted command mode configuration structure - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains - * the DSI command mode configuration parameters - * @note The implementation of this function is taking into account the LTDC - * polarities inversion as described in the current LTDC specification - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg) -{ - /* Retrieve signal polarities from DSI */ - - /* The following polarities are inverted: - LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH - LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH - LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ - - /* Note 1 : Code in line w/ Current LTDC specification */ - hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; - hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; - hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; - - /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ - /* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29; - hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29; - hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */ - - return HAL_OK; -} -#endif /*STM32F769xx | STM32F779xx */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_LTCD_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mdios.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mdios.c deleted file mode 100644 index 42fb86c..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mdios.c +++ /dev/null @@ -1,629 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_mdios.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief MDIOS HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the MDIOS Peripheral. - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The MDIOS HAL driver can be used as follow: - - (#) Declare a MDIOS_HandleTypeDef handle structure. - - (#) Initialize the MDIOS low level resources by implementing the HAL_MDIOS_MspInit() API: - (##) Enable the MDIOS interface clock. - (##) MDIOS pins configuration: - (+++) Enable clocks for the MDIOS GPIOs. - (+++) Configure the MDIOS pins as alternate function. - (##) NVIC configuration if you need to use interrupt process: - (+++) Configure the MDIOS interrupt priority. - (+++) Enable the NVIC MDIOS IRQ handle. - - (#) Program the Port Address and the Preamble Check in the Init structure. - - (#) Initialize the MDIOS registers by calling the HAL_MDIOS_Init() API. - - (#) Perform direct slave read/write operations using the following APIs: - (##) Read the value of a DINn register: HAL_MDIOS_ReadReg() - (##) Write a value to a DOUTn register: HAL_MDIOS_WriteReg() - - (#) Get the Master read/write operations flags using the following APIs: - (##) Bit map of DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress() - (##) Bit map of DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress() - - (#) Clear the read/write flags using the following APIs: - (##) Clear read flags of a set of registers: HAL_MDIOS_ClearReadRegAddress() - (##) Clear write flags of a set of registers: HAL_MDIOS_ClearWriteRegAddress() - - (#) Enable interrupts on events using HAL_MDIOS_EnableEvents(), when called - the MDIOS will generate an interrupt in the following cases: - (##) a DINn register written by the Master - (##) a DOUTn register read by the Master - (##) an error occur - - (@) A callback is executed for each genereted interrupt, so the driver provide the following - HAL_MDIOS_WriteCpltCallback(), HAL_MDIOS_ReadCpltCallback() and HAL_MDIOS_ErrorCallback() - (@) HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt - and execute the previous callbacks - - (#) Reset the MDIOS peripheral and all related ressources by calling the HAL_MDIOS_DeInit() API. - (##) HAL_MDIOS_MspDeInit() must be implemented to reset low level ressources - (GPIO, Clocks, NVIC configuration ...) - - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup MDIOS MDIOS - * @brief HAL MDIOS module driver - * @{ - */ -#ifdef HAL_MDIOS_MODULE_ENABLED - -#if defined (MDIOS) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define MDIOS_PORT_ADDRESS_SHIFT ((uint32_t)8) -#define MDIOS_ALL_REG_FLAG ((uint32_t)0xFFFFFFFFU) -#define MDIOS_ALL_ERRORS_FLAG ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF)) - -#define MDIOS_DIN_BASE_ADDR (MDIOS_BASE + 0x100) -#define MDIOS_DOUT_BASE_ADDR (MDIOS_BASE + 0x180) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions - * @{ - */ - -/** @defgroup MDIOS_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the MDIOS - (+) The following parameters can be configured: - (++) Port Address - (++) Preamble Check - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the MDIOS according to the specified parameters in - * the MDIOS_InitTypeDef and creates the associated handle . - * @param hmdios: pointer to a MDIOS_HandleTypeDef structure that contains - * the configuration information for MDIOS module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios) -{ - uint32_t tmpcr = 0; - - /* Check the MDIOS handle allocation */ - if(hmdios == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance)); - assert_param(IS_MDIOS_PORTADDRESS(hmdios->Init.PortAddress)); - assert_param(IS_MDIOS_PREAMBLECHECK(hmdios->Init.PreambleCheck)); - - /* Process Locked */ - __HAL_LOCK(hmdios); - - if(hmdios->State == HAL_MDIOS_STATE_RESET) - { - /* Init the low level hardware */ - HAL_MDIOS_MspInit(hmdios); - } - - /* Change the MDIOS state */ - hmdios->State = HAL_MDIOS_STATE_BUSY; - - /* Get the MDIOS CR value */ - tmpcr = hmdios->Instance->CR; - - /* Clear PORT_ADDRESS, DPC and EN bits */ - tmpcr &= ((uint32_t)~(MDIOS_CR_EN | MDIOS_CR_DPC | MDIOS_CR_PORT_ADDRESS)); - - /* Set MDIOS control parametrs and enable the peripheral */ - tmpcr |= (uint32_t)(((hmdios->Init.PortAddress) << MDIOS_PORT_ADDRESS_SHIFT) |\ - (hmdios->Init.PreambleCheck) | \ - (MDIOS_CR_EN)); - - /* Write the MDIOS CR */ - hmdios->Instance->CR = tmpcr; - - /* Change the MDIOS state */ - hmdios->State = HAL_MDIOS_STATE_READY; - - /* Release Lock */ - __HAL_UNLOCK(hmdios); - - /* Return function status */ - return HAL_OK; - -} - -/** - * @brief DeInitializes the MDIOS peripheral. - * @param hmdios: MDIOS handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios) -{ - /* Check the MDIOS handle allocation */ - if(hmdios == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance)); - - /* Change the MDIOS state */ - hmdios->State = HAL_MDIOS_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_MDIOS_DISABLE(hmdios); - - /* DeInit the low level hardware */ - HAL_MDIOS_MspDeInit(hmdios); - - /* Change the MDIOS state */ - hmdios->State = HAL_MDIOS_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hmdios); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief MDIOS MSP Init - * @param hmdios: mdios handle - * @retval None - */ - __weak void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmdios); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MDIOS_MspInit can be implemented in the user file - */ -} - -/** - * @brief MDIOS MSP DeInit - * @param hmdios: mdios handle - * @retval None - */ - __weak void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmdios); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MDIOS_MspDeInit can be implemented in the user file - */ -} -/** - * @} - */ - -/** @defgroup MDIOS_Exported_Functions_Group2 IO operation functions - * @brief MDIOS Read/Write functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of functions allowing to manage the MDIOS - read and write operations. - - (#) APIs that allow to the MDIOS to read/write from/to the - values of one of the DINn/DOUTn registers: - (+) Read the value of a DINn register: HAL_MDIOS_ReadReg() - (+) Write a value to a DOUTn register: HAL_MDIOS_WriteReg() - - (#) APIs that provide if there are some Slave registres have been - read or written by the Master: - (+) DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress() - (+) DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress() - - (#) APIs that Clear the read/write flags: - (+) Clear read registers flags: HAL_MDIOS_ClearReadRegAddress() - (+) Clear write registers flags: HAL_MDIOS_ClearWriteRegAddress() - - (#) A set of Callbacks are provided: - (+) HAL_MDIOS_WriteCpltCallback() - (+) HAL_MDIOS_ReadCpltCallback() - (+) HAL_MDIOS_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Writes to an MDIOS output register - * @param hmdios: mdios handle - * @param RegNum: MDIOS input register number - * @param Data: Data to write - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data) -{ - uint32_t tmpreg; - - /* Check the parameters */ - assert_param(IS_MDIOS_REGISTER(RegNum)); - - /* Process Locked */ - __HAL_LOCK(hmdios); - - /* Get the addr of output register to be written by the MDIOS */ - tmpreg = MDIOS_DOUT_BASE_ADDR + (4 * RegNum); - - /* Write to DOUTn register */ - *((uint32_t *)tmpreg) = Data; - - /* Process Unlocked */ - __HAL_UNLOCK(hmdios); - - return HAL_OK; -} - -/** - * @brief Reads an MDIOS input register - * @param hmdios: mdios handle - * @param RegNum: MDIOS input register number - * @param pData: pointer to Data - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData) -{ - uint32_t tmpreg; - - /* Check the parameters */ - assert_param(IS_MDIOS_REGISTER(RegNum)); - - /* Process Locked */ - __HAL_LOCK(hmdios); - - /* Get the addr of input register to be read by the MDIOS */ - tmpreg = MDIOS_DIN_BASE_ADDR + (4 * RegNum); - - /* Read DINn register */ - *pData = (uint16_t)(*((uint32_t *)tmpreg)); - - /* Process Unlocked */ - __HAL_UNLOCK(hmdios); - - return HAL_OK; -} - -/** - * @brief Gets Written registers by MDIO master - * @param hmdios: mdios handle - * @retval bit map of written registers addresses - */ -uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios) -{ - return hmdios->Instance->WRFR; -} - -/** - * @brief Gets Read registers by MDIO master - * @param hmdios: mdios handle - * @retval bit map of read registers addresses - */ -uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios) -{ - return hmdios->Instance->RDFR; -} - -/** - * @brief Clears Write registers flag - * @param hmdios: mdios handle - * @param RegNum: registers addresses to be cleared - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum) -{ - /* Check the parameters */ - assert_param(IS_MDIOS_REGISTER(RegNum)); - - /* Process Locked */ - __HAL_LOCK(hmdios); - - /* Clear write registers flags */ - hmdios->Instance->CWRFR |= (RegNum); - - /* Release Lock */ - __HAL_UNLOCK(hmdios); - - return HAL_OK; -} - -/** - * @brief Clears Read register flag - * @param hmdios: mdios handle - * @param RegNum: registers addresses to be cleared - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum) -{ - /* Check the parameters */ - assert_param(IS_MDIOS_REGISTER(RegNum)); - - /* Process Locked */ - __HAL_LOCK(hmdios); - - /* Clear read registers flags */ - hmdios->Instance->CRDFR |= (RegNum); - - /* Release Lock */ - __HAL_UNLOCK(hmdios); - - return HAL_OK; -} - -/** - * @brief Enables Events for MDIOS peripheral - * @param hmdios: mdios handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios) -{ - /* Process Locked */ - __HAL_LOCK(hmdios); - - /* Enable MDIOS interrupts: Register Write, Register Read and Error ITs */ - __HAL_MDIOS_ENABLE_IT(hmdios, (MDIOS_IT_WRITE | MDIOS_IT_READ | MDIOS_IT_ERROR)); - - /* Process Unlocked */ - __HAL_UNLOCK(hmdios); - - return HAL_OK; -} - -/** - * @brief This function handles MDIOS interrupt request. - * @param hmdios: MDIOS handle - * @retval None - */ -void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios) -{ - /* Write Register Interrupt enabled ? */ - if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_WRITE) != RESET) - { - /* Write register flag */ - if(HAL_MDIOS_GetWrittenRegAddress(hmdios) != RESET) - { - /* Write callback function */ - HAL_MDIOS_WriteCpltCallback(hmdios); - - /* Clear write register flag */ - HAL_MDIOS_ClearWriteRegAddress(hmdios, MDIOS_ALL_REG_FLAG); - } - } - - /* Read Register Interrupt enabled ? */ - if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_READ) != RESET) - { - /* Read register flag */ - if(HAL_MDIOS_GetReadRegAddress(hmdios) != RESET) - { - /* Read callback function */ - HAL_MDIOS_ReadCpltCallback(hmdios); - - /* Clear read register flag */ - HAL_MDIOS_ClearReadRegAddress(hmdios, MDIOS_ALL_REG_FLAG); - } - } - - /* Error Interrupt enabled ? */ - if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_ERROR) != RESET) - { - /* All Errors Flag */ - if(__HAL_MDIOS_GET_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG) !=RESET) - { - /* Error Callback */ - HAL_MDIOS_ErrorCallback(hmdios); - - /* Clear errors flag */ - __HAL_MDIOS_CLEAR_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG); - } - } - - /* check MDIOS WAKEUP exti flag */ - if(__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG() != RESET) - { - /* MDIOS WAKEUP interrupt user callback */ - HAL_MDIOS_WakeUpCallback(hmdios); - - /* Clear MDIOS WAKEUP Exti pending bit */ - __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(); - } -} - -/** - * @brief Write Complete Callback - * @param hmdios: mdios handle - * @retval None - */ - __weak void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmdios); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MDIOS_WriteCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Read Complete Callback - * @param hmdios: mdios handle - * @retval None - */ - __weak void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmdios); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MDIOS_ReadCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Error Callback - * @param hmdios: mdios handle - * @retval None - */ - __weak void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmdios); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MDIOS_ErrorCallback can be implemented in the user file - */ -} - -/** - * @brief MDIOS WAKEUP interrupt callback - * @param hmdios: mdios handle - * @retval None - */ -__weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmdios); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_MDIOS_WakeUpCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup MDIOS_Exported_Functions_Group3 Peripheral Control functions - * @brief MDIOS control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the MDIOS. - (+) HAL_MDIOS_GetState() API, helpful to check in run-time the state. - (+) HAL_MDIOS_GetError() API, returns the errors occured during data transfer. - -@endverbatim - * @{ - */ - -/** - * @brief Gets MDIOS error flags - * @param hmdios: mdios handle - * @retval bit map of occured errors - */ -uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios) -{ - /* return errors flags on status register */ - return hmdios->Instance->SR; -} - -/** - * @brief Return the MDIOS HAL state - * @param hmdios: mdios handle - * @retval MDIOS state - */ -HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios) -{ - /* Return MDIOS state */ - return hmdios->State; -} - -/** - * @} - */ - -/** - * @} - */ -#endif /* MDIOS */ -#endif /* HAL_MDIOS_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nand.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nand.c deleted file mode 100644 index 355dca5..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nand.c +++ /dev/null @@ -1,1458 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_nand.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief NAND HAL module driver. - * This file provides a generic firmware to drive NAND memories mounted - * as external device. - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - This driver is a generic layered driver which contains a set of APIs used to - control NAND flash memories. It uses the FMC/FSMC layer functions to interface - with NAND devices. This driver is used as follows: - - (+) NAND flash memory configuration sequence using the function HAL_NAND_Init() - with control and timing parameters for both common and attribute spaces. - - (+) Read NAND flash memory maker and device IDs using the function - HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef - structure declared by the function caller. - - (+) Access NAND flash memory by read/write operations using the functions - HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea() - to read/write page(s)/spare area(s). These functions use specific device - information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef - structure. The read/write address information is contained by the Nand_Address_Typedef - structure passed as parameter. - - (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset(). - - (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block(). - The erase block address information is contained in the Nand_Address_Typedef - structure passed as parameter. - - (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status(). - - (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/ - HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction - feature or the function HAL_NAND_GetECC() to get the ECC correction code. - - (+) You can monitor the NAND device HAL state by calling the function - HAL_NAND_GetState() - - [..] - (@) This driver is a set of generic APIs which handle standard NAND flash operations. - If a NAND flash device contains different operations and/or implementations, - it should be implemented separately. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - - -#ifdef HAL_NAND_MODULE_ENABLED - -/** @defgroup NAND NAND - * @brief NAND HAL module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private Constants ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup NAND_Exported_Functions NAND Exported Functions - * @{ - */ - -/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - ============================================================================== - ##### NAND Initialization and de-initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to initialize/de-initialize - the NAND memory - -@endverbatim - * @{ - */ - -/** - * @brief Perform NAND memory Initialization sequence - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param ComSpace_Timing: pointer to Common space timing structure - * @param AttSpace_Timing: pointer to Attribute space timing structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing) -{ - /* Check the NAND handle state */ - if(hnand == NULL) - { - return HAL_ERROR; - } - - if(hnand->State == HAL_NAND_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hnand->Lock = HAL_UNLOCKED; - /* Initialize the low level hardware (MSP) */ - HAL_NAND_MspInit(hnand); - } - - /* Initialize NAND control Interface */ - FMC_NAND_Init(hnand->Instance, &(hnand->Init)); - - /* Initialize NAND common space timing Interface */ - FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank); - - /* Initialize NAND attribute space timing Interface */ - FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank); - - /* Enable the NAND device */ - __FMC_NAND_ENABLE(hnand->Instance); - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Perform NAND memory De-Initialization sequence - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) -{ - /* Initialize the low level hardware (MSP) */ - HAL_NAND_MspDeInit(hnand); - - /* Configure the NAND registers with their reset values */ - FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank); - - /* Reset the NAND controller state */ - hnand->State = HAL_NAND_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hnand); - - return HAL_OK; -} - -/** - * @brief NAND MSP Init - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval None - */ -__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hnand); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_NAND_MspInit could be implemented in the user file - */ -} - -/** - * @brief NAND MSP DeInit - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval None - */ -__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hnand); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_NAND_MspDeInit could be implemented in the user file - */ -} - - -/** - * @brief This function handles NAND device interrupt request. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval HAL status -*/ -void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) -{ - /* Check NAND interrupt Rising edge flag */ - if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE)) - { - /* NAND interrupt callback*/ - HAL_NAND_ITCallback(hnand); - - /* Clear NAND interrupt Rising edge pending bit */ - __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE); - } - - /* Check NAND interrupt Level flag */ - if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL)) - { - /* NAND interrupt callback*/ - HAL_NAND_ITCallback(hnand); - - /* Clear NAND interrupt Level pending bit */ - __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL); - } - - /* Check NAND interrupt Falling edge flag */ - if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE)) - { - /* NAND interrupt callback*/ - HAL_NAND_ITCallback(hnand); - - /* Clear NAND interrupt Falling edge pending bit */ - __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE); - } - - /* Check NAND interrupt FIFO empty flag */ - if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT)) - { - /* NAND interrupt callback*/ - HAL_NAND_ITCallback(hnand); - - /* Clear NAND interrupt FIFO empty pending bit */ - __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT); - } - -} - -/** - * @brief NAND interrupt feature callback - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval None - */ -__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hnand); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_NAND_ITCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions - * @brief Input Output and memory control functions - * - @verbatim - ============================================================================== - ##### NAND Input and Output functions ##### - ============================================================================== - [..] - This section provides functions allowing to use and control the NAND - memory - -@endverbatim - * @{ - */ - -/** - * @brief Read the NAND memory electronic signature - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pNAND_ID: NAND ID structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID) -{ - __IO uint32_t data = 0; - __IO uint32_t data1 = 0; - uint32_t deviceAddress = 0; - - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - deviceAddress = NAND_DEVICE; - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Send Read ID command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - __DSB(); - - /* Read the electronic signature from NAND flash */ - if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) - { - data = *(__IO uint32_t *)deviceAddress; - - /* Return the data read */ - pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); - pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data); - pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data); - pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data); - } - else - { - data = *(__IO uint32_t *)deviceAddress; - data1 = *((__IO uint32_t *)deviceAddress + 4); - - /* Return the data read */ - pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); - pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data); - pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1); - pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1); - } - - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_OK; -} - -/** - * @brief NAND memory reset - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) -{ - uint32_t deviceAddress = 0; - - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - deviceAddress = NAND_DEVICE; - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Send NAND reset command */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF; - - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_OK; - -} - -/** - * @brief Read Page(s) from NAND memory block (8-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer : pointer to destination read buffer - * @param NumPageToRead : number of pages to read from block - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) -{ - __IO uint32_t index = 0; - uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0; - - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - deviceAddress = NAND_DEVICE; - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Page(s) read loop */ - while((NumPageToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize)))) - { - /* update the buffer size */ - size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead); - - /* Send read page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); - __DSB(); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) - { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); - __DSB(); - } - - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; - __DSB(); - - if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8) - { - /* Get Data into Buffer */ - for(; index < size; index++) - { - *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress; - } - } - else - { - /* Get Data into Buffer */ - for(; index < size; index++) - { - *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress; - } - } - - /* Increment read pages number */ - numPagesRead++; - - /* Decrement pages to read */ - NumPageToRead--; - - /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8)); - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_OK; - -} - -/** - * @brief Read Page(s) from NAND memory block (16-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer : pointer to destination read buffer - * @param NumPageToRead : number of pages to read from block - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead) -{ - __IO uint32_t index = 0; - uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0; - - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - deviceAddress = NAND_DEVICE; - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Page(s) read loop */ - while((NumPageToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize)))) - { - /* update the buffer size */ - size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead); - - /* Send read page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); - __DSB(); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) - { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); - __DSB(); - } - - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; - __DSB(); - - /* Get Data into Buffer */ - for(; index < size; index++) - { - *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress; - } - - /* Increment read pages number */ - numPagesRead++; - - /* Decrement pages to read */ - NumPageToRead--; - - /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8)); - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_OK; -} - -/** - * @brief Write Page(s) to NAND memory block (8-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer : pointer to source buffer to write - * @param NumPageToWrite : number of pages to write to block - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite) -{ - __IO uint32_t index = 0; - uint32_t tickstart = 0; - uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0; - - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - deviceAddress = NAND_DEVICE; - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Page(s) write loop */ - while((NumPageToWrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize)))) - { - /* update the buffer size */ - size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten); - - /* Send write page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; - __DSB(); - - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); - __DSB(); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) - { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); - __DSB(); - } - - if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8) - { - /* Write data to memory */ - for(; index < size; index++) - { - *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++; - __DSB(); - } - } - else - { - /* Write data to memory */ - for(; index < size; index++) - { - *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++; - __DSB(); - } - } - - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; - __DSB(); - - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) - { - return HAL_TIMEOUT; - } - } - - /* Increment written pages number */ - numPagesWritten++; - - /* Decrement pages to write */ - NumPageToWrite--; - - /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8)); - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_OK; -} - -/** - * @brief Write Page(s) to NAND memory block (16-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer : pointer to source buffer to write - * @param NumPageToWrite : number of pages to write to block - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite) -{ - __IO uint32_t index = 0; - uint32_t tickstart = 0; - uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0; - - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - deviceAddress = NAND_DEVICE; - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Page(s) write loop */ - while((NumPageToWrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize)))) - { - /* update the buffer size */ - size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten); - - /* Send write page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; - __DSB(); - - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); - __DSB(); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) - { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); - __DSB(); - } - - /* Write data to memory */ - for(; index < size; index++) - { - *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++; - __DSB(); - } - - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; - __DSB(); - - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) - { - return HAL_TIMEOUT; - } - } - - /* Increment written pages number */ - numPagesWritten++; - - /* Decrement pages to write */ - NumPageToWrite--; - - /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8)); - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_OK; -} - -/** - * @brief Read Spare area(s) from NAND memory (8-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer: pointer to source buffer to write - * @param NumSpareAreaToRead: Number of spare area to read - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) -{ - __IO uint32_t index = 0; - uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0; - - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - deviceAddress = NAND_DEVICE; - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Spare area(s) read loop */ - while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize)))) - { - /* update the buffer size */ - size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead); - - /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); - __DSB(); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) - { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); - __DSB(); - } - - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; - __DSB(); - - /* Get Data into Buffer */ - for(; index < size; index++) - { - *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress; - } - - /* Increment read spare areas number */ - numSpareAreaRead++; - - /* Decrement spare areas to read */ - NumSpareAreaToRead--; - - /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize)); - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_OK; -} - -/** - * @brief Read Spare area(s) from NAND memory (16-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer: pointer to source buffer to write - * @param NumSpareAreaToRead: Number of spare area to read - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead) -{ - __IO uint32_t index = 0; - uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0; - - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - deviceAddress = NAND_DEVICE; - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Spare area(s) read loop */ - while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize)))) - { - /* update the buffer size */ - size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead); - - /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); - __DSB(); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) - { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); - __DSB(); - } - - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; - __DSB(); - - /* Get Data into Buffer */ - for(; index < size; index++) - { - *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress; - } - - /* Increment read spare areas number */ - numSpareAreaRead++; - - /* Decrement spare areas to read */ - NumSpareAreaToRead--; - - /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize)); - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_OK; -} - -/** - * @brief Write Spare area(s) to NAND memory (8-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer : pointer to source buffer to write - * @param NumSpareAreaTowrite : number of spare areas to write to block - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) -{ - __IO uint32_t index = 0; - uint32_t tickstart = 0; - uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0; - - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - deviceAddress = NAND_DEVICE; - - /* Update the FMC_NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Spare area(s) write loop */ - while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize)))) - { - /* update the buffer size */ - size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten); - - /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); - __DSB(); - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) - { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); - __DSB(); - } - - /* Write data to memory */ - for(; index < size; index++) - { - *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++; - __DSB(); - } - - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; - __DSB(); - - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) - { - return HAL_TIMEOUT; - } - } - - /* Increment written spare areas number */ - numSpareAreaWritten++; - - /* Decrement spare areas to write */ - NumSpareAreaTowrite--; - - /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize)); - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_OK; -} - -/** - * @brief Write Spare area(s) to NAND memory (16-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer : pointer to source buffer to write - * @param NumSpareAreaTowrite : number of spare areas to write to block - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) -{ - __IO uint32_t index = 0; - uint32_t tickstart = 0; - uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0; - - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - deviceAddress = NAND_DEVICE; - - /* Update the FMC_NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Spare area(s) write loop */ - while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize)))) - { - /* update the buffer size */ - size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten); - - /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); - __DSB(); - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) - { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); - __DSB(); - } - - /* Write data to memory */ - for(; index < size; index++) - { - *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++; - __DSB(); - } - - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; - __DSB(); - - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) - { - return HAL_TIMEOUT; - } - } - - /* Increment written spare areas number */ - numSpareAreaWritten++; - - /* Decrement spare areas to write */ - NumSpareAreaTowrite--; - - /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize)); - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_OK; -} - -/** - * @brief NAND memory Block erase - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) -{ - uint32_t DeviceAddress = 0; - - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - DeviceAddress = NAND_DEVICE; - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Send Erase block command sequence */ - *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0; - __DSB(); - *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - __DSB(); - *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - __DSB(); - *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - __DSB(); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) - { - *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - __DSB(); - } - - *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1; - __DSB(); - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_OK; -} - -/** - * @brief NAND memory read status - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval NAND status - */ -uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) -{ - uint32_t data = 0; - uint32_t DeviceAddress = 0; - - /* Identify the device address */ - DeviceAddress = NAND_DEVICE; - - /* Send Read status operation command */ - *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS; - - /* Read status register data */ - data = *(__IO uint8_t *)DeviceAddress; - - /* Return the status */ - if((data & NAND_ERROR) == NAND_ERROR) - { - return NAND_ERROR; - } - else if((data & NAND_READY) == NAND_READY) - { - return NAND_READY; - } - - return NAND_BUSY; -} - -/** - * @brief Increment the NAND memory address - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress: pointer to NAND address structure - * @retval The new status of the increment address operation. It can be: - * - NAND_VALID_ADDRESS: When the new address is valid address - * - NAND_INVALID_ADDRESS: When the new address is invalid address - */ -uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) -{ - uint32_t status = NAND_VALID_ADDRESS; - - /* Increment page address */ - pAddress->Page++; - - /* Check NAND address is valid */ - if(pAddress->Page == hnand->Info.BlockSize) - { - pAddress->Page = 0; - pAddress->Block++; - - if(pAddress->Block == hnand->Info.ZoneSize) - { - pAddress->Block = 0; - pAddress->Zone++; - - if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr)) - { - status = NAND_INVALID_ADDRESS; - } - } - } - - return (status); -} -/** - * @} - */ - -/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * -@verbatim - ============================================================================== - ##### NAND Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the NAND interface. - -@endverbatim - * @{ - */ - - -/** - * @brief Enables dynamically NAND ECC feature. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand) -{ - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Enable ECC feature */ - FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank); - - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Disables dynamically FMC_NAND ECC feature. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) -{ - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Disable ECC feature */ - FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank); - - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Disables dynamically NAND ECC feature. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param ECCval: pointer to ECC value - * @param Timeout: maximum timeout to wait - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Get NAND ECC value */ - status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout); - - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_READY; - - return status; -} - -/** - * @} - */ - - -/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### NAND State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the NAND controller - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief return the NAND state - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval HAL state - */ -HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) -{ - return hnand->State; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_NAND_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nor.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nor.c deleted file mode 100644 index 682c2a0..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nor.c +++ /dev/null @@ -1,1044 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_nor.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief NOR HAL module driver. - * This file provides a generic firmware to drive NOR memories mounted - * as external device. - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - This driver is a generic layered driver which contains a set of APIs used to - control NOR flash memories. It uses the FMC layer functions to interface - with NOR devices. This driver is used as follows: - - (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() - with control and timing parameters for both normal and extended mode. - - (+) Read NOR flash memory manufacturer code and device IDs using the function - HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef - structure declared by the function caller. - - (+) Access NOR flash memory by read/write data unit operations using the functions - HAL_NOR_Read(), HAL_NOR_Program(). - - (+) Perform NOR flash erase block/chip operations using the functions - HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip(). - - (+) Read the NOR flash CFI (common flash interface) IDs using the function - HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef - structure declared by the function caller. - - (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/ - HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation - - (+) You can monitor the NOR device HAL state by calling the function - HAL_NOR_GetState() - [..] - (@) This driver is a set of generic APIs which handle standard NOR flash operations. - If a NOR flash device contains different operations and/or implementations, - it should be implemented separately. - - *** NOR HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in NOR HAL driver. - - (+) NOR_WRITE : NOR memory write data to specified address - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup NOR NOR - * @brief NOR driver modules - * @{ - */ -#ifdef HAL_NOR_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup NOR_Private_Defines NOR Private Defines - * @{ - */ - -/* Constants to define address to set to write a command */ -#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555 -#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055 -#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA -#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555 -#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555 -#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA -#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555 - -/* Constants to define data to program a command */ -#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0 -#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA -#define NOR_CMD_DATA_SECOND (uint16_t)0x0055 -#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090 -#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0 -#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080 -#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA -#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055 -#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010 -#define NOR_CMD_DATA_CFI (uint16_t)0x0098 - -#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25 -#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29 -#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30 - -/* Mask on NOR STATUS REGISTER */ -#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020 -#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040 - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup NOR_Private_Variables NOR Private Variables - * @{ - */ - -static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B; - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup NOR_Exported_Functions NOR Exported Functions - * @{ - */ - -/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - ============================================================================== - ##### NOR Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to initialize/de-initialize - the NOR memory - -@endverbatim - * @{ - */ - -/** - * @brief Perform the NOR memory Initialization sequence - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param Timing: pointer to NOR control timing structure - * @param ExtTiming: pointer to NOR extended mode timing structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) -{ - /* Check the NOR handle parameter */ - if(hnor == NULL) - { - return HAL_ERROR; - } - - if(hnor->State == HAL_NOR_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hnor->Lock = HAL_UNLOCKED; - /* Initialize the low level hardware (MSP) */ - HAL_NOR_MspInit(hnor); - } - - /* Initialize NOR control Interface */ - FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init)); - - /* Initialize NOR timing Interface */ - FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); - - /* Initialize NOR extended mode timing Interface */ - FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode); - - /* Enable the NORSRAM device */ - __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); - - /* Initialize NOR Memory Data Width*/ - if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8) - { - uwNORMemoryDataWidth = NOR_MEMORY_8B; - } - else - { - uwNORMemoryDataWidth = NOR_MEMORY_16B; - } - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Perform NOR memory De-Initialization sequence - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) -{ - /* De-Initialize the low level hardware (MSP) */ - HAL_NOR_MspDeInit(hnor); - - /* Configure the NOR registers with their reset values */ - FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hnor); - - return HAL_OK; -} - -/** - * @brief NOR MSP Init - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @retval None - */ -__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hnor); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_NOR_MspInit could be implemented in the user file - */ -} - -/** - * @brief NOR MSP DeInit - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @retval None - */ -__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hnor); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_NOR_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief NOR MSP Wait for Ready/Busy signal - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param Timeout: Maximum timeout value - * @retval None - */ -__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hnor); - UNUSED(Timeout); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_NOR_MspWait could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions - * @brief Input Output and memory control functions - * - @verbatim - ============================================================================== - ##### NOR Input and Output functions ##### - ============================================================================== - [..] - This section provides functions allowing to use and control the NOR memory - -@endverbatim - * @{ - */ - -/** - * @brief Read NOR flash IDs - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param pNOR_ID : pointer to NOR ID structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID) -{ - uint32_t deviceaddress = 0; - - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Send read ID command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); - - /* Read the NOR IDs */ - pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); - pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR); - pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR); - pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR); - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; -} - -/** - * @brief Returns the NOR memory to Read mode. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) -{ - uint32_t deviceaddress = 0; - - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET); - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; -} - -/** - * @brief Read data from NOR memory - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param pAddress: pointer to Device address - * @param pData : pointer to read data - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) -{ - uint32_t deviceaddress = 0; - - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Send read data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); - - /* Read the data */ - *pData = *(__IO uint32_t *)(uint32_t)pAddress; - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; -} - -/** - * @brief Program data to NOR memory - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param pAddress: Device address - * @param pData : pointer to the data to write - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) -{ - uint32_t deviceaddress = 0; - - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Send program data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); - - /* Write the data */ - NOR_WRITE(pAddress, *pData); - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; -} - -/** - * @brief Reads a half-word buffer from the NOR memory. - * @param hnor: pointer to the NOR handle - * @param uwAddress: NOR memory internal address to read from. - * @param pData: pointer to the buffer that receives the data read from the - * NOR memory. - * @param uwBufferSize : number of Half word to read. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) -{ - uint32_t deviceaddress = 0; - - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Send read data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); - - /* Read buffer */ - while( uwBufferSize > 0) - { - *pData++ = *(__IO uint16_t *)uwAddress; - uwAddress += 2; - uwBufferSize--; - } - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; -} - -/** - * @brief Writes a half-word buffer to the NOR memory. This function must be used - only with S29GL128P NOR memory. - * @param hnor: pointer to the NOR handle - * @param uwAddress: NOR memory internal start write address - * @param pData: pointer to source data buffer. - * @param uwBufferSize: Size of the buffer to write - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) -{ - uint16_t * p_currentaddress = (uint16_t *)NULL; - uint16_t * p_endaddress = (uint16_t *)NULL; - uint32_t lastloadedaddress = 0, deviceaddress = 0; - - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Initialize variables */ - p_currentaddress = (uint16_t*)((uint32_t)(uwAddress)); - p_endaddress = p_currentaddress + (uwBufferSize-1); - lastloadedaddress = (uint32_t)(uwAddress); - - /* Issue unlock command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - - /* Write Buffer Load Command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uwBufferSize - 1)); - - /* Load Data into NOR Buffer */ - while(p_currentaddress <= p_endaddress) - { - /* Store last loaded address & data value (for polling) */ - lastloadedaddress = (uint32_t)p_currentaddress; - - NOR_WRITE(p_currentaddress, *pData++); - - p_currentaddress ++; - } - - NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; - -} - -/** - * @brief Erase the specified block of the NOR memory - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param BlockAddress : Block to erase address - * @param Address: Device address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) -{ - uint32_t deviceaddress = 0; - - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Send block erase command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); - - /* Check the NOR memory status and update the controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; - -} - -/** - * @brief Erase the entire NOR chip. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param Address : Device address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) -{ - uint32_t deviceaddress = 0; - - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Send NOR chip erase command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); - - /* Check the NOR memory status and update the controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; -} - -/** - * @brief Read NOR flash CFI IDs - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param pNOR_CFI : pointer to NOR CFI IDs structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI) -{ - uint32_t deviceaddress = 0; - - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Send read CFI query command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); - - /* read the NOR CFI information */ - pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS); - pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS); - pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS); - pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS); - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions - * @brief management functions - * -@verbatim - ============================================================================== - ##### NOR Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the NOR interface. - -@endverbatim - * @{ - */ - -/** - * @brief Enables dynamically NOR write operation. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) -{ - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Enable write operation */ - FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; -} - -/** - * @brief Disables dynamically NOR write operation. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) -{ - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Update the SRAM controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Disable write operation */ - FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_PROTECTED; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup NOR_Exported_Functions_Group4 NOR State functions - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### NOR State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the NOR controller - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief return the NOR controller state - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @retval NOR controller state - */ -HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) -{ - return hnor->State; -} - -/** - * @brief Returns the NOR operation status. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param Address: Device address - * @param Timeout: NOR programming Timeout - * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR - * or HAL_NOR_STATUS_TIMEOUT - */ -HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) -{ - HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING; - uint16_t tmpSR1 = 0, tmpSR2 = 0; - uint32_t tickstart = 0; - - /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ - HAL_NOR_MspWait(hnor, Timeout); - - /* Get the NOR memory operation status -------------------------------------*/ - - /* Get tick */ - tickstart = HAL_GetTick(); - while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - status = HAL_NOR_STATUS_TIMEOUT; - } - } - - /* Read NOR status register (DQ6 and DQ5) */ - tmpSR1 = *(__IO uint16_t *)Address; - tmpSR2 = *(__IO uint16_t *)Address; - - /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ - if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) - { - return HAL_NOR_STATUS_SUCCESS ; - } - - if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) - { - status = HAL_NOR_STATUS_ONGOING; - } - - tmpSR1 = *(__IO uint16_t *)Address; - tmpSR2 = *(__IO uint16_t *)Address; - - /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ - if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) - { - return HAL_NOR_STATUS_SUCCESS; - } - if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) - { - return HAL_NOR_STATUS_ERROR; - } - } - - /* Return the operation status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ -#endif /* HAL_NOR_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c deleted file mode 100644 index fc54bc3..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c +++ /dev/null @@ -1,1311 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_pcd.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief PCD HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The PCD HAL driver can be used as follows: - - (#) Declare a PCD_HandleTypeDef handle structure, for example: - PCD_HandleTypeDef hpcd; - - (#) Fill parameters of Init structure in HCD handle - - (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) - - (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: - (##) Enable the PCD/USB Low Level interface clock using - (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); - (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) - - (##) Initialize the related GPIO clocks - (##) Configure PCD pin-out - (##) Configure PCD NVIC interrupt - - (#)Associate the Upper USB device stack to the HAL PCD Driver: - (##) hpcd.pData = pdev; - - (#)Enable PCD transmission and reception: - (##) HAL_PCD_Start(); - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup PCD PCD - * @brief PCD HAL module driver - * @{ - */ - -#ifdef HAL_PCD_MODULE_ENABLED - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup PCD_Private_Macros PCD Private Macros - * @{ - */ -#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b)) -#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b)) -/** - * @} - */ - -/* Private functions prototypes ----------------------------------------------*/ -/** @defgroup PCD_Private_Functions PCD Private Functions - * @{ - */ -static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup PCD_Exported_Functions PCD Exported Functions - * @{ - */ - -/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the PCD according to the specified - * parameters in the PCD_InitTypeDef and create the associated handle. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) -{ - uint32_t i = 0; - - /* Check the PCD handle allocation */ - if(hpcd == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); - - hpcd->State = HAL_PCD_STATE_BUSY; - - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - HAL_PCD_MspInit(hpcd); - - /* Disable the Interrupts */ - __HAL_PCD_DISABLE(hpcd); - - /*Init the Core (common init.) */ - USB_CoreInit(hpcd->Instance, hpcd->Init); - - /* Force Device Mode*/ - USB_SetCurrentMode(hpcd->Instance , USB_OTG_DEVICE_MODE); - - /* Init endpoints structures */ - for (i = 0; i < 15 ; i++) - { - /* Init ep structure */ - hpcd->IN_ep[i].is_in = 1; - hpcd->IN_ep[i].num = i; - hpcd->IN_ep[i].tx_fifo_num = i; - /* Control until ep is activated */ - hpcd->IN_ep[i].type = EP_TYPE_CTRL; - hpcd->IN_ep[i].maxpacket = 0; - hpcd->IN_ep[i].xfer_buff = 0; - hpcd->IN_ep[i].xfer_len = 0; - } - - for (i = 0; i < 15 ; i++) - { - hpcd->OUT_ep[i].is_in = 0; - hpcd->OUT_ep[i].num = i; - hpcd->IN_ep[i].tx_fifo_num = i; - /* Control until ep is activated */ - hpcd->OUT_ep[i].type = EP_TYPE_CTRL; - hpcd->OUT_ep[i].maxpacket = 0; - hpcd->OUT_ep[i].xfer_buff = 0; - hpcd->OUT_ep[i].xfer_len = 0; - - hpcd->Instance->DIEPTXF[i] = 0; - } - - /* Init Device */ - USB_DevInit(hpcd->Instance, hpcd->Init); - - hpcd->State= HAL_PCD_STATE_READY; - - /* Activate LPM */ - if (hpcd->Init.lpm_enable == 1) - { - HAL_PCDEx_ActivateLPM(hpcd); - } - - USB_DevDisconnect (hpcd->Instance); - return HAL_OK; -} - -/** - * @brief DeInitializes the PCD peripheral. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) -{ - /* Check the PCD handle allocation */ - if(hpcd == NULL) - { - return HAL_ERROR; - } - - hpcd->State = HAL_PCD_STATE_BUSY; - - /* Stop Device */ - HAL_PCD_Stop(hpcd); - - /* DeInit the low level hardware */ - HAL_PCD_MspDeInit(hpcd); - - hpcd->State = HAL_PCD_STATE_RESET; - - return HAL_OK; -} - -/** - * @brief Initializes the PCD MSP. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes PCD MSP. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the PCD data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Start The USB OTG Device. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - USB_DevConnect (hpcd->Instance); - __HAL_PCD_ENABLE(hpcd); - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - -/** - * @brief Stop The USB OTG Device. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - __HAL_PCD_DISABLE(hpcd); - USB_StopDevice(hpcd->Instance); - USB_DevDisconnect (hpcd->Instance); - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - -/** - * @brief Handle PCD interrupt request. - * @param hpcd: PCD handle - * @retval HAL status - */ -void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t i = 0, ep_intr = 0, epint = 0, epnum = 0; - uint32_t fifoemptymsk = 0, temp = 0; - USB_OTG_EPTypeDef *ep = NULL; - uint32_t hclk = 200000000; - - /* ensure that we are in device mode */ - if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) - { - /* avoid spurious interrupt */ - if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) - { - return; - } - - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) - { - /* incorrect mode, acknowledge the interrupt */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); - } - - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) - { - epnum = 0; - - /* Read in the device interrupt bits */ - ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); - - while ( ep_intr ) - { - if (ep_intr & 0x1) - { - epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum); - - if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); - - if(hpcd->Init.dma_enable == 1) - { - hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); - hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket; - } - - HAL_PCD_DataOutStageCallback(hpcd, epnum); - if(hpcd->Init.dma_enable == 1) - { - if((epnum == 0) && (hpcd->OUT_ep[epnum].xfer_len == 0)) - { - /* this is ZLP, so prepare EP0 for next setup */ - USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup); - } - } - } - - if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) - { - /* Inform the upper layer that a setup packet is available */ - HAL_PCD_SetupStageCallback(hpcd); - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); - } - - if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); - } - /* Clear Status Phase Received interrupt */ - if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); - } - } - epnum++; - ep_intr >>= 1; - } - } - - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) - { - /* Read in the device interrupt bits */ - ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); - - epnum = 0; - - while ( ep_intr ) - { - if (ep_intr & 0x1) /* In ITR */ - { - epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum); - - if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) - { - fifoemptymsk = 0x1 << epnum; - USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; - - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); - - if (hpcd->Init.dma_enable == 1) - { - hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; - } - - HAL_PCD_DataInStageCallback(hpcd, epnum); - - if (hpcd->Init.dma_enable == 1) - { - /* this is ZLP, so prepare EP0 for next setup */ - if((epnum == 0) && (hpcd->IN_ep[epnum].xfer_len == 0)) - { - /* prepare to rx more setup packets */ - USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup); - } - } - } - if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) - { - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); - } - if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) - { - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); - } - if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) - { - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); - } - if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) - { - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); - } - if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) - { - PCD_WriteEmptyTxFifo(hpcd , epnum); - } - } - epnum++; - ep_intr >>= 1; - } - } - - /* Handle Resume Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) - { - /* Clear the Remote Wake-up Signaling */ - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; - - if(hpcd->LPM_State == LPM_L1) - { - hpcd->LPM_State = LPM_L0; - HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); - } - else - { - HAL_PCD_ResumeCallback(hpcd); - } - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); - } - - /* Handle Suspend Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) - { - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) - { - - HAL_PCD_SuspendCallback(hpcd); - } - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); - } - - /* Handle LPM Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); - if( hpcd->LPM_State == LPM_L0) - { - hpcd->LPM_State = LPM_L1; - hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ; - HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); - } - else - { - HAL_PCD_SuspendCallback(hpcd); - } - } - - /* Handle Reset Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) - { - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; - USB_FlushTxFifo(hpcd->Instance , 0 ); - - for (i = 0; i < hpcd->Init.dev_endpoints ; i++) - { - USBx_INEP(i)->DIEPINT = 0xFF; - USBx_OUTEP(i)->DOEPINT = 0xFF; - } - USBx_DEVICE->DAINT = 0xFFFFFFFF; - USBx_DEVICE->DAINTMSK |= 0x10001; - - if(hpcd->Init.use_dedicated_ep1) - { - USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); - USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); - } - else - { - USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM); - USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); - } - - /* Set Default Address to 0 */ - USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; - - /* setup EP0 to receive SETUP packets */ - USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); - } - - /* Handle Enumeration done Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) - { - USB_ActivateSetup(hpcd->Instance); - hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; - - if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH) - { - hpcd->Init.speed = USB_OTG_SPEED_HIGH; - hpcd->Init.ep0_mps = USB_OTG_HS_MAX_PACKET_SIZE ; - hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT); - } - else - { - hpcd->Init.speed = USB_OTG_SPEED_FULL; - hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ; - - /* The USBTRD is configured according to the tables below, depending on AHB frequency - used by application. In the low AHB frequency range it is used to stretch enough the USB response - time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access - latency to the Data FIFO */ - - /* Get hclk frequency value */ - hclk = HAL_RCC_GetHCLKFreq(); - - if((hclk >= 14200000)&&(hclk < 15000000)) - { - /* hclk Clock Range between 14.2-15 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xF << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 15000000)&&(hclk < 16000000)) - { - /* hclk Clock Range between 15-16 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xE << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 16000000)&&(hclk < 17200000)) - { - /* hclk Clock Range between 16-17.2 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xD << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 17200000)&&(hclk < 18500000)) - { - /* hclk Clock Range between 17.2-18.5 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xC << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 18500000)&&(hclk < 20000000)) - { - /* hclk Clock Range between 18.5-20 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xB << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 20000000)&&(hclk < 21800000)) - { - /* hclk Clock Range between 20-21.8 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xA << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 21800000)&&(hclk < 24000000)) - { - /* hclk Clock Range between 21.8-24 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x9 << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 24000000)&&(hclk < 27700000)) - { - /* hclk Clock Range between 24-27.7 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x8 << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 27700000)&&(hclk < 32000000)) - { - /* hclk Clock Range between 27.7-32 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x7 << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else /* if(hclk >= 32000000) */ - { - /* hclk Clock Range between 32-200 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x6 << 10) & USB_OTG_GUSBCFG_TRDT); - } - } - - HAL_PCD_ResetCallback(hpcd); - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); - } - - /* Handle RxQLevel Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) - { - USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - temp = USBx->GRXSTSP; - ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; - - if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) - { - if((temp & USB_OTG_GRXSTSP_BCNT) != 0) - { - USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4); - ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - } - } - else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) - { - USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8); - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - } - USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - } - - /* Handle SOF Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) - { - HAL_PCD_SOFCallback(hpcd); - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); - } - - /* Handle Incomplete ISO IN Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) - { - HAL_PCD_ISOINIncompleteCallback(hpcd, epnum); - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); - } - - /* Handle Incomplete ISO OUT Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) - { - HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum); - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); - } - - /* Handle Connection event Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) - { - HAL_PCD_ConnectCallback(hpcd); - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); - } - - /* Handle Disconnection event Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) - { - temp = hpcd->Instance->GOTGINT; - - if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) - { - HAL_PCD_DisconnectCallback(hpcd); - } - hpcd->Instance->GOTGINT |= temp; - } - } -} - -/** - * @brief Data OUT stage callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval None - */ - __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_DataOutStageCallback could be implemented in the user file - */ -} - -/** - * @brief Data IN stage callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval None - */ - __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_DataInStageCallback could be implemented in the user file - */ -} -/** - * @brief Setup stage callback. - * @param hpcd: PCD handle - * @retval None - */ - __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_SetupStageCallback could be implemented in the user file - */ -} - -/** - * @brief USB Start Of Frame callback. - * @param hpcd: PCD handle - * @retval None - */ - __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_SOFCallback could be implemented in the user file - */ -} - -/** - * @brief USB Reset callback. - * @param hpcd: PCD handle - * @retval None - */ - __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_ResetCallback could be implemented in the user file - */ -} - -/** - * @brief Suspend event callback. - * @param hpcd: PCD handle - * @retval None - */ - __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_SuspendCallback could be implemented in the user file - */ -} - -/** - * @brief Resume event callback. - * @param hpcd: PCD handle - * @retval None - */ - __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_ResumeCallback could be implemented in the user file - */ -} - -/** - * @brief Incomplete ISO OUT callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval None - */ - __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file - */ -} - -/** - * @brief Incomplete ISO IN callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval None - */ - __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file - */ -} - -/** - * @brief Connection event callback. - * @param hpcd: PCD handle - * @retval None - */ - __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_ConnectCallback could be implemented in the user file - */ -} - -/** - * @brief Disconnection event callback. - * @param hpcd: PCD handle - * @retval None - */ - __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_DisconnectCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the PCD data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Connect the USB device. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - USB_DevConnect(hpcd->Instance); - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - -/** - * @brief Disconnect the USB device. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - USB_DevDisconnect(hpcd->Instance); - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - -/** - * @brief Set the USB Device address. - * @param hpcd: PCD handle - * @param address: new device address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) -{ - __HAL_LOCK(hpcd); - USB_SetDevAddress(hpcd->Instance, address); - __HAL_UNLOCK(hpcd); - return HAL_OK; -} -/** - * @brief Open and configure an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param ep_mps: endpoint max packet size - * @param ep_type: endpoint type - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) -{ - HAL_StatusTypeDef ret = HAL_OK; - USB_OTG_EPTypeDef *ep; - - if ((ep_addr & 0x80) == 0x80) - { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; - } - ep->num = ep_addr & 0x7F; - - ep->is_in = (0x80 & ep_addr) != 0; - ep->maxpacket = ep_mps; - ep->type = ep_type; - if (ep->is_in) - { - /* Assign a Tx FIFO */ - ep->tx_fifo_num = ep->num; - } - /* Set initial data PID. */ - if (ep_type == EP_TYPE_BULK ) - { - ep->data_pid_start = 0; - } - - __HAL_LOCK(hpcd); - USB_ActivateEndpoint(hpcd->Instance , ep); - __HAL_UNLOCK(hpcd); - return ret; -} - - -/** - * @brief Deactivate an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - USB_OTG_EPTypeDef *ep; - - if ((ep_addr & 0x80) == 0x80) - { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; - } - ep->num = ep_addr & 0x7F; - - ep->is_in = (0x80 & ep_addr) != 0; - - __HAL_LOCK(hpcd); - USB_DeactivateEndpoint(hpcd->Instance , ep); - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - - -/** - * @brief Receive an amount of data. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the reception buffer - * @param len: amount of data to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) -{ - USB_OTG_EPTypeDef *ep; - - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; - - /*setup and start the Xfer */ - ep->xfer_buff = pBuf; - ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 0; - ep->num = ep_addr & 0x7F; - - if (hpcd->Init.dma_enable == 1) - { - ep->dma_addr = (uint32_t)pBuf; - } - - __HAL_LOCK(hpcd); - - if ((ep_addr & 0x7F) == 0 ) - { - USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable); - } - else - { - USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable); - } - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Get Received Data Size. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval Data Size - */ -uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count; -} -/** - * @brief Send an amount of data. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the transmission buffer - * @param len: amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) -{ - USB_OTG_EPTypeDef *ep; - - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - - /*setup and start the Xfer */ - ep->xfer_buff = pBuf; - ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 1; - ep->num = ep_addr & 0x7F; - - if (hpcd->Init.dma_enable == 1) - { - ep->dma_addr = (uint32_t)pBuf; - } - - __HAL_LOCK(hpcd); - - if ((ep_addr & 0x7F) == 0 ) - { - USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable); - } - else - { - USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable); - } - - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Set a STALL condition over an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - USB_OTG_EPTypeDef *ep; - - if ((0x80 & ep_addr) == 0x80) - { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr]; - } - - ep->is_stall = 1; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); - - - __HAL_LOCK(hpcd); - USB_EPSetStall(hpcd->Instance , ep); - if((ep_addr & 0x7F) == 0) - { - USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); - } - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Clear a STALL condition over in an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - USB_OTG_EPTypeDef *ep; - - if ((0x80 & ep_addr) == 0x80) - { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr]; - } - - ep->is_stall = 0; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); - - __HAL_LOCK(hpcd); - USB_EPClearStall(hpcd->Instance , ep); - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Flush an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - __HAL_LOCK(hpcd); - - if ((ep_addr & 0x80) == 0x80) - { - USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F); - } - else - { - USB_FlushRxFifo(hpcd->Instance); - } - - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Activate remote wakeup signalling. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) - { - /* Activate Remote wakeup signaling */ - USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; - } - return HAL_OK; -} - -/** - * @brief De-activate remote wakeup signalling. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - /* De-activate Remote wakeup signaling */ - USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); - return HAL_OK; -} -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the PCD handle state. - * @param hpcd: PCD handle - * @retval HAL state - */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) -{ - return hpcd->State; -} -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup PCD_Private_Functions - * @{ - */ - -/** - * @brief Check FIFO for the next packet to be loaded. - * @param hpcd: PCD handle - * @param epnum : endpoint number - * @retval HAL status - */ -static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - USB_OTG_EPTypeDef *ep; - int32_t len = 0; - uint32_t len32b; - uint32_t fifoemptymsk = 0; - - ep = &hpcd->IN_ep[epnum]; - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->maxpacket) - { - len = ep->maxpacket; - } - - - len32b = (len + 3) / 4; - - while ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b && - ep->xfer_count < ep->xfer_len && - ep->xfer_len != 0) - { - /* Write the FIFO */ - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->maxpacket) - { - len = ep->maxpacket; - } - len32b = (len + 3) / 4; - - USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable); - - ep->xfer_buff += len; - ep->xfer_count += len; - } - - if(len <= 0) - { - fifoemptymsk = 0x1 << epnum; - USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; - - } - - return HAL_OK; -} - -/** - * @} - */ - -#endif /* HAL_PCD_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c deleted file mode 100644 index 820a1d4..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c +++ /dev/null @@ -1,203 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_pcd_ex.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief PCD HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Extended features functions - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup PCDEx PCDEx - * @brief PCD Extended HAL module driver - * @{ - */ -#ifdef HAL_PCD_MODULE_ENABLED - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions - * @{ - */ - -/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions - * @brief PCDEx control functions - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Update FIFO configuration - -@endverbatim - * @{ - */ - -/** - * @brief Set Tx FIFO - * @param hpcd: PCD handle - * @param fifo: The number of Tx fifo - * @param size: Fifo size - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) -{ - uint8_t i = 0; - uint32_t Tx_Offset = 0; - - /* TXn min size = 16 words. (n : Transmit FIFO index) - When a TxFIFO is not used, the Configuration should be as follows: - case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) - --> Txm can use the space allocated for Txn. - case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) - --> Txn should be configured with the minimum space of 16 words - The FIFO is used optimally when used TxFIFOs are allocated in the top - of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. - When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ - - Tx_Offset = hpcd->Instance->GRXFSIZ; - - if(fifo == 0) - { - hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16) | Tx_Offset); - } - else - { - Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; - for (i = 0; i < (fifo - 1); i++) - { - Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); - } - - /* Multiply Tx_Size by 2 to get higher performance */ - hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16) | Tx_Offset); - } - - return HAL_OK; -} - -/** - * @brief Set Rx FIFO - * @param hpcd: PCD handle - * @param size: Size of Rx fifo - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) -{ - hpcd->Instance->GRXFSIZ = size; - - return HAL_OK; -} - -/** - * @brief Activate LPM Feature - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = ENABLE; - hpcd->LPM_State = LPM_L0; - USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; - USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); - - return HAL_OK; -} - -/** - * @brief DeActivate LPM feature. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = DISABLE; - USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM; - USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); - - return HAL_OK; -} - -/** - * @brief Send LPM message to user layer callback. - * @param hpcd: PCD handle - * @param msg: LPM message - * @retval HAL status - */ -__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(msg); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCDEx_LPM_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_PCD_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c deleted file mode 100644 index 45a2643..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c +++ /dev/null @@ -1,609 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_pwr.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief PWR HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup PWR PWR - * @brief PWR HAL module driver - * @{ - */ - -#ifdef HAL_PWR_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup PWR_Private_Constants - * @{ - */ - -/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask - * @{ - */ -#define PVD_MODE_IT ((uint32_t)0x00010000U) -#define PVD_MODE_EVT ((uint32_t)0x00020000U) -#define PVD_RISING_EDGE ((uint32_t)0x00000001U) -#define PVD_FALLING_EDGE ((uint32_t)0x00000002U) -/** - * @} - */ - -/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask - * @{ - */ -#define PWR_EWUP_MASK ((uint32_t)0x00003F00) -/** - * @} - */ - -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted - write accesses. - To enable access to the RTC Domain and RTC registers, proceed as follows: - (+) Enable the Power Controller (PWR) APB1 interface clock using the - __HAL_RCC_PWR_CLK_ENABLE() macro. - (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the HAL PWR peripheral registers to their default reset values. - * @retval None - */ -void HAL_PWR_DeInit(void) -{ - __HAL_RCC_PWR_FORCE_RESET(); - __HAL_RCC_PWR_RELEASE_RESET(); -} - -/** - * @brief Enables access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @retval None - */ -void HAL_PWR_EnableBkUpAccess(void) -{ - /* Enable access to RTC and backup registers */ - SET_BIT(PWR->CR1, PWR_CR1_DBP); -} - -/** - * @brief Disables access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @retval None - */ -void HAL_PWR_DisableBkUpAccess(void) -{ - /* Disable access to RTC and backup registers */ - CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); -} - -/** - * @} - */ - -/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @brief Low Power modes configuration functions - * -@verbatim - - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - - *** PVD configuration *** - ========================= - [..] - (+) The PVD is used to monitor the VDD power supply by comparing it to a - threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). - (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower - than the PVD threshold. This event is internally connected to the EXTI - line16 and can generate an interrupt if enabled. This is done through - __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. - (+) The PVD is stopped in Standby mode. - - *** Wake-up pin configuration *** - ================================ - [..] - (+) Wake-up pin is used to wake up the system from Standby mode. This pin is - forced in input pull-down configuration and is active on rising edges. - (+) There are to 6 Wake-up pin in the STM32F7 devices family - - *** Low Power modes configuration *** - ===================================== - [..] - The devices feature 3 low-power modes: - (+) Sleep mode: Cortex-M7 core stopped, peripherals kept running. - (+) Stop mode: all clocks are stopped, regulator running, regulator - in low power mode - (+) Standby mode: 1.2V domain powered off. - - *** Sleep mode *** - ================== - [..] - (+) Entry: - The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI) - functions with - (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - - -@@- The Regulator parameter is not used for the STM32F7 family - and is kept as parameter just to maintain compatibility with the - lower power families (STM32L). - (+) Exit: - Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) can wake up the device from Sleep mode. - - *** Stop mode *** - ================= - [..] - In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, - and the HSE RC oscillators are disabled. Internal SRAM and register contents - are preserved. - The voltage regulator can be configured either in normal or low-power mode. - To minimize the consumption In Stop mode, FLASH can be powered off before - entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function. - It can be switched on again by software after exiting the Stop mode using - the HAL_PWREx_DisableFlashPowerDown() function. - - (+) Entry: - The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) - function with: - (++) Main regulator ON. - (++) Low Power regulator ON. - (+) Exit: - Any EXTI Line (Internal or External) configured in Interrupt/Event mode. - - *** Standby mode *** - ==================== - [..] - (+) - The Standby mode allows to achieve the lowest power consumption. It is based - on the Cortex-M7 deep sleep mode, with the voltage regulator disabled. - The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and - the HSE oscillator are also switched off. SRAM and register contents are lost - except for the RTC registers, RTC backup registers, backup SRAM and Standby - circuitry. - - The voltage regulator is OFF. - - (++) Entry: - (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. - (++) Exit: - (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC - wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset. - - *** Auto-wakeup (AWU) from low-power mode *** - ============================================= - [..] - - (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC - Wakeup event, a tamper event or a time-stamp event, without depending on - an external interrupt (Auto-wakeup mode). - - (+) RTC auto-wakeup (AWU) from the Stop and Standby modes - - (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to - configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. - - (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it - is necessary to configure the RTC to detect the tamper or time stamp event using the - HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. - - (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to - configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration - * information for the PVD. - * @note Refer to the electrical characteristics of your device datasheet for - * more details about the voltage threshold corresponding to each - * detection level. - * @retval None - */ -void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) -{ - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); - assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); - - /* Set PLS[7:5] bits according to PVDLevel value */ - MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); - - /* Clear any previous config. Keep it clear if no event or IT mode is selected */ - __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); - __HAL_PWR_PVD_EXTI_DISABLE_IT(); - __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); - __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); - - /* Configure interrupt mode */ - if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) - { - __HAL_PWR_PVD_EXTI_ENABLE_IT(); - } - - /* Configure event mode */ - if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) - { - __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); - } - - /* Configure the edge */ - if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) - { - __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); - } - - if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) - { - __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); - } -} - -/** - * @brief Enables the Power Voltage Detector(PVD). - * @retval None - */ -void HAL_PWR_EnablePVD(void) -{ - /* Enable the power voltage detector */ - SET_BIT(PWR->CR1, PWR_CR1_PVDE); -} - -/** - * @brief Disables the Power Voltage Detector(PVD). - * @retval None - */ -void HAL_PWR_DisablePVD(void) -{ - /* Disable the power voltage detector */ - CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE); -} - -/** - * @brief Enable the WakeUp PINx functionality. - * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable. - * This parameter can be one of the following legacy values, which sets the default polarity: - * detection on high level (rising edge): - * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6 - * or one of the following value where the user can explicitly states the enabled pin and - * the chosen polarity - * @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW - * @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW - * @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW - * @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW - * @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW - * @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW - * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. - * @retval None - */ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) -{ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); - - /* Enable wake-up pin */ - SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity)); - - /* Specifies the Wake-Up pin polarity for the event detection - (rising or falling edge) */ - MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06)); -} - -/** - * @brief Disables the WakeUp PINx functionality. - * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. - * This parameter can be one of the following values: - * @arg PWR_WAKEUP_PIN1 - * @arg PWR_WAKEUP_PIN2 - * @arg PWR_WAKEUP_PIN3 - * @arg PWR_WAKEUP_PIN4 - * @arg PWR_WAKEUP_PIN5 - * @arg PWR_WAKEUP_PIN6 - * @retval None - */ -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) -{ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - - CLEAR_BIT(PWR->CSR2, WakeUpPinx); -} - -/** - * @brief Enters Sleep mode. - * - * @note In Sleep mode, all I/O pins keep the same state as in Run mode. - * - * @note In Sleep mode, the systick is stopped to avoid exit from this mode with - * systick interrupt when used as time base for Timeout - * - * @param Regulator: Specifies the regulator state in SLEEP mode. - * This parameter can be one of the following values: - * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON - * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON - * @note This parameter is not used for the STM32F7 family and is kept as parameter - * just to maintain compatibility with the lower power families. - * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - * @retval None - */ -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); - - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select SLEEP mode entry -------------------------------------------------*/ - if(SLEEPEntry == PWR_SLEEPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } -} - -/** - * @brief Enters Stop mode. - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * @param Regulator: Specifies the regulator state in Stop mode. - * This parameter can be one of the following values: - * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON - * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON - * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction - * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction - * @retval None - */ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - - /* Select the regulator state in Stop mode ---------------------------------*/ - tmpreg = PWR->CR1; - /* Clear PDDS and LPDS bits */ - tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS); - - /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */ - tmpreg |= Regulator; - - /* Store the new value */ - PWR->CR1 = tmpreg; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Select Stop mode entry --------------------------------------------------*/ - if(STOPEntry == PWR_STOPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/** - * @brief Enters Standby mode. - * @note In Standby mode, all I/O pins are high impedance except for: - * - Reset pad (still available) - * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC - * Alarm out, or RTC clock calibration out. - * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. - * - WKUP pins if enabled. - * @retval None - */ -void HAL_PWR_EnterSTANDBYMode(void) -{ - /* Select Standby mode */ - PWR->CR1 |= PWR_CR1_PDDS; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @brief This function handles the PWR PVD interrupt request. - * @note This API should be called under the PVD_IRQHandler(). - * @retval None - */ -void HAL_PWR_PVD_IRQHandler(void) -{ - /* Check PWR Exti flag */ - if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) - { - /* PWR PVD interrupt user callback */ - HAL_PWR_PVDCallback(); - - /* Clear PWR Exti pending bit */ - __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); - } -} - -/** - * @brief PWR PVD interrupt callback - * @retval None - */ -__weak void HAL_PWR_PVDCallback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PWR_PVDCallback could be implemented in the user file - */ -} - -/** - * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. - * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. - * Setting this bit is useful when the processor is expected to run only on - * interruptions handling. - * @retval None - */ -void HAL_PWR_EnableSleepOnExit(void) -{ - /* Set SLEEPONEXIT bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - -/** - * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. - * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. - * @retval None - */ -void HAL_PWR_DisableSleepOnExit(void) -{ - /* Clear SLEEPONEXIT bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - -/** - * @brief Enables CORTEX M4 SEVONPEND bit. - * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. - * @retval None - */ -void HAL_PWR_EnableSEVOnPend(void) -{ - /* Set SEVONPEND bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @brief Disables CORTEX M4 SEVONPEND bit. - * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. - * @retval None - */ -void HAL_PWR_DisableSEVOnPend(void) -{ - /* Clear SEVONPEND bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_PWR_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c deleted file mode 100644 index cb4e9e8..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c +++ /dev/null @@ -1,572 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_pwr_ex.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Extended PWR HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of PWR extension peripheral: - * + Peripheral Extended features functions - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup PWREx PWREx - * @brief PWR HAL module driver - * @{ - */ - -#ifdef HAL_PWR_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup PWREx_Private_Constants - * @{ - */ -#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000 -#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000 -#define PWR_BKPREG_TIMEOUT_VALUE 1000 -#define PWR_VOSRDY_TIMEOUT_VALUE 1000 -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @defgroup PWREx_Exported_Functions PWREx Exported Functions - * @{ - */ - -/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions - * @brief Peripheral Extended features functions - * -@verbatim - - =============================================================================== - ##### Peripheral extended features functions ##### - =============================================================================== - - *** Main and Backup Regulators configuration *** - ================================================ - [..] - (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from - the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is - retained even in Standby or VBAT mode when the low power backup regulator - is enabled. It can be considered as an internal EEPROM when VBAT is - always present. You can use the HAL_PWREx_EnableBkUpReg() function to - enable the low power backup regulator. - - (+) When the backup domain is supplied by VDD (analog switch connected to VDD) - the backup SRAM is powered from VDD which replaces the VBAT power supply to - save battery life. - - (+) The backup SRAM is not mass erased by a tamper event. It is read - protected to prevent confidential data, such as cryptographic private - key, from being accessed. The backup SRAM can be erased only through - the Flash interface when a protection level change from level 1 to - level 0 is requested. - -@- Refer to the description of Read protection (RDP) in the Flash - programming manual. - - (+) The main internal regulator can be configured to have a tradeoff between - performance and power consumption when the device does not operate at - the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() - macro which configure VOS bit in PWR_CR register - - Refer to the product datasheets for more details. - - *** FLASH Power Down configuration **** - ======================================= - [..] - (+) By setting the FPDS bit in the PWR_CR register by using the - HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power - down mode when the device enters Stop mode. When the Flash memory - is in power down mode, an additional startup delay is incurred when - waking up from Stop mode. - - *** Over-Drive and Under-Drive configuration **** - ================================================= - [..] - (+) In Run mode: the main regulator has 2 operating modes available: - (++) Normal mode: The CPU and core logic operate at maximum frequency at a given - voltage scaling (scale 1, scale 2 or scale 3) - (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a - higher frequency than the normal mode for a given voltage scaling (scale 1, - scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and - disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow - the sequence described in Reference manual. - - (+) In Stop mode: the main regulator or low power regulator supplies a low power - voltage to the 1.2V domain, thus preserving the content of registers - and internal SRAM. 2 operating modes are available: - (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only - available when the main regulator or the low power regulator is used in Scale 3 or - low voltage mode. - (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only - available when the main regulator or the low power regulator is in low voltage mode. - -@endverbatim - * @{ - */ - -/** - * @brief Enables the Backup Regulator. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void) -{ - uint32_t tickstart = 0; - - /* Enable Backup regulator */ - PWR->CSR1 |= PWR_CSR1_BRE; - - /* Workaround for the following hardware bug: */ - /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */ - PWR->CSR1 |= PWR_CSR1_EIWUP; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till Backup regulator ready flag is set */ - while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET) - { - if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief Disables the Backup Regulator. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void) -{ - uint32_t tickstart = 0; - - /* Disable Backup regulator */ - PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE); - - /* Workaround for the following hardware bug: */ - /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */ - PWR->CSR1 |= PWR_CSR1_EIWUP; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till Backup regulator ready flag is set */ - while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET) - { - if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief Enables the Flash Power Down in Stop mode. - * @retval None - */ -void HAL_PWREx_EnableFlashPowerDown(void) -{ - /* Enable the Flash Power Down */ - PWR->CR1 |= PWR_CR1_FPDS; -} - -/** - * @brief Disables the Flash Power Down in Stop mode. - * @retval None - */ -void HAL_PWREx_DisableFlashPowerDown(void) -{ - /* Disable the Flash Power Down */ - PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS); -} - -/** - * @brief Enables Main Regulator low voltage mode. - * @retval None - */ -void HAL_PWREx_EnableMainRegulatorLowVoltage(void) -{ - /* Enable Main regulator low voltage */ - PWR->CR1 |= PWR_CR1_MRUDS; -} - -/** - * @brief Disables Main Regulator low voltage mode. - * @retval None - */ -void HAL_PWREx_DisableMainRegulatorLowVoltage(void) -{ - /* Disable Main regulator low voltage */ - PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS); -} - -/** - * @brief Enables Low Power Regulator low voltage mode. - * @retval None - */ -void HAL_PWREx_EnableLowRegulatorLowVoltage(void) -{ - /* Enable low power regulator */ - PWR->CR1 |= PWR_CR1_LPUDS; -} - -/** - * @brief Disables Low Power Regulator low voltage mode. - * @retval None - */ -void HAL_PWREx_DisableLowRegulatorLowVoltage(void) -{ - /* Disable low power regulator */ - PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS); -} - -/** - * @brief Activates the Over-Drive mode. - * @note This mode allows the CPU and the core logic to operate at a higher frequency - * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). - * @note It is recommended to enter or exit Over-drive mode when the application is not running - * critical tasks and when the system clock source is either HSI or HSE. - * During the Over-drive switch activation, no peripheral clocks should be enabled. - * The peripheral clocks must be enabled once the Over-drive mode is activated. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) -{ - uint32_t tickstart = 0; - - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable the Over-drive to extend the clock frequency to 216 MHz */ - __HAL_PWR_OVERDRIVE_ENABLE(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) - { - if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Enable the Over-drive switch */ - __HAL_PWR_OVERDRIVESWITCHING_ENABLE(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) - { - if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief Deactivates the Over-Drive mode. - * @note This mode allows the CPU and the core logic to operate at a higher frequency - * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). - * @note It is recommended to enter or exit Over-drive mode when the application is not running - * critical tasks and when the system clock source is either HSI or HSE. - * During the Over-drive switch activation, no peripheral clocks should be enabled. - * The peripheral clocks must be enabled once the Over-drive mode is activated. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) -{ - uint32_t tickstart = 0; - - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Disable the Over-drive switch */ - __HAL_PWR_OVERDRIVESWITCHING_DISABLE(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) - { - if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Disable the Over-drive */ - __HAL_PWR_OVERDRIVE_DISABLE(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) - { - if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @brief Enters in Under-Drive STOP mode. - * - * @note This mode can be selected only when the Under-Drive is already active - * - * @note This mode is enabled only with STOP low power mode. - * In this mode, the 1.2V domain is preserved in reduced leakage mode. This - * mode is only available when the main regulator or the low power regulator - * is in low voltage mode - * - * @note If the Under-drive mode was enabled, it is automatically disabled after - * exiting Stop mode. - * When the voltage regulator operates in Under-drive mode, an additional - * startup delay is induced when waking up from Stop mode. - * - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * - * @note When exiting Stop mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock. - * - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * - * @param Regulator: specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode - * and Flash memory in power-down when the device is in Stop under-drive mode - * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode - * and Flash memory in power-down when the device is in Stop under-drive mode - * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction - * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction - * @retval None - */ -HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry) -{ - uint32_t tempreg = 0; - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator)); - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - - /* Enable Power ctrl clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - /* Enable the Under-drive Mode ---------------------------------------------*/ - /* Clear Under-drive flag */ - __HAL_PWR_CLEAR_ODRUDR_FLAG(); - - /* Enable the Under-drive */ - __HAL_PWR_UNDERDRIVE_ENABLE(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for UnderDrive mode is ready */ - while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY)) - { - if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Select the regulator state in STOP mode ---------------------------------*/ - tempreg = PWR->CR1; - /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */ - tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS); - - /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ - tempreg |= Regulator; - - /* Store the new value */ - PWR->CR1 = tempreg; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Select STOP mode entry --------------------------------------------------*/ - if(STOPEntry == PWR_SLEEPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - - return HAL_OK; -} - -/** - * @brief Returns Voltage Scaling Range. - * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or - * PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1 - */ -uint32_t HAL_PWREx_GetVoltageRange(void) -{ - return (PWR->CR1 & PWR_CR1_VOS); -} - -/** - * @brief Configures the main internal regulator output voltage. - * @param VoltageScaling: specifies the regulator output voltage to achieve - * a tradeoff between performance and power consumption. - * This parameter can be one of the following values: - * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, - * typical output voltage at 1.4 V, - * system frequency up to 216 MHz. - * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, - * typical output voltage at 1.2 V, - * system frequency up to 180 MHz. - * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode, - * typical output voltage at 1.00 V, - * system frequency up to 151 MHz. - * @note To update the system clock frequency(SYSCLK): - * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig(). - * - Call the HAL_RCC_OscConfig() to configure the PLL. - * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale. - * - Set the new system clock frequency using the HAL_RCC_ClockConfig(). - * @note The scale can be modified only when the HSI or HSE clock source is selected - * as system clock source, otherwise the API returns HAL_ERROR. - * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits - * value in the PWR_CR1 register are not taken in account. - * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2. - * @note The new voltage scale is active only when the PLL is ON. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) -{ - uint32_t tickstart = 0; - - assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling)); - - /* Enable Power ctrl clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Check if the PLL is used as system clock or not */ - if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) - { - /* Disable the main PLL */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - /* Wait till PLL is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Set Range */ - __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); - - /* Enable the main PLL */ - __HAL_RCC_PLL_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) - { - if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - return HAL_ERROR; - } - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_PWR_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c deleted file mode 100644 index caf294c..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c +++ /dev/null @@ -1,2337 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_qspi.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief QSPI HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the QuadSPI interface (QSPI). - * + Initialization and de-initialization functions - * + Indirect functional mode management - * + Memory-mapped functional mode management - * + Auto-polling functional mode management - * + Interrupts and flags management - * + DMA channel configuration for indirect functional mode - * + Errors management and abort functionality - * - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - *** Initialization *** - ====================== - [..] - (#) As prerequisite, fill in the HAL_QSPI_MspInit() : - (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE(). - (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET(). - (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). - (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init(). - (++) If interrupt mode is used, enable and configure QuadSPI global - interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). - (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel - with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), - link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure - DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). - (#) Configure the flash size, the clock prescaler, the fifo threshold, the - clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function. - - *** Indirect functional mode *** - ================================ - [..] - (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT() - functions : - (++) Instruction phase : the mode used and if present the instruction opcode. - (++) Address phase : the mode used and if present the size and the address value. - (++) Alternate-bytes phase : the mode used and if present the size and the alternate - bytes values. - (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). - (++) Data phase : the mode used and if present the number of bytes. - (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay - if activated. - (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. - (#) If no data is required for the command, it is sent directly to the memory : - (++) In polling mode, the output of the function is done when the transfer is complete. - (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete. - (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or - HAL_QSPI_Transmit_IT() after the command configuration : - (++) In polling mode, the output of the function is done when the transfer is complete. - (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold - is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete. - (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and - HAL_QSPI_TxCpltCallback() will be called when the transfer is complete. - (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or - HAL_QSPI_Receive_IT() after the command configuration : - (++) In polling mode, the output of the function is done when the transfer is complete. - (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold - is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete. - (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and - HAL_QSPI_RxCpltCallback() will be called when the transfer is complete. - - *** Auto-polling functional mode *** - ==================================== - [..] - (#) Configure the command sequence and the auto-polling functional mode using the - HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions : - (++) Instruction phase : the mode used and if present the instruction opcode. - (++) Address phase : the mode used and if present the size and the address value. - (++) Alternate-bytes phase : the mode used and if present the size and the alternate - bytes values. - (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). - (++) Data phase : the mode used. - (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay - if activated. - (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. - (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND), - the polling interval and the automatic stop activation. - (#) After the configuration : - (++) In polling mode, the output of the function is done when the status match is reached. The - automatic stop is activated to avoid an infinite loop. - (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached. - - *** Memory-mapped functional mode *** - ===================================== - [..] - (#) Configure the command sequence and the memory-mapped functional mode using the - HAL_QSPI_MemoryMapped() functions : - (++) Instruction phase : the mode used and if present the instruction opcode. - (++) Address phase : the mode used and the size. - (++) Alternate-bytes phase : the mode used and if present the size and the alternate - bytes values. - (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). - (++) Data phase : the mode used. - (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay - if activated. - (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. - (++) The timeout activation and the timeout period. - (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on - the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires. - - *** Errors management and abort functionality *** - ================================================== - [..] - (#) HAL_QSPI_GetError() function gives the error raised during the last operation. - (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and - flushes the fifo : - (++) In polling mode, the output of the function is done when the transfer - complete bit is set and the busy bit cleared. - (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when - the transfer complete bi is set. - - *** Control functions *** - ========================= - [..] - (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver. - (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver. - (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP. - (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold - - *** Workarounds linked to Silicon Limitation *** - ==================================================== - [..] - (#) Workarounds Implemented inside HAL Driver - (++) Extra data written in the FIFO at the end of a read transfer - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup QSPI QSPI - * @brief HAL QSPI module driver - * @{ - */ -#ifdef HAL_QSPI_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup QSPI_Private_Constants - * @{ - */ -#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000U) /*!Instance)); - assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler)); - assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold)); - assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting)); - assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize)); - assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime)); - assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode)); - assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash)); - - if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE ) - { - assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID)); - } - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hqspi->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK */ - HAL_QSPI_MspInit(hqspi); - - /* Configure the default timeout for the QSPI memory access */ - HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE); - } - - /* Configure QSPI FIFO Threshold */ - MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8)); - - /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); - - if(status == HAL_OK) - { - - /* Configure QSPI Clock Prescaler and Sample Shift */ - MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash )); - - /* Configure QSPI Flash Size, CS High Time and Clock Mode */ - MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), - ((hqspi->Init.FlashSize << 16) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode)); - - /* Enable the QSPI peripheral */ - __HAL_QSPI_ENABLE(hqspi); - - /* Set QSPI error code to none */ - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - /* Initialize the QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; - } - - /* Release Lock */ - __HAL_UNLOCK(hqspi); - - /* Return function status */ - return status; -} - -/** - * @brief DeInitializes the QSPI peripheral - * @param hqspi: qspi handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) -{ - /* Check the QSPI handle allocation */ - if(hqspi == NULL) - { - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hqspi); - - /* Disable the QSPI Peripheral Clock */ - __HAL_QSPI_DISABLE(hqspi); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ - HAL_QSPI_MspDeInit(hqspi); - - /* Set QSPI error code to none */ - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - /* Initialize the QSPI state */ - hqspi->State = HAL_QSPI_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hqspi); - - return HAL_OK; -} - -/** - * @brief QSPI MSP Init - * @param hqspi: QSPI handle - * @retval None - */ - __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_QSPI_MspInit can be implemented in the user file - */ -} - -/** - * @brief QSPI MSP DeInit - * @param hqspi: QSPI handle - * @retval None - */ - __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_QSPI_MspDeInit can be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup QSPI_Exported_Functions_Group2 IO operation functions - * @brief QSPI Transmit/Receive functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to : - (+) Handle the interrupts. - (+) Handle the command sequence. - (+) Transmit data in blocking, interrupt or DMA mode. - (+) Receive data in blocking, interrupt or DMA mode. - (+) Manage the auto-polling functional mode. - (+) Manage the memory-mapped functional mode. - -@endverbatim - * @{ - */ - -/** - * @brief This function handles QSPI interrupt request. - * @param hqspi: QSPI handle - * @retval None. - */ -void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) -{ - __IO uint32_t *data_reg; - uint32_t flag = READ_REG(hqspi->Instance->SR); - uint32_t itsource = READ_REG(hqspi->Instance->CR); - - /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/ - if(((flag & QSPI_FLAG_FT)!= RESET) && ((itsource & QSPI_IT_FT)!= RESET)) - { - data_reg = &hqspi->Instance->DR; - - if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) - { - /* Transmission process */ - while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0) - { - if (hqspi->TxXferCount > 0) - { - /* Fill the FIFO until it is full */ - *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++; - hqspi->TxXferCount--; - } - else - { - /* No more data available for the transfer */ - /* Disable the QSPI FIFO Threshold Interrupt */ - __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); - break; - } - } - } - else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) - { - /* Receiving Process */ - while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0) - { - if (hqspi->RxXferCount > 0) - { - /* Read the FIFO until it is empty */ - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg; - hqspi->RxXferCount--; - } - else - { - /* All data have been received for the transfer */ - /* Disable the QSPI FIFO Threshold Interrupt */ - __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); - break; - } - } - } - - /* FIFO Threshold callback */ - HAL_QSPI_FifoThresholdCallback(hqspi); - } - - /* QSPI Transfer Complete interrupt occurred -------------------------------*/ - else if(((flag & QSPI_FLAG_TC)!= RESET) && ((itsource & QSPI_IT_TC)!= RESET)) - { - /* Clear interrupt */ - WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC); - - /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */ - __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); - - /* Transfer complete callback */ - if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) - { - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET) - { - /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ - CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - - /* Disable the DMA channel */ - __HAL_DMA_DISABLE(hqspi->hdma); - } - -#if defined(QSPI1_V1_0) -/* Clear Busy bit */ - HAL_QSPI_Abort_IT(hqspi); -#endif - - /* Change state of QSPI */ - hqspi->State = HAL_QSPI_STATE_READY; - - /* TX Complete callback */ - HAL_QSPI_TxCpltCallback(hqspi); - } - else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) - { - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET) - { - /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ - CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - - /* Disable the DMA channel */ - __HAL_DMA_DISABLE(hqspi->hdma); - } - else - { - data_reg = &hqspi->Instance->DR; - while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0) - { - if (hqspi->RxXferCount > 0) - { - /* Read the last data received in the FIFO until it is empty */ - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg; - hqspi->RxXferCount--; - } - else - { - /* All data have been received for the transfer */ - break; - } - } - } -#if defined(QSPI1_V1_0) - /* Workaround - Extra data written in the FIFO at the end of a read transfer */ - HAL_QSPI_Abort_IT(hqspi); -#endif /* QSPI_V1_0*/ - - /* Change state of QSPI */ - hqspi->State = HAL_QSPI_STATE_READY; - - /* RX Complete callback */ - HAL_QSPI_RxCpltCallback(hqspi); - } - else if(hqspi->State == HAL_QSPI_STATE_BUSY) - { - /* Change state of QSPI */ - hqspi->State = HAL_QSPI_STATE_READY; - - /* Command Complete callback */ - HAL_QSPI_CmdCpltCallback(hqspi); - } - else if(hqspi->State == HAL_QSPI_STATE_ABORT) - { - /* Change state of QSPI */ - hqspi->State = HAL_QSPI_STATE_READY; - - if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE) - { - /* Abort called by the user */ - - /* Abort Complete callback */ - HAL_QSPI_AbortCpltCallback(hqspi); - } - else - { - /* Abort due to an error (eg : DMA error) */ - - /* Error callback */ - HAL_QSPI_ErrorCallback(hqspi); - } - } - } - - /* QSPI Status Match interrupt occurred ------------------------------------*/ - else if(((flag & QSPI_FLAG_SM)!= RESET) && ((itsource & QSPI_IT_SM)!= RESET)) - { - /* Clear interrupt */ - WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM); - - /* Check if the automatic poll mode stop is activated */ - if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0) - { - /* Disable the QSPI Transfer Error and Status Match Interrupts */ - __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); - - /* Change state of QSPI */ - hqspi->State = HAL_QSPI_STATE_READY; - } - - /* Status match callback */ - HAL_QSPI_StatusMatchCallback(hqspi); - } - - /* QSPI Transfer Error interrupt occurred ----------------------------------*/ - else if(((flag & QSPI_FLAG_TE)!= RESET) && ((itsource & QSPI_IT_TE)!= RESET)) - { - /* Clear interrupt */ - WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE); - - /* Disable all the QSPI Interrupts */ - __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); - - /* Set error code */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER; - - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET) - { - /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ - CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - - /* Disable the DMA channel */ - hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; - HAL_DMA_Abort_IT(hqspi->hdma); - } - else - { - /* Change state of QSPI */ - hqspi->State = HAL_QSPI_STATE_READY; - - /* Error callback */ - HAL_QSPI_ErrorCallback(hqspi); - } - } - - /* QSPI Timeout interrupt occurred -----------------------------------------*/ - else if(((flag & QSPI_FLAG_TO)!= RESET) && ((itsource & QSPI_IT_TO)!= RESET)) - { - /* Clear interrupt */ - WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO); - - /* Time out callback */ - HAL_QSPI_TimeOutCallback(hqspi); - } -} - -/** - * @brief Sets the command configuration. - * @param hqspi: QSPI handle - * @param cmd : structure that contains the command configuration information - * @param Timeout : Time out duration - * @note This function is used only in Indirect Read or Write Modes - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout) -{ - HAL_StatusTypeDef status = HAL_ERROR; - uint32_t tickstart = HAL_GetTick(); - - /* Check the parameters */ - assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); - if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) - { - assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction)); - } - - assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode)); - if (cmd->AddressMode != QSPI_ADDRESS_NONE) - { - assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize)); - } - - assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode)); - if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) - { - assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize)); - } - - assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles)); - assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); - - assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); - assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); - assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_BUSY; - - /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); - - if (status == HAL_OK) - { - /* Call the configuration function */ - QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - - if (cmd->DataMode == QSPI_DATA_NONE) - { - /* When there is no data phase, the transfer start as soon as the configuration is done - so wait until TC flag is set to go back in idle state */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); - - if (status == HAL_OK) - { - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - - /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; - } - - } - else - { - /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; - } - } - } - else - { - status = HAL_BUSY; - } - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Return function status */ - return status; -} - -/** - * @brief Sets the command configuration in interrupt mode. - * @param hqspi: QSPI handle - * @param cmd : structure that contains the command configuration information - * @note This function is used only in Indirect Read or Write Modes - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd) -{ - HAL_StatusTypeDef status = HAL_ERROR; - uint32_t tickstart = HAL_GetTick(); - - /* Check the parameters */ - assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); - if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) - { - assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction)); - } - - assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode)); - if (cmd->AddressMode != QSPI_ADDRESS_NONE) - { - assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize)); - } - - assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode)); - if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) - { - assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize)); - } - - assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles)); - assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); - - assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); - assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); - assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_BUSY; - - /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); - - if (status == HAL_OK) - { - if (cmd->DataMode == QSPI_DATA_NONE) - { - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); - } - - /* Call the configuration function */ - QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - - if (cmd->DataMode == QSPI_DATA_NONE) - { - /* When there is no data phase, the transfer start as soon as the configuration is done - so activate TC and TE interrupts */ - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Enable the QSPI Transfer Error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC); - } - else - { - /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - } - else - { - status = HAL_BUSY; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - - /* Return function status */ - return status; -} - -/** - * @brief Transmit an amount of data in blocking mode. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer - * @param Timeout : Time out duration - * @note This function is used only in Indirect Write Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart = HAL_GetTick(); - __IO uint32_t *data_reg = &hqspi->Instance->DR; - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - if(pData != NULL ) - { - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; - - /* Configure counters and size of the handle */ - hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->pTxBuffPtr = pData; - - /* Configure QSPI: CCR register with functional as indirect write */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - - while(hqspi->TxXferCount > 0) - { - /* Wait until FT flag is set to send data */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout); - - if (status != HAL_OK) - { - break; - } - - *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++; - hqspi->TxXferCount--; - } - - if (status == HAL_OK) - { - /* Wait until TC flag is set to go back in idle state */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); - - if (status == HAL_OK) - { - /* Clear Transfer Complete bit */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - -#if defined(QSPI1_V1_0) - /* Clear Busy bit */ - status = HAL_QSPI_Abort(hqspi); -#endif /* QSPI_V1_0 */ - } - } - - /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; - } - else - { - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - } - } - else - { - status = HAL_BUSY; - } - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - return status; -} - - -/** - * @brief Receive an amount of data in blocking mode - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer - * @param Timeout : Time out duration - * @note This function is used only in Indirect Read Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart = HAL_GetTick(); - uint32_t addr_reg = READ_REG(hqspi->Instance->AR); - __IO uint32_t *data_reg = &hqspi->Instance->DR; - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - if(pData != NULL ) - { - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; - - /* Configure counters and size of the handle */ - hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->pRxBuffPtr = pData; - - /* Configure QSPI: CCR register with functional as indirect read */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); - - /* Start the transfer by re-writing the address in AR register */ - WRITE_REG(hqspi->Instance->AR, addr_reg); - - while(hqspi->RxXferCount > 0) - { - /* Wait until FT or TC flag is set to read received data */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout); - - if (status != HAL_OK) - { - break; - } - - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg; - hqspi->RxXferCount--; - } - - if (status == HAL_OK) - { - /* Wait until TC flag is set to go back in idle state */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); - - if (status == HAL_OK) - { - /* Clear Transfer Complete bit */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - -#if defined(QSPI1_V1_0) - /* Workaround - Extra data written in the FIFO at the end of a read transfer */ - status = HAL_QSPI_Abort(hqspi); -#endif /* QSPI_V1_0 */ - } - } - - /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; - } - else - { - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - } - } - else - { - status = HAL_BUSY; - } - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - return status; -} - -/** - * @brief Send an amount of data in interrupt mode - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer - * @note This function is used only in Indirect Write Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - if(pData != NULL ) - { - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; - - /* Configure counters and size of the handle */ - hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->pTxBuffPtr = pData; - - /* Configure QSPI: CCR register with functional as indirect write */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); - - } - else - { - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - } - else - { - status = HAL_BUSY; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - - return status; -} - -/** - * @brief Receive an amount of data in no-blocking mode with Interrupt - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer - * @note This function is used only in Indirect Read Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t addr_reg = READ_REG(hqspi->Instance->AR); - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - if(pData != NULL ) - { - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; - - /* Configure counters and size of the handle */ - hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->pRxBuffPtr = pData; - - /* Configure QSPI: CCR register with functional as indirect read */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); - - /* Start the transfer by re-writing the address in AR register */ - WRITE_REG(hqspi->Instance->AR, addr_reg); - - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); - } - else - { - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - } - else - { - status = HAL_BUSY; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - - return status; -} - -/** - * @brief Sends an amount of data in non blocking mode with DMA. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer - * @note This function is used only in Indirect Write Mode - * @note If DMA peripheral access is configured as halfword, the number - * of data and the fifo threshold should be aligned on halfword - * @note If DMA peripheral access is configured as word, the number - * of data and the fifo threshold should be aligned on word - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t *tmp; - uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1); - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - /* Clear the error code */ - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - if(pData != NULL ) - { - /* Configure counters of the handle */ - if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) - { - hqspi->TxXferCount = data_size; - } - else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) - { - if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0)) - { - /* The number of data or the fifo threshold is not aligned on halfword - => no transfer possible with DMA peripheral access configured as halfword */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - else - { - hqspi->TxXferCount = (data_size >> 1); - } - } - else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) - { - if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0)) - { - /* The number of data or the fifo threshold is not aligned on word - => no transfer possible with DMA peripheral access configured as word */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - else - { - hqspi->TxXferCount = (data_size >> 2); - } - } - - if (status == HAL_OK) - { - - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; - - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); - - /* Configure size and pointer of the handle */ - hqspi->TxXferSize = hqspi->TxXferCount; - hqspi->pTxBuffPtr = pData; - - /* Configure QSPI: CCR register with functional mode as indirect write */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - - /* Set the QSPI DMA transfer complete callback */ - hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt; - - /* Set the QSPI DMA Half transfer complete callback */ - hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt; - - /* Set the DMA error callback */ - hqspi->hdma->XferErrorCallback = QSPI_DMAError; - - /* Clear the DMA abort callback */ - hqspi->hdma->XferAbortCallback = NULL; - - /* Configure the direction of the DMA */ - hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; - MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); - - /* Enable the QSPI transmit DMA Channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize); - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Enable the QSPI transfer error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - - /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - } - } - else - { - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - - status = HAL_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - } - else - { - status = HAL_BUSY; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - - return status; -} - -/** - * @brief Receives an amount of data in non blocking mode with DMA. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer. - * @note This function is used only in Indirect Read Mode - * @note If DMA peripheral access is configured as halfword, the number - * of data and the fifo threshold should be aligned on halfword - * @note If DMA peripheral access is configured as word, the number - * of data and the fifo threshold should be aligned on word - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t *tmp; - uint32_t addr_reg = READ_REG(hqspi->Instance->AR); - uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1); - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - if(pData != NULL ) - { - /* Configure counters of the handle */ - if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) - { - hqspi->RxXferCount = data_size; - } - else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) - { - if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0)) - { - /* The number of data or the fifo threshold is not aligned on halfword - => no transfer possible with DMA peripheral access configured as halfword */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - else - { - hqspi->RxXferCount = (data_size >> 1); - } - } - else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) - { - if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0)) - { - /* The number of data or the fifo threshold is not aligned on word - => no transfer possible with DMA peripheral access configured as word */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - else - { - hqspi->RxXferCount = (data_size >> 2); - } - } - - if (status == HAL_OK) - { - - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; - - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); - - /* Configure size and pointer of the handle */ - hqspi->RxXferSize = hqspi->RxXferCount; - hqspi->pRxBuffPtr = pData; - - /* Set the QSPI DMA transfer complete callback */ - hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt; - - /* Set the QSPI DMA Half transfer complete callback */ - hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt; - - /* Set the DMA error callback */ - hqspi->hdma->XferErrorCallback = QSPI_DMAError; - - /* Clear the DMA abort callback */ - hqspi->hdma->XferAbortCallback = NULL; - - /* Configure the direction of the DMA */ - hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; - MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); - - /* Enable the DMA Channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize); - - /* Configure QSPI: CCR register with functional as indirect read */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); - - /* Start the transfer by re-writing the address in AR register */ - WRITE_REG(hqspi->Instance->AR, addr_reg); - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Enable the QSPI transfer error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - - /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - } - } - else - { - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - } - else - { - status = HAL_BUSY; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - - return status; -} - -/** - * @brief Configure the QSPI Automatic Polling Mode in blocking mode. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information. - * @param cfg: structure that contains the polling configuration information. - * @param Timeout : Time out duration - * @note This function is used only in Automatic Polling Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout) -{ - HAL_StatusTypeDef status = HAL_ERROR; - uint32_t tickstart = HAL_GetTick(); - - /* Check the parameters */ - assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); - if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) - { - assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction)); - } - - assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode)); - if (cmd->AddressMode != QSPI_ADDRESS_NONE) - { - assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize)); - } - - assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode)); - if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) - { - assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize)); - } - - assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles)); - assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); - - assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); - assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); - assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); - - assert_param(IS_QSPI_INTERVAL(cfg->Interval)); - assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize)); - assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode)); - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; - - /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); - - if (status == HAL_OK) - { - /* Configure QSPI: PSMAR register with the status match value */ - WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); - - /* Configure QSPI: PSMKR register with the status mask value */ - WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); - - /* Configure QSPI: PIR register with the interval value */ - WRITE_REG(hqspi->Instance->PIR, cfg->Interval); - - /* Configure QSPI: CR register with Match mode and Automatic stop enabled - (otherwise there will be an infinite loop in blocking mode) */ - MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), - (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE)); - - /* Call the configuration function */ - cmd->NbData = cfg->StatusBytesSize; - QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); - - /* Wait until SM flag is set to go back in idle state */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout); - - if (status == HAL_OK) - { - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM); - - /* Update state */ - hqspi->State = HAL_QSPI_STATE_READY; - } - } - } - else - { - status = HAL_BUSY; - } - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Return function status */ - return status; -} - -/** - * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information. - * @param cfg: structure that contains the polling configuration information. - * @note This function is used only in Automatic Polling Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg) -{ - HAL_StatusTypeDef status = HAL_ERROR; - uint32_t tickstart = HAL_GetTick(); - - /* Check the parameters */ - assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); - if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) - { - assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction)); - } - - assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode)); - if (cmd->AddressMode != QSPI_ADDRESS_NONE) - { - assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize)); - } - - assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode)); - if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) - { - assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize)); - } - - assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles)); - assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); - - assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); - assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); - assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); - - assert_param(IS_QSPI_INTERVAL(cfg->Interval)); - assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize)); - assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode)); - assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop)); - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; - - /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); - - if (status == HAL_OK) - { - /* Configure QSPI: PSMAR register with the status match value */ - WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); - - /* Configure QSPI: PSMKR register with the status mask value */ - WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); - - /* Configure QSPI: PIR register with the interval value */ - WRITE_REG(hqspi->Instance->PIR, cfg->Interval); - - /* Configure QSPI: CR register with Match mode and Automatic stop mode */ - MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), - (cfg->MatchMode | cfg->AutomaticStop)); - - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM); - - /* Call the configuration function */ - cmd->NbData = cfg->StatusBytesSize; - QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Enable the QSPI Transfer Error and status match Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); - - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - } - else - { - status = HAL_BUSY; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - - /* Return function status */ - return status; -} - -/** - * @brief Configure the Memory Mapped mode. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information. - * @param cfg: structure that contains the memory mapped configuration information. - * @note This function is used only in Memory mapped Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg) -{ - HAL_StatusTypeDef status = HAL_ERROR; - uint32_t tickstart = HAL_GetTick(); - - /* Check the parameters */ - assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); - if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) - { - assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction)); - } - - assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode)); - if (cmd->AddressMode != QSPI_ADDRESS_NONE) - { - assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize)); - } - - assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode)); - if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) - { - assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize)); - } - - assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles)); - assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); - - assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); - assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); - assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); - - assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation)); - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED; - - /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); - - if (status == HAL_OK) - { - /* Configure QSPI: CR register with timeout counter enable */ - MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation); - - if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE) - { - assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod)); - - /* Configure QSPI: LPTR register with the low-power timeout value */ - WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod); - - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO); - - /* Enable the QSPI TimeOut Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO); - } - - /* Call the configuration function */ - QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED); - } - } - else - { - status = HAL_BUSY; - } - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Return function status */ - return status; -} - -/** - * @brief Transfer Error callbacks - * @param hqspi: QSPI handle - * @retval None - */ -__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_QSPI_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief Abort completed callback. - * @param hqspi: QSPI handle - * @retval None - */ -__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_QSPI_AbortCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Command completed callback. - * @param hqspi: QSPI handle - * @retval None - */ -__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_QSPI_CmdCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callbacks. - * @param hqspi: QSPI handle - * @retval None - */ -__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_QSPI_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Tx Transfer completed callbacks. - * @param hqspi: QSPI handle - * @retval None - */ - __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_QSPI_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Half Transfer completed callbacks. - * @param hqspi: QSPI handle - * @retval None - */ -__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Tx Half Transfer completed callbacks. - * @param hqspi: QSPI handle - * @retval None - */ - __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief FIFO Threshold callbacks - * @param hqspi: QSPI handle - * @retval None - */ -__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file - */ -} - -/** - * @brief Status Match callbacks - * @param hqspi: QSPI handle - * @retval None - */ -__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_QSPI_StatusMatchCallback could be implemented in the user file - */ -} - -/** - * @brief Timeout callbacks - * @param hqspi: QSPI handle - * @retval None - */ -__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_QSPI_TimeOutCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions - * @brief QSPI control and State functions - * -@verbatim - =============================================================================== - ##### Peripheral Control and State functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to : - (+) Check in run-time the state of the driver. - (+) Check the error code set during last operation. - (+) Abort any operation. -..... -@endverbatim - * @{ - */ - -/** - * @brief Return the QSPI handle state. - * @param hqspi: QSPI handle - * @retval HAL state - */ -HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) -{ - /* Return QSPI handle state */ - return hqspi->State; -} - -/** -* @brief Return the QSPI error code -* @param hqspi: QSPI handle -* @retval QSPI Error Code -*/ -uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) -{ - return hqspi->ErrorCode; -} - -/** -* @brief Abort the current transmission -* @param hqspi: QSPI handle -* @retval HAL status -*/ -HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart = HAL_GetTick(); - - /* Check if the state is in one of the busy states */ - if ((hqspi->State & 0x2) != 0) - { - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET) - { - /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ - CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - - /* Abort DMA channel */ - status = HAL_DMA_Abort(hqspi->hdma); - if(status != HAL_OK) - { - hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; - } - } - - /* Configure QSPI: CR register with Abort request */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); - - /* Wait until TC flag is set to go back in idle state */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); - - if(status == HAL_OK) - { - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - - /* Wait until BUSY flag is reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); - } - - if (status == HAL_OK) - { - /* Update state */ - hqspi->State = HAL_QSPI_STATE_READY; - } - } - - return status; -} - -/** -* @brief Abort the current transmission (non-blocking function) -* @param hqspi: QSPI handle -* @retval HAL status -*/ -HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check if the state is in one of the busy states */ - if ((hqspi->State & 0x2) != 0) - { - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_ABORT; - - /* Disable all interrupts */ - __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE)); - - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET) - { - /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ - CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - - /* Abort DMA channel */ - hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; - HAL_DMA_Abort_IT(hqspi->hdma); - } - else - { - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - - /* Enable the QSPI Transfer Complete Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); - - /* Configure QSPI: CR register with Abort request */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); - } - } - - return status; -} - -/** @brief Set QSPI timeout - * @param hqspi: QSPI handle. - * @param Timeout: Timeout for the QSPI memory access. - * @retval None - */ -void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) -{ - hqspi->Timeout = Timeout; -} - -/** @brief Set QSPI Fifo threshold. - * @param hqspi: QSPI handle. - * @param Threshold: Threshold of the Fifo (value between 1 and 16). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - /* Synchronize init structure with new FIFO threshold value */ - hqspi->Init.FifoThreshold = Threshold; - - /* Configure QSPI FIFO Threshold */ - MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, - ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES))); - } - else - { - status = HAL_BUSY; - } - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Return function status */ - return status; -} - -/** @brief Get QSPI Fifo threshold. - * @param hqspi: QSPI handle. - * @retval Fifo threshold (value between 1 and 16) - */ -uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) -{ - return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> POSITION_VAL(QUADSPI_CR_FTHRES)) + 1); -} - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief DMA QSPI receive process complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) -{ - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hqspi->RxXferCount = 0; - - /* Enable the QSPI transfer complete Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); -} - -/** - * @brief DMA QSPI transmit process complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) -{ - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hqspi->TxXferCount = 0; - - /* Enable the QSPI transfer complete Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); -} - -/** - * @brief DMA QSPI receive process half complete callback - * @param hdma : DMA handle - * @retval None - */ -static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - HAL_QSPI_RxHalfCpltCallback(hqspi); -} - -/** - * @brief DMA QSPI transmit process half complete callback - * @param hdma : DMA handle - * @retval None - */ -static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) -{ - QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - HAL_QSPI_TxHalfCpltCallback(hqspi); -} - -/** - * @brief DMA QSPI communication error callback. - * @param hdma: DMA handle - * @retval None - */ -static void QSPI_DMAError(DMA_HandleTypeDef *hdma) -{ - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* if DMA error is FIFO error ignore it */ - if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) - { - hqspi->RxXferCount = 0; - hqspi->TxXferCount = 0; - hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; - - /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ - CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - - /* Abort the QSPI */ - HAL_QSPI_Abort_IT(hqspi); - } -} - -/** - * @brief DMA QSPI abort complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) -{ - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - hqspi->RxXferCount = 0; - hqspi->TxXferCount = 0; - - if(hqspi->State == HAL_QSPI_STATE_ABORT) - { - /* DMA Abort called by QSPI abort */ - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - - /* Enable the QSPI Transfer Complete Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); - - /* Configure QSPI: CR register with Abort request */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); - } - else - { - /* DMA Abort called due to a transfer error interrupt */ - /* Change state of QSPI */ - hqspi->State = HAL_QSPI_STATE_READY; - - /* Error callback */ - HAL_QSPI_ErrorCallback(hqspi); - } -} - -/** - * @brief Wait for a flag state until timeout. - * @param hqspi: QSPI handle - * @param Flag: Flag checked - * @param State: Value of the flag expected - * @param tickstart: Start tick value - * @param Timeout: Duration of the time out - * @retval HAL status - */ -static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, - FlagStatus State, uint32_t tickstart, uint32_t Timeout) -{ - /* Wait until flag is in expected state */ - while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) - { - hqspi->State = HAL_QSPI_STATE_ERROR; - hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; - - return HAL_ERROR; - } - } - } - return HAL_OK; -} - -/** - * @brief Configure the communication registers. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information - * @param FunctionalMode: functional mode to configured - * This parameter can be one of the following values: - * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode - * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode - * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode - * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode - * @retval None - */ -static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode) -{ - assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode)); - - if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)) - { - /* Configure QSPI: DLR register with the number of data to read or write */ - WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1)); - } - - if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) - { - if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) - { - /* Configure QSPI: ABR register with alternate bytes value */ - WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes); - - if (cmd->AddressMode != QSPI_ADDRESS_NONE) - { - /*---- Command with instruction, address and alternate bytes ----*/ - /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize | - cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | - cmd->InstructionMode | cmd->Instruction | FunctionalMode)); - - if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) - { - /* Configure QSPI: AR register with address value */ - WRITE_REG(hqspi->Instance->AR, cmd->Address); - } - } - else - { - /*---- Command with instruction and alternate bytes ----*/ - /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize | - cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | - cmd->Instruction | FunctionalMode)); - } - } - else - { - if (cmd->AddressMode != QSPI_ADDRESS_NONE) - { - /*---- Command with instruction and address ----*/ - /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | - cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | - cmd->Instruction | FunctionalMode)); - - if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) - { - /* Configure QSPI: AR register with address value */ - WRITE_REG(hqspi->Instance->AR, cmd->Address); - } - } - else - { - /*---- Command with only instruction ----*/ - /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | - cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | - FunctionalMode)); - } - } - } - else - { - if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) - { - /* Configure QSPI: ABR register with alternate bytes value */ - WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes); - - if (cmd->AddressMode != QSPI_ADDRESS_NONE) - { - /*---- Command with address and alternate bytes ----*/ - /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize | - cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | - cmd->InstructionMode | FunctionalMode)); - - if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) - { - /* Configure QSPI: AR register with address value */ - WRITE_REG(hqspi->Instance->AR, cmd->Address); - } - } - else - { - /*---- Command with only alternate bytes ----*/ - /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize | - cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | - FunctionalMode)); - } - } - else - { - if (cmd->AddressMode != QSPI_ADDRESS_NONE) - { - /*---- Command with only address ----*/ - /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | - cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | - FunctionalMode)); - - if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) - { - /* Configure QSPI: AR register with address value */ - WRITE_REG(hqspi->Instance->AR, cmd->Address); - } - } - else - { - /*---- Command with only data phase ----*/ - if (cmd->DataMode != QSPI_DATA_NONE) - { - /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | - cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); - } - } - } - } -} -/** - * @} - */ - -#endif /* HAL_QSPI_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c deleted file mode 100644 index f156a9a..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c +++ /dev/null @@ -1,1101 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_rcc.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief RCC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Reset and Clock Control (RCC) peripheral: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - @verbatim - ============================================================================== - ##### RCC specific features ##### - ============================================================================== - [..] - After reset the device is running from Internal High Speed oscillator - (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache - and I-Cache are disabled, and all peripherals are off except internal - SRAM, Flash and JTAG. - (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; - all peripherals mapped on these busses are running at HSI speed. - (+) The clock for all peripherals is switched off, except the SRAM and FLASH. - (+) All GPIOs are in input floating state, except the JTAG pins which - are assigned to be used for debug purpose. - - [..] - Once the device started from reset, the user application has to: - (+) Configure the clock source to be used to drive the System clock - (if the application needs higher frequency/performance) - (+) Configure the System clock frequency and Flash settings - (+) Configure the AHB and APB busses prescalers - (+) Enable the clock for the peripheral(s) to be used - (+) Configure the clock source(s) for peripherals which clocks are not - derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) - - ##### RCC Limitations ##### - ============================================================================== - [..] - A delay between an RCC peripheral clock enable and the effective peripheral - enabling should be taken into account in order to manage the peripheral read/write - from/to registers. - (+) This delay depends on the peripheral mapping. - (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle - after the clock enable bit is set on the hardware register - (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle - after the clock enable bit is set on the hardware register - - [..] - Implemented Workaround: - (+) For AHB & APB peripherals, a dummy read to the peripheral register has been - inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup RCC RCC - * @brief RCC HAL module driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/** @defgroup RCC_Private_Macros RCC Private Macros - * @{ - */ - -#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() -#define MCO1_GPIO_PORT GPIOA -#define MCO1_PIN GPIO_PIN_8 - -#define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() -#define MCO2_GPIO_PORT GPIOC -#define MCO2_PIN GPIO_PIN_9 - -/** - * @} - */ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup RCC_Private_Variables RCC Private Variables - * @{ - */ - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Functions RCC Exported Functions - * @{ - */ - -/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - =============================================================================== -##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to configure the internal/external oscillators - (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 - and APB2). - - [..] Internal/external clock and PLL configuration - (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through - the PLL as System clock source. - - (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC - clock source. - - (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also as RTC clock source. - - (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. - - (#) PLL (clocked by HSI or HSE), featuring two different output clocks: - (++) The first output is used to generate the high speed system clock (up to 216 MHz) - (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), - the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). - - (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS() - and if a HSE clock failure occurs(HSE used directly or through PLL as System - clock source), the System clock is automatically switched to HSI and an interrupt - is generated if enabled. The interrupt is linked to the Cortex-M7 NMI - (Non-Maskable Interrupt) exception vector. - - (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL - clock (through a configurable prescaler) on PA8 pin. - - (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S - clock (through a configurable prescaler) on PC9 pin. - - [..] System, AHB and APB busses clocks configuration - (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, - HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable - prescaler and used to clock the CPU, memory and peripherals mapped - on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived - from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these busses. You can use - "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. - - -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: - (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or - from an external clock mapped on the I2S_CKIN pin. - You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. - (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or - from an external clock mapped on the I2S_CKIN pin. - You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. - (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock - divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE() - macros to configure this clock. - (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz - to work correctly, while the SDIO require a frequency equal or lower than - to 48. This clock is derived of the main PLL through PLLQ divider. - (+@) IWDG clock which is always the LSI clock. -@endverbatim - * @{ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - HSI ON and used as system clock source - * - HSE, PLL and PLLI2S OFF - * - AHB, APB1 and APB2 prescaler set to 1. - * - CSS, MCO1 and MCO2 OFF - * - All interrupts disabled - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval None - */ -void HAL_RCC_DeInit(void) -{ - /* Set HSION bit */ - SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); - - /* Reset CFGR register */ - CLEAR_REG(RCC->CFGR); - - /* Reset HSEON, CSSON, PLLON, PLLI2S */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON); - - /* Reset PLLCFGR register */ - CLEAR_REG(RCC->PLLCFGR); - SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | ((uint32_t)0x20000000U)); - - /* Reset PLLI2SCFGR register */ - CLEAR_REG(RCC->PLLI2SCFGR); - SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1); - - /* Reset HSEBYP bit */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); - - /* Disable all interrupts */ - CLEAR_REG(RCC->CIR); - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HSI_VALUE; -} - -/** - * @brief Initializes the RCC Oscillators according to the specified parameters in the - * RCC_OscInitTypeDef. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC Oscillators. - * @note The PLL is not disabled when used as system clock. - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not - * supported by this function. User should request a transition to LSE Off - * first and then LSE On or LSE Bypass. - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this function. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - - /*------------------------------- HSE Configuration ------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - { - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); - /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) - || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) - { - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - { - return HAL_ERROR; - } - } - else - { - /* Set the new HSE configuration ---------------------------------------*/ - __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - - /* Check the HSE State */ - if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSE is bypassed or disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*----------------------------- HSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); - assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) - || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) - { - /* When HSI is used as system clock it will not disabled */ - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - { - return HAL_ERROR; - } - /* Otherwise, just the calibration is allowed */ - else - { - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - } - else - { - /* Check the HSI State */ - if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) - { - /* Enable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - else - { - /* Disable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*------------------------------ LSI Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - { - /* Check the parameters */ - assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); - - /* Check the LSI State */ - if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) - { - /* Enable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /*------------------------------ LSE Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - { - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - PWR->CR1 |= PWR_CR1_DBP; - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while((PWR->CR1 & PWR_CR1_DBP) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Set the new LSE configuration -----------------------------------------*/ - __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - /* Check the LSE State */ - if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /*-------------------------------- PLL Configuration -----------------------*/ - /* Check the parameters */ - assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); - if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - { - /* Check if the PLL is used as system clock or not */ - if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - { - /* Check the parameters */ - assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); - assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); - assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); - assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); - assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); - - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Configure the main PLL clock source, multiplication and division factors. */ - WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ - RCC_OscInitStruct->PLL.PLLM | \ - (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ - (((RCC_OscInitStruct->PLL.PLLP >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \ - (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ)))); - /* Enable the main PLL. */ - __HAL_RCC_PLL_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - else - { - return HAL_ERROR; - } - } - return HAL_OK; -} - -/** - * @brief Initializes the CPU, AHB and APB busses clocks according to the specified - * parameters in the RCC_ClkInitStruct. - * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC peripheral. - * @param FLatency: FLASH Latency, this parameter depend on device selected - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated by HAL_RCC_GetHCLKFreq() function called within this function - * - * @note The HSI is used (enabled by hardware) as system clock source after - * startup from Reset, wake-up from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * You can use HAL_RCC_GetClockConfig() function to know which clock is - * currently used as system clock source. - * @note Depending on the device voltage range, the software has to set correctly - * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency - * (for more details refer to section above "Initialization/de-initialization functions") - * @retval None - */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); - assert_param(IS_FLASH_LATENCY(FLatency)); - - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. */ - - /* Increasing the CPU frequency */ - if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) - { - return HAL_ERROR; - } - } - - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - { - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - } - - /*------------------------- SYSCLK Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - /* Check the HSE ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - return HAL_ERROR; - } - } - /* PLL is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - /* Check the PLL ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - return HAL_ERROR; - } - } - /* HSI is selected as System Clock Source */ - else - { - /* Check the HSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - return HAL_ERROR; - } - } - - __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - - /* Decreasing the number of wait states because of lower CPU frequency */ - if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) - { - return HAL_ERROR; - } - } - - /*-------------------------- PCLK1 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); - } - - /*-------------------------- PCLK2 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); - } - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)]; - - /* Configure the source of time base considering new system clocks settings*/ - HAL_InitTick (TICK_INT_PRIORITY); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions - * @brief RCC clocks control functions - * - @verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the RCC Clocks - frequencies. - -@endverbatim - * @{ - */ - -/** - * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). - * @note PA8/PC9 should be configured in alternate function mode. - * @param RCC_MCOx: specifies the output direction for the clock source. - * This parameter can be one of the following values: - * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8). - * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9). - * @param RCC_MCOSource: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source - * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source - * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source - * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source - * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source - * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source - * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source - * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source - * @param RCC_MCODiv: specifies the MCOx prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCODIV_1: no division applied to MCOx clock - * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock - * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock - * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock - * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock - * @retval None - */ -void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) -{ - GPIO_InitTypeDef GPIO_InitStruct; - /* Check the parameters */ - assert_param(IS_RCC_MCO(RCC_MCOx)); - assert_param(IS_RCC_MCODIV(RCC_MCODiv)); - /* RCC_MCO1 */ - if(RCC_MCOx == RCC_MCO1) - { - assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); - - /* MCO1 Clock Enable */ - MCO1_CLK_ENABLE(); - - /* Configure the MCO1 pin in alternate function mode */ - GPIO_InitStruct.Pin = MCO1_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Alternate = GPIO_AF0_MCO; - HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); - - /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); - } - else - { - assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); - - /* MCO2 Clock Enable */ - MCO2_CLK_ENABLE(); - - /* Configure the MCO2 pin in alternate function mode */ - GPIO_InitStruct.Pin = MCO2_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Alternate = GPIO_AF0_MCO; - HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); - - /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3))); - } -} - -/** - * @brief Enables the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector. - * @retval None - */ -void HAL_RCC_EnableCSS(void) -{ - SET_BIT(RCC->CR, RCC_CR_CSSON); -} - -/** - * @brief Disables the Clock Security System. - * @retval None - */ -void HAL_RCC_DisableCSS(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_CSSON); -} - -/** - * @brief Returns the SYSCLK frequency - * - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) - * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * @note (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * @note (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @note This function can be used by the user application to compute the - * baudrate for the communication peripherals or configure other parameters. - * - * @note Each time SYSCLK changes, this function must be called to update the - * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * - * @retval SYSCLK frequency - */ -uint32_t HAL_RCC_GetSysClockFreq(void) -{ - uint32_t pllm = 0, pllvco = 0, pllp = 0; - uint32_t sysclockfreq = 0; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (RCC->CFGR & RCC_CFGR_SWS) - { - case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ - { - sysclockfreq = HSI_VALUE; - break; - } - case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ - { - sysclockfreq = HSE_VALUE; - break; - } - case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */ - { - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN - SYSCLK = PLL_VCO / PLLP */ - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) - { - /* HSE used as PLL clock source */ - pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); - } - else - { - /* HSI used as PLL clock source */ - pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); - } - pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2); - - sysclockfreq = pllvco/pllp; - break; - } - default: - { - sysclockfreq = HSI_VALUE; - break; - } - } - return sysclockfreq; -} - -/** - * @brief Returns the HCLK frequency - * @note Each time HCLK changes, this function must be called to update the - * right HCLK value. Otherwise, any configuration based on this function will be incorrect. - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. - * @retval HCLK frequency - */ -uint32_t HAL_RCC_GetHCLKFreq(void) -{ - return SystemCoreClock; -} - -/** - * @brief Returns the PCLK1 frequency - * @note Each time PCLK1 changes, this function must be called to update the - * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK1 frequency - */ -uint32_t HAL_RCC_GetPCLK1Freq(void) -{ - /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]); -} - -/** - * @brief Returns the PCLK2 frequency - * @note Each time PCLK2 changes, this function must be called to update the - * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK2 frequency - */ -uint32_t HAL_RCC_GetPCLK2Freq(void) -{ - /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]); -} - -/** - * @brief Configures the RCC_OscInitStruct according to the internal - * RCC configuration registers. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that - * will be configured. - * @retval None - */ -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - /* Set all possible values for the Oscillator type parameter ---------------*/ - RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; - - /* Get the HSE configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) - { - RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; - } - else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) - { - RCC_OscInitStruct->HSEState = RCC_HSE_ON; - } - else - { - RCC_OscInitStruct->HSEState = RCC_HSE_OFF; - } - - /* Get the HSI configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) - { - RCC_OscInitStruct->HSIState = RCC_HSI_ON; - } - else - { - RCC_OscInitStruct->HSIState = RCC_HSI_OFF; - } - - RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM)); - - /* Get the LSE configuration -----------------------------------------------*/ - if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) - { - RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; - } - else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) - { - RCC_OscInitStruct->LSEState = RCC_LSE_ON; - } - else - { - RCC_OscInitStruct->LSEState = RCC_LSE_OFF; - } - - /* Get the LSI configuration -----------------------------------------------*/ - if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) - { - RCC_OscInitStruct->LSIState = RCC_LSI_ON; - } - else - { - RCC_OscInitStruct->LSIState = RCC_LSI_OFF; - } - - /* Get the PLL configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; - } - else - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; - } - RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); - RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)); - RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP)); - RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)); -} - -/** - * @brief Configures the RCC_ClkInitStruct according to the internal - * RCC configuration registers. - * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that - * will be configured. - * @param pFLatency: Pointer on the Flash Latency. - * @retval None - */ -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) -{ - /* Set all possible values for the Clock type parameter --------------------*/ - RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - - /* Get the SYSCLK configuration --------------------------------------------*/ - RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); - - /* Get the HCLK configuration ----------------------------------------------*/ - RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); - - /* Get the APB1 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); - - /* Get the APB2 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); - - /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); -} - -/** - * @brief This function handles the RCC CSS interrupt request. - * @note This API should be called under the NMI_Handler(). - * @retval None - */ -void HAL_RCC_NMI_IRQHandler(void) -{ - /* Check RCC CSSF flag */ - if(__HAL_RCC_GET_IT(RCC_IT_CSS)) - { - /* RCC Clock Security System interrupt user callback */ - HAL_RCC_CSSCallback(); - - /* Clear RCC CSS pending bit */ - __HAL_RCC_CLEAR_IT(RCC_IT_CSS); - } -} - -/** - * @brief RCC Clock Security System interrupt callback - * @retval None - */ -__weak void HAL_RCC_CSSCallback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RCC_CSSCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RCC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c deleted file mode 100644 index 7e42db2..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c +++ /dev/null @@ -1,1340 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_rcc_ex.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Extension RCC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities RCC extension peripheral: - * + Extended Peripheral Control functions - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup RCCEx RCCEx - * @brief RCCEx HAL module driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup RCCEx_Private_Defines RCCEx Private Defines - * @{ - */ - -#define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */ -#define PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */ - -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/** @defgroup RCCEx_Private_Macros RCCEx Private Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup RCCEx_Private_Macros RCCEx Private Macros - * @{ - */ - -/** - * @} - */ - - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions - * @{ - */ - -/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Extended Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the RCC Clocks - frequencies. - [..] - (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to - select the RTC clock source; in this case the Backup domain will be reset in - order to modify the RTC Clock source, as consequence RTC registers (including - the backup registers) and RCC_BDCR register will be set to their reset values. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the RCC extended peripherals clocks according to the specified - * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that - * contains the configuration information for the Extended Peripherals - * clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including - * the backup registers) are set to their reset values. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tickstart = 0; - uint32_t tmpreg0 = 0; - uint32_t tmpreg1 = 0; - uint32_t plli2sused = 0; - uint32_t pllsaiused = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - - /*----------------------------------- I2S configuration ----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) - { - /* Check the parameters */ - assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); - - /* Configure I2S Clock source */ - __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); - - /* Enable the PLLI2S when it's used as clock source for I2S */ - if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) - { - plli2sused = 1; - } - } - - /*------------------------------------ SAI1 configuration --------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) - { - /* Check the parameters */ - assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); - - /* Configure SAI1 Clock source */ - __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); - /* Enable the PLLI2S when it's used as clock source for SAI */ - if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) - { - plli2sused = 1; - } - /* Enable the PLLSAI when it's used as clock source for SAI */ - if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) - { - pllsaiused = 1; - } - } - - /*------------------------------------ SAI2 configuration --------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) - { - /* Check the parameters */ - assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); - - /* Configure SAI2 Clock source */ - __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); - - /* Enable the PLLI2S when it's used as clock source for SAI */ - if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) - { - plli2sused = 1; - } - /* Enable the PLLSAI when it's used as clock source for SAI */ - if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) - { - pllsaiused = 1; - } - } - - /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) - { - plli2sused = 1; - } - - /*------------------------------------ RTC configuration --------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) - { - /* Check for RTC Parameters used to output RTCCLK */ - assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - PWR->CR1 |= PWR_CR1_DBP; - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait for Backup domain Write protection disable */ - while((PWR->CR1 & PWR_CR1_DBP) == RESET) - { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Reset the Backup domain only if the RTC Clock source selection is modified */ - tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); - - if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) - { - /* Store the content of BDCR register before the reset of Backup Domain */ - tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); - - /* RTC Clock selection can be changed only if the Backup Domain is reset */ - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - /* Restore the Content of BDCR register */ - RCC->BDCR = tmpreg0; - - /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ - if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - } - - /*------------------------------------ TIM configuration --------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) - { - /* Check the parameters */ - assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); - - /* Configure Timer Prescaler */ - __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); - } - - /*-------------------------------------- I2C1 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); - - /* Configure the I2C1 clock source */ - __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); - } - - /*-------------------------------------- I2C2 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); - - /* Configure the I2C2 clock source */ - __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); - } - - /*-------------------------------------- I2C3 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); - - /* Configure the I2C3 clock source */ - __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); - } - - /*-------------------------------------- I2C4 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); - - /* Configure the I2C4 clock source */ - __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); - } - - /*-------------------------------------- USART1 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) - { - /* Check the parameters */ - assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); - - /* Configure the USART1 clock source */ - __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); - } - - /*-------------------------------------- USART2 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) - { - /* Check the parameters */ - assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); - - /* Configure the USART2 clock source */ - __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); - } - - /*-------------------------------------- USART3 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) - { - /* Check the parameters */ - assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); - - /* Configure the USART3 clock source */ - __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); - } - - /*-------------------------------------- UART4 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) - { - /* Check the parameters */ - assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); - - /* Configure the UART4 clock source */ - __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); - } - - /*-------------------------------------- UART5 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) - { - /* Check the parameters */ - assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); - - /* Configure the UART5 clock source */ - __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); - } - - /*-------------------------------------- USART6 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) - { - /* Check the parameters */ - assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); - - /* Configure the USART6 clock source */ - __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); - } - - /*-------------------------------------- UART7 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) - { - /* Check the parameters */ - assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); - - /* Configure the UART7 clock source */ - __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); - } - - /*-------------------------------------- UART8 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) - { - /* Check the parameters */ - assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); - - /* Configure the UART8 clock source */ - __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); - } - - /*--------------------------------------- CEC Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) - { - /* Check the parameters */ - assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); - - /* Configure the CEC clock source */ - __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); - } - - /*-------------------------------------- CK48 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) - { - /* Check the parameters */ - assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); - - /* Configure the CLK48 source */ - __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); - - /* Enable the PLLSAI when it's used as clock source for CK48 */ - if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) - { - pllsaiused = 1; - } - } - - /*-------------------------------------- LTDC Configuration -----------------------------------*/ -#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) - { - pllsaiused = 1; - } -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - - /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) - { - /* Check the parameters */ - assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); - - /* Configure the LTPIM1 clock source */ - __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); - } - - /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) - { - /* Check the parameters */ - assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); - - /* Configure the SDMMC1 clock source */ - __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); - } - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) - { - /* Check the parameters */ - assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); - - /* Configure the SDMMC2 clock source */ - __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); - } - - /*------------------------------------- DFSDM1 Configuration -------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) - { - /* Check the parameters */ - assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); - - /* Configure the DFSDM1 interface clock source */ - __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); - } - - /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) - { - /* Check the parameters */ - assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); - - /* Configure the DFSDM interface clock source */ - __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); - } -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - - /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ - /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */ - if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) - { - /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLI2S is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - /* check for common PLLI2S Parameters */ - assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); - - /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ - if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) - { - /* check for Parameters */ - assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - - /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ - tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)); - tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ - /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR); - } - - /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ - if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) - { - /* Check for PLLI2S Parameters */ - assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); - /* Check for PLLI2S/DIVQ parameters */ - assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); - - /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ - tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)); - tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ - /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ - /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); - } - - /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) - { - /* check for Parameters */ - assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); - - /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */ - tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); - tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ - /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1); - } - - /*----------------- In Case of PLLI2S is just selected -----------------*/ - if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) - { - /* Check for Parameters */ - assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); - assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); - - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ - /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); - } - - /* Enable the PLLI2S */ - __HAL_RCC_PLLI2S_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLI2S is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) - { - if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - } - - /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ - /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ - if(pllsaiused == 1) - { - /* Disable PLLSAI Clock */ - __HAL_RCC_PLLSAI_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI is disabled */ - while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - /* Check the PLLSAI division factors */ - assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); - - /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ - if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) - { - /* check for PLLSAIQ Parameter */ - assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); - /* check for PLLSAI/DIVQ Parameter */ - assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); - - /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ - tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)); - tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); - /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ - /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ - /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ - __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ - __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); - } - - /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ - /* In Case of PLLI2S is selected as source clock for CK48 */ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) - { - /* check for Parameters */ - assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); - /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ - tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); - tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); - - /* Configure the PLLSAI division factors */ - /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ - /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ - __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1); - } - -#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - /*---------------------------- LTDC configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) - { - assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); - assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); - - /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */ - tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); - tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)); - - /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ - /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ - /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ - __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR); - - /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ - __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); - } -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - - /* Enable PLLSAI Clock */ - __HAL_RCC_PLLSAI_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI is ready */ - while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal - * RCC configuration registers. - * @param PeriphClkInit: pointer to the configured RCC_PeriphCLKInitTypeDef structure - * @retval None - */ -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tempreg = 0; - - /* Set all possible values for the extended clock type parameter------------*/ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ - RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ - RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ - RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\ - RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ - RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ - RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ - RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ - RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ - RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ - RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2 |\ - RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1_AUDIO; -#else - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ - RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ - RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ - RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\ - RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ - RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ - RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ - RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ - RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ - RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ - RCC_PERIPHCLK_CLK48; -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - - /* Get the PLLI2S Clock configuration -----------------------------------------------*/ - PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); - PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)); - PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); - PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); - - /* Get the PLLSAI Clock configuration -----------------------------------------------*/ - PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)); - PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)); - PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); - PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); - - /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/ - PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLI2SDIVQ)); - PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVQ)); - PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVR)); - - /* Get the SAI1 clock configuration ----------------------------------------------*/ - PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); - - /* Get the SAI2 clock configuration ----------------------------------------------*/ - PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); - - /* Get the I2S clock configuration ------------------------------------------*/ - PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE(); - - /* Get the I2C1 clock configuration ------------------------------------------*/ - PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); - - /* Get the I2C2 clock configuration ------------------------------------------*/ - PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); - - /* Get the I2C3 clock configuration ------------------------------------------*/ - PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); - - /* Get the I2C4 clock configuration ------------------------------------------*/ - PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); - - /* Get the USART1 clock configuration ------------------------------------------*/ - PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); - - /* Get the USART2 clock configuration ------------------------------------------*/ - PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); - - /* Get the USART3 clock configuration ------------------------------------------*/ - PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); - - /* Get the UART4 clock configuration ------------------------------------------*/ - PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); - - /* Get the UART5 clock configuration ------------------------------------------*/ - PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); - - /* Get the USART6 clock configuration ------------------------------------------*/ - PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); - - /* Get the UART7 clock configuration ------------------------------------------*/ - PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE(); - - /* Get the UART8 clock configuration ------------------------------------------*/ - PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE(); - - /* Get the LPTIM1 clock configuration ------------------------------------------*/ - PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); - - /* Get the CEC clock configuration -----------------------------------------------*/ - PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); - - /* Get the CK48 clock configuration -----------------------------------------------*/ - PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); - - /* Get the SDMMC1 clock configuration -----------------------------------------------*/ - PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - /* Get the SDMMC2 clock configuration -----------------------------------------------*/ - PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE(); - - /* Get the DFSDM clock configuration -----------------------------------------------*/ - PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); - - /* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/ - PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - - /* Get the RTC Clock configuration -----------------------------------------------*/ - tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); - PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - - /* Get the TIM Prescaler configuration --------------------------------------------*/ - if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET) - { - PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; - } - else - { - PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; - } -} - -/** - * @brief Return the peripheral clock frequency for a given peripheral(SAI..) - * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk: Peripheral clock identifier - * This parameter can be one of the following values: - * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock - * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock - * @retval Frequency in KHz - */ -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) -{ - uint32_t tmpreg = 0; - /* This variable is used to store the SAI clock frequency (value in Hz) */ - uint32_t frequency = 0; - /* This variable is used to store the VCO Input (value in Hz) */ - uint32_t vcoinput = 0; - /* This variable is used to store the SAI clock source */ - uint32_t saiclocksource = 0; - - if (PeriphClk == RCC_PERIPHCLK_SAI1) - { - saiclocksource = RCC->DCKCFGR1; - saiclocksource &= RCC_DCKCFGR1_SAI1SEL; - switch (saiclocksource) - { - case 0: /* PLLSAI is the clock source for SAI1 */ - { - /* Configure the PLLSAI division factor */ - /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) - { - /* In Case the PLL Source is HSI (Internal Clock) */ - vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - else - { - /* In Case the PLL Source is HSE (External Clock) */ - vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); - } - /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ - /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ - tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24; - frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ - tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1); - frequency = frequency/(tmpreg); - break; - } - case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */ - { - /* Configure the PLLI2S division factor */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) - { - /* In Case the PLL Source is HSI (Internal Clock) */ - vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - else - { - /* In Case the PLL Source is HSE (External Clock) */ - vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); - } - - /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ - /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ - tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24; - frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); - frequency = frequency/(tmpreg); - break; - } - case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */ - { - frequency = EXTERNAL_CLOCK_VALUE; - break; - } -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/ - { - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) - { - /* In Case the main PLL Source is HSI */ - frequency = HSI_VALUE; - } - else - { - /* In Case the main PLL Source is HSE */ - frequency = HSE_VALUE; - } - break; - } -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - default : - { - break; - } - } - } - - if (PeriphClk == RCC_PERIPHCLK_SAI2) - { - saiclocksource = RCC->DCKCFGR1; - saiclocksource &= RCC_DCKCFGR1_SAI2SEL; - switch (saiclocksource) - { - case 0: /* PLLSAI is the clock source for SAI*/ - { - /* Configure the PLLSAI division factor */ - /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) - { - /* In Case the PLL Source is HSI (Internal Clock) */ - vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - else - { - /* In Case the PLL Source is HSE (External Clock) */ - vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); - } - /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ - /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ - tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24; - frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ - tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1); - frequency = frequency/(tmpreg); - break; - } - case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */ - { - /* Configure the PLLI2S division factor */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) - { - /* In Case the PLL Source is HSI (Internal Clock) */ - vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - else - { - /* In Case the PLL Source is HSE (External Clock) */ - vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); - } - - /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ - /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ - tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24; - frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); - frequency = frequency/(tmpreg); - break; - } - case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */ - { - frequency = EXTERNAL_CLOCK_VALUE; - break; - } -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */ - { - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) - { - /* In Case the main PLL Source is HSI */ - frequency = HSI_VALUE; - } - else - { - /* In Case the main PLL Source is HSE */ - frequency = HSE_VALUE; - } - break; - } -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - default : - { - break; - } - } - } - - return frequency; -} - -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -/** - * @brief Initializes the RCC Oscillators according to the specified parameters in the - * RCC_OscInitTypeDef. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC Oscillators. - * @note The PLL is not disabled when used as system clock. - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not - * supported by this function. User should request a transition to LSE Off - * first and then LSE On or LSE Bypass. - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this function. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - - /*------------------------------- HSE Configuration ------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - { - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); - /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) - || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) - { - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - { - return HAL_ERROR; - } - } - else - { - /* Set the new HSE configuration ---------------------------------------*/ - __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - - /* Check the HSE State */ - if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSE is bypassed or disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*----------------------------- HSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); - assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) - || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) - { - /* When HSI is used as system clock it will not disabled */ - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - { - return HAL_ERROR; - } - /* Otherwise, just the calibration is allowed */ - else - { - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - } - else - { - /* Check the HSI State */ - if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) - { - /* Enable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - else - { - /* Disable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*------------------------------ LSI Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - { - /* Check the parameters */ - assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); - - /* Check the LSI State */ - if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) - { - /* Enable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /*------------------------------ LSE Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - { - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - PWR->CR1 |= PWR_CR1_DBP; - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while((PWR->CR1 & PWR_CR1_DBP) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Set the new LSE configuration -----------------------------------------*/ - __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - /* Check the LSE State */ - if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /*-------------------------------- PLL Configuration -----------------------*/ - /* Check the parameters */ - assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); - if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - { - /* Check if the PLL is used as system clock or not */ - if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - { - /* Check the parameters */ - assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); - assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); - assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); - assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); - assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); - assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); - - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Configure the main PLL clock source, multiplication and division factors. */ - __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - RCC_OscInitStruct->PLL.PLLM, - RCC_OscInitStruct->PLL.PLLN, - RCC_OscInitStruct->PLL.PLLP, - RCC_OscInitStruct->PLL.PLLQ, - RCC_OscInitStruct->PLL.PLLR); - - /* Enable the main PLL. */ - __HAL_RCC_PLL_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - else - { - return HAL_ERROR; - } - } - return HAL_OK; -} -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RCC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rng.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rng.c deleted file mode 100644 index e19e68d..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rng.c +++ /dev/null @@ -1,522 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_rng.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief RNG HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Random Number Generator (RNG) peripheral: - * + Initialization/de-initialization functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The RNG HAL driver can be used as follows: - - (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro - in HAL_RNG_MspInit(). - (#) Activate the RNG peripheral using HAL_RNG_Init() function. - (#) Wait until the 32 bit Random Number Generator contains a valid - random data using (polling/interrupt) mode. - (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup RNG - * @{ - */ - -#ifdef HAL_RNG_MODULE_ENABLED - -/* Private types -------------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup RNG_Private_Constants - * @{ - */ -#define RNG_TIMEOUT_VALUE 2 -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/* Private functions prototypes ----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup RNG_Exported_Functions - * @{ - */ - -/** @addtogroup RNG_Exported_Functions_Group1 - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the RNG according to the specified parameters - in the RNG_InitTypeDef and create the associated handle - (+) DeInitialize the RNG peripheral - (+) Initialize the RNG MSP - (+) DeInitialize RNG MSP - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the RNG peripheral and creates the associated handle. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) -{ - /* Check the RNG handle allocation */ - if(hrng == NULL) - { - return HAL_ERROR; - } - - __HAL_LOCK(hrng); - - if(hrng->State == HAL_RNG_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hrng->Lock = HAL_UNLOCKED; - - /* Init the low level hardware */ - HAL_RNG_MspInit(hrng); - } - - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_BUSY; - - /* Enable the RNG Peripheral */ - __HAL_RNG_ENABLE(hrng); - - /* Initialize the RNG state */ - hrng->State = HAL_RNG_STATE_READY; - - __HAL_UNLOCK(hrng); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief DeInitializes the RNG peripheral. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) -{ - /* Check the RNG handle allocation */ - if(hrng == NULL) - { - return HAL_ERROR; - } - /* Disable the RNG Peripheral */ - CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN); - - /* Clear RNG interrupt status flags */ - CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS); - - /* DeInit the low level hardware */ - HAL_RNG_MspDeInit(hrng); - - /* Update the RNG state */ - hrng->State = HAL_RNG_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hrng); - - /* Return the function status */ - return HAL_OK; -} - -/** - * @brief Initializes the RNG MSP. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval None - */ -__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrng); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_RNG_MspInit must be implemented in the user file. - */ -} - -/** - * @brief DeInitializes the RNG MSP. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval None - */ -__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrng); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_RNG_MspDeInit must be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @addtogroup RNG_Exported_Functions_Group2 - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Get the 32 bit Random number - (+) Get the 32 bit Random number with interrupt enabled - (+) Handle RNG interrupt request - -@endverbatim - * @{ - */ - -/** - * @brief Generates a 32-bit random number. - * @note Each time the random number data is read the RNG_FLAG_DRDY flag - * is automatically cleared. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @param random32bit: pointer to generated random number variable if successful. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit) -{ - uint32_t tickstart = 0; - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(hrng); - - /* Check RNG peripheral state */ - if(hrng->State == HAL_RNG_STATE_READY) - { - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_BUSY; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check if data register contains valid random data */ - while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE) - { - hrng->State = HAL_RNG_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - - return HAL_TIMEOUT; - } - } - - /* Get a 32bit Random number */ - hrng->RandomNumber = hrng->Instance->DR; - *random32bit = hrng->RandomNumber; - - hrng->State = HAL_RNG_STATE_READY; - } - else - { - status = HAL_ERROR; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - - return status; -} - -/** - * @brief Generates a 32-bit random number in interrupt mode. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(hrng); - - /* Check RNG peripheral state */ - if(hrng->State == HAL_RNG_STATE_READY) - { - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_BUSY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - - /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ - __HAL_RNG_ENABLE_IT(hrng); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Handles RNG interrupt request. - * @note In the case of a clock error, the RNG is no more able to generate - * random numbers because the PLL48CLK clock is not correct. User has - * to check that the clock controller is correctly configured to provide - * the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). - * The clock error has no impact on the previously generated - * random numbers, and the RNG_DR register contents can be used. - * @note In the case of a seed error, the generation of random numbers is - * interrupted as long as the SECS bit is '1'. If a number is - * available in the RNG_DR register, it must not be used because it may - * not have enough entropy. In this case, it is recommended to clear the - * SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable - * the RNG peripheral to reinitialize and restart the RNG. - * @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS - * or CEIS are set. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval None - - */ -void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) -{ - /* RNG clock error interrupt occurred */ - if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) || (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)) - { - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_ERROR; - - HAL_RNG_ErrorCallback(hrng); - - /* Clear the clock error flag */ - __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI); - - } - - /* Check RNG data ready interrupt occurred */ - if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET) - { - /* Generate random number once, so disable the IT */ - __HAL_RNG_DISABLE_IT(hrng); - - /* Get the 32bit Random number (DRDY flag automatically cleared) */ - hrng->RandomNumber = hrng->Instance->DR; - - if(hrng->State != HAL_RNG_STATE_ERROR) - { - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_READY; - - /* Data Ready callback */ - HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber); - } - } -} - -/** - * @brief Returns generated random number in polling mode (Obsolete) - * Use HAL_RNG_GenerateRandomNumber() API instead. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval Random value - */ -uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng) -{ - if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK) - { - return hrng->RandomNumber; - } - else - { - return 0; - } -} - -/** - * @brief Returns a 32-bit random number with interrupt enabled (Obsolete), - * Use HAL_RNG_GenerateRandomNumber_IT() API instead. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval 32-bit random number - */ -uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng) -{ - uint32_t random32bit = 0; - - /* Process locked */ - __HAL_LOCK(hrng); - - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_BUSY; - - /* Get a 32bit Random number */ - random32bit = hrng->Instance->DR; - - /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ - __HAL_RNG_ENABLE_IT(hrng); - - /* Return the 32 bit random number */ - return random32bit; -} - -/** - * @brief Read latest generated random number. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval random value - */ -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng) -{ - return(hrng->RandomNumber); -} - -/** - * @brief Data Ready callback in non-blocking mode. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @param random32bit: generated random number. - * @retval None - */ -__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrng); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_RNG_ReadyDataCallback must be implemented in the user file. - */ -} - -/** - * @brief RNG error callbacks. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval None - */ -__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrng); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_RNG_ErrorCallback must be implemented in the user file. - */ -} -/** - * @} - */ - - -/** @addtogroup RNG_Exported_Functions_Group3 - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the RNG state. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval HAL state - */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) -{ - return hrng->State; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RNG_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c deleted file mode 100644 index c66ca8b..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c +++ /dev/null @@ -1,1567 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_rtc.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief RTC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Real Time Clock (RTC) peripheral: - * + Initialization and de-initialization functions - * + RTC Time and Date functions - * + RTC Alarm functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### Backup Domain Operating Condition ##### - ============================================================================== - [..] The real-time clock (RTC), the RTC backup registers, and the backup - SRAM (BKP SRAM) can be powered from the VBAT voltage when the main - VDD supply is powered off. - To retain the content of the RTC backup registers, backup SRAM, and supply - the RTC when VDD is turned off, VBAT pin can be connected to an optional - standby voltage supplied by a battery or by another source. - - [..] To allow the RTC operating even when the main digital supply (VDD) is turned - off, the VBAT pin powers the following blocks: - (#) The RTC - (#) The LSE oscillator - (#) The backup SRAM when the low power backup regulator is enabled - (#) PC13 to PC15 I/Os, plus PI8 I/O (when available) - - [..] When the backup domain is supplied by VDD (analog switch connected to VDD), - the following pins are available: - (#) PC14 and PC15 can be used as either GPIO or LSE pins - (#) PC13 can be used as a GPIO or as the RTC_AF1 pin - (#) PI8 can be used as a GPIO or as the RTC_AF2 pin - - [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT - because VDD is not present), the following pins are available: - (#) PC14 and PC15 can be used as LSE pins only - (#) PC13 can be used as the RTC_AF1 pin - (#) PI8 can be used as the RTC_AF2 pin - (#) PC1 can be used as the RTC_AF3 pin - - ##### Backup Domain Reset ##### - ================================================================== - [..] The backup domain reset sets all RTC registers and the RCC_BDCR register - to their reset values. The BKPSRAM is not affected by this reset. The only - way to reset the BKPSRAM is through the Flash interface by requesting - a protection level change from 1 to 0. - [..] A backup domain reset is generated when one of the following events occurs: - (#) Software reset, triggered by setting the BDRST bit in the - RCC Backup domain control register (RCC_BDCR). - (#) VDD or VBAT power on, if both supplies have previously been powered off. - - ##### Backup Domain Access ##### - ================================================================== - [..] After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted write - accesses. - [..] To enable access to the RTC Domain and RTC registers, proceed as follows: - (+) Enable the Power Controller (PWR) APB1 interface clock using the - __HAL_RCC_PWR_CLK_ENABLE() function. - (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. - (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function. - (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function. - - - ##### How to use this driver ##### - ================================================================== - [..] - (+) Enable the RTC domain access (see description in the section above). - (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour - format using the HAL_RTC_Init() function. - - *** Time and Date configuration *** - =================================== - [..] - (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() - and HAL_RTC_SetDate() functions. - (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. - - *** Alarm configuration *** - =========================== - [..] - (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. - You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function. - (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. - - ##### RTC and low power modes ##### - ================================================================== - [..] The MCU can be woken up from a low power mode by an RTC alternate - function. - [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), - RTC wakeup, RTC tamper event detection and RTC time stamp event detection. - These RTC alternate functions can wake up the system from the Stop and - Standby low power modes. - [..] The system can also wake up from low power modes without depending - on an external interrupt (Auto-wakeup mode), by using the RTC alarm - or the RTC wakeup events. - [..] The RTC provides a programmable time base for waking up from the - Stop or Standby mode at regular intervals. - Wakeup from STOP and STANDBY modes is possible only when the RTC clock source - is LSE or LSI. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup RTC RTC - * @brief RTC HAL module driver - * @{ - */ - -#ifdef HAL_RTC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RTC_Exported_Functions RTC Exported Functions - * @{ - */ - -/** @defgroup RTC_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to initialize and configure the - RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable - RTC registers Write protection, enter and exit the RTC initialization mode, - RTC registers synchronization check and reference clock detection enable. - (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. - It is split into 2 programmable prescalers to minimize power consumption. - (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler. - (++) When both prescalers are used, it is recommended to configure the - asynchronous prescaler to a high value to minimize power consumption. - (#) All RTC registers are Write protected. Writing to the RTC registers - is enabled by writing a key into the Write Protection register, RTC_WPR. - (#) To configure the RTC Calendar, user application should enter - initialization mode. In this mode, the calendar counter is stopped - and its value can be updated. When the initialization sequence is - complete, the calendar restarts counting after 4 RTCCLK cycles. - (#) To read the calendar through the shadow registers after Calendar - initialization, calendar update or after wakeup from low power modes - the software must first clear the RSF flag. The software must then - wait until it is set again before reading the calendar, which means - that the calendar registers have been correctly copied into the - RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function - implements the above software sequence (RSF clear and RSF check). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the RTC peripheral - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) -{ - /* Check the RTC peripheral state */ - if(hrtc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); - assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); - assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); - assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); - assert_param (IS_RTC_OUTPUT(hrtc->Init.OutPut)); - assert_param (IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); - assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); - - if(hrtc->State == HAL_RTC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hrtc->Lock = HAL_UNLOCKED; - /* Initialize RTC MSP */ - HAL_RTC_MspInit(hrtc); - } - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - else - { - /* Clear RTC_CR FMT, OSEL and POL Bits */ - hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); - /* Set RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); - - /* Configure the RTC PRER */ - hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); - hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - - hrtc->Instance->OR &= (uint32_t)~RTC_OR_ALARMTYPE; - hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; - } -} - -/** - * @brief DeInitializes the RTC peripheral - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @note This function doesn't reset the RTC Backup Data registers. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - else - { - /* Reset TR, DR and CR registers */ - hrtc->Instance->TR = (uint32_t)0x00000000; - hrtc->Instance->DR = (uint32_t)0x00002101; - /* Reset All CR bits except CR[2:0] */ - hrtc->Instance->CR &= (uint32_t)0x00000007; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till WUTWF flag is set and if Time out is reached exit */ - while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - - /* Reset all RTC CR register bits */ - hrtc->Instance->CR &= (uint32_t)0x00000000; - hrtc->Instance->WUTR = (uint32_t)0x0000FFFF; - hrtc->Instance->PRER = (uint32_t)0x007F00FF; - hrtc->Instance->ALRMAR = (uint32_t)0x00000000; - hrtc->Instance->ALRMBR = (uint32_t)0x00000000; - hrtc->Instance->SHIFTR = (uint32_t)0x00000000; - hrtc->Instance->CALR = (uint32_t)0x00000000; - hrtc->Instance->ALRMASSR = (uint32_t)0x00000000; - hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000; - - /* Reset ISR register and exit initialization mode */ - hrtc->Instance->ISR = (uint32_t)0x00000000; - - /* Reset Tamper and alternate functions configuration register */ - hrtc->Instance->TAMPCR = 0x00000000; - - /* Reset Option register */ - hrtc->Instance->OR = 0x00000000; - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* De-Initialize RTC MSP */ - HAL_RTC_MspDeInit(hrtc); - - hrtc->State = HAL_RTC_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Initializes the RTC MSP. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the RTC MSP. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup RTC_Group2 RTC Time and Date functions - * @brief RTC Time and Date functions - * -@verbatim - =============================================================================== - ##### RTC Time and Date functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure Time and Date features - -@endverbatim - * @{ - */ - -/** - * @brief Sets RTC current time. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sTime: Pointer to Time structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); - assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if(Format == RTC_FORMAT_BIN) - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(sTime->Hours)); - assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); - } - else - { - sTime->TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(sTime->Hours)); - } - assert_param(IS_RTC_MINUTES(sTime->Minutes)); - assert_param(IS_RTC_SECONDS(sTime->Seconds)); - - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ - (((uint32_t)sTime->TimeFormat) << 16)); - } - else - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(sTime->Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); - } - else - { - sTime->TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); - } - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); - tmpreg = (((uint32_t)(sTime->Hours) << 16) | \ - ((uint32_t)(sTime->Minutes) << 8) | \ - ((uint32_t)sTime->Seconds) | \ - ((uint32_t)(sTime->TimeFormat) << 16)); - } - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - /* Set the RTC_TR register */ - hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - - /* Clear the bits to be configured */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK; - - /* Configure the RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - __HAL_UNLOCK(hrtc); - - return HAL_OK; - } -} - -/** - * @brief Gets RTC current time. - * @param hrtc: RTC handle - * @param sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned - * with input format (BIN or BCD), also SubSeconds field returning the - * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler - * factor to be used for second fraction ratio computation. - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds - * value in second fraction ratio with time unit following generic formula: - * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit - * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS - * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values - * in the higher-order calendar shadow registers to ensure consistency between the time and date values. - * Reading RTC current time locks the values in calendar shadow registers until Current date is read - * to ensure consistency between the time and date values. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Get subseconds values from the correspondent registers*/ - sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR); - - /* Get SecondFraction structure field from the corresponding register field*/ - sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S); - - /* Get the TR register */ - tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); - sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); - sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); - - /* Check the input parameters format */ - if(Format == RTC_FORMAT_BIN) - { - /* Convert the time structure parameters to Binary format */ - sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); - sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes); - sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); - } - - return HAL_OK; -} - -/** - * @brief Sets RTC current date. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sDate: Pointer to date structure - * @param Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) -{ - uint32_t datetmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) - { - sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); - } - - assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); - - if(Format == RTC_FORMAT_BIN) - { - assert_param(IS_RTC_YEAR(sDate->Year)); - assert_param(IS_RTC_MONTH(sDate->Month)); - assert_param(IS_RTC_DATE(sDate->Date)); - - datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ - ((uint32_t)sDate->WeekDay << 13)); - } - else - { - assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); - datetmpreg = RTC_Bcd2ToByte(sDate->Month); - assert_param(IS_RTC_MONTH(datetmpreg)); - datetmpreg = RTC_Bcd2ToByte(sDate->Date); - assert_param(IS_RTC_DATE(datetmpreg)); - - datetmpreg = ((((uint32_t)sDate->Year) << 16) | \ - (((uint32_t)sDate->Month) << 8) | \ - ((uint32_t)sDate->Date) | \ - (((uint32_t)sDate->WeekDay) << 13)); - } - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - /* Set the RTC_DR register */ - hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY ; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; - } -} - -/** - * @brief Gets RTC current date. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sDate: Pointer to Date structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values - * in the higher-order calendar shadow registers to ensure consistency between the time and date values. - * Reading RTC current time locks the values in calendar shadow registers until Current date is read. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) -{ - uint32_t datetmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Get the DR register */ - datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); - sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); - sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU)); - sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if(Format == RTC_FORMAT_BIN) - { - /* Convert the date structure parameters to Binary format */ - sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); - sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month); - sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); - } - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTC_Group3 RTC Alarm functions - * @brief RTC Alarm functions - * -@verbatim - =============================================================================== - ##### RTC Alarm functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure Alarm feature - -@endverbatim - * @{ - */ -/** - * @brief Sets the specified RTC Alarm. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) -{ - uint32_t tickstart = 0; - uint32_t tmpreg = 0, subsecondtmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_ALARM(sAlarm->Alarm)); - assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); - assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); - assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if(Format == RTC_FORMAT_BIN) - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); - } - assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); - assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); - } - - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } - else - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); - } - else - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); - } - - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } - - /* Configure the Alarm A or Alarm B Sub Second registers */ - subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the Alarm register */ - if(sAlarm->Alarm == RTC_ALARM_A) - { - /* Disable the Alarm A interrupt */ - __HAL_RTC_ALARMA_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMAR = (uint32_t)tmpreg; - /* Configure the Alarm A Sub Second register */ - hrtc->Instance->ALRMASSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMA_ENABLE(hrtc); - } - else - { - /* Disable the Alarm B interrupt */ - __HAL_RTC_ALARMB_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMBR = (uint32_t)tmpreg; - /* Configure the Alarm B Sub Second register */ - hrtc->Instance->ALRMBSSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMB_ENABLE(hrtc); - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Sets the specified RTC Alarm with Interrupt - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format - * @note The Alarm register can only be written when the corresponding Alarm - * is disabled (Use the HAL_RTC_DeactivateAlarm()). - * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) -{ - uint32_t tickstart = 0; - uint32_t tmpreg = 0, subsecondtmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_ALARM(sAlarm->Alarm)); - assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); - assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); - assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if(Format == RTC_FORMAT_BIN) - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); - } - assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); - assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); - } - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } - else - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); - } - else - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); - } - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } - /* Configure the Alarm A or Alarm B Sub Second registers */ - subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the Alarm register */ - if(sAlarm->Alarm == RTC_ALARM_A) - { - /* Disable the Alarm A interrupt */ - __HAL_RTC_ALARMA_DISABLE(hrtc); - - /* Clear flag alarm A */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMAR = (uint32_t)tmpreg; - /* Configure the Alarm A Sub Second register */ - hrtc->Instance->ALRMASSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMA_ENABLE(hrtc); - /* Configure the Alarm interrupt */ - __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA); - } - else - { - /* Disable the Alarm B interrupt */ - __HAL_RTC_ALARMB_DISABLE(hrtc); - - /* Clear flag alarm B */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMBR = (uint32_t)tmpreg; - /* Configure the Alarm B Sub Second register */ - hrtc->Instance->ALRMBSSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMB_ENABLE(hrtc); - /* Configure the Alarm interrupt */ - __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB); - } - - /* RTC Alarm Interrupt Configuration: EXTI configuration */ - __HAL_RTC_ALARM_EXTI_ENABLE_IT(); - - EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactive the specified RTC Alarm - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Alarm: Specifies the Alarm. - * This parameter can be one of the following values: - * @arg RTC_ALARM_A: AlarmA - * @arg RTC_ALARM_B: AlarmB - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_ALARM(Alarm)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - if(Alarm == RTC_ALARM_A) - { - /* AlarmA */ - __HAL_RTC_ALARMA_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - else - { - /* AlarmB */ - __HAL_RTC_ALARMB_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Gets the RTC Alarm value and masks. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sAlarm: Pointer to Date structure - * @param Alarm: Specifies the Alarm. - * This parameter can be one of the following values: - * @arg RTC_ALARM_A: AlarmA - * @arg RTC_ALARM_B: AlarmB - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) -{ - uint32_t tmpreg = 0, subsecondtmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_ALARM(Alarm)); - - if(Alarm == RTC_ALARM_A) - { - /* AlarmA */ - sAlarm->Alarm = RTC_ALARM_A; - - tmpreg = (uint32_t)(hrtc->Instance->ALRMAR); - subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS); - } - else - { - sAlarm->Alarm = RTC_ALARM_B; - - tmpreg = (uint32_t)(hrtc->Instance->ALRMBR); - subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS); - } - - /* Fill the structure with the read parameters */ - sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16); - sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8); - sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); - sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); - sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; - sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); - sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); - sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); - - if(Format == RTC_FORMAT_BIN) - { - sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); - sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); - sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds); - sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - } - - return HAL_OK; -} - -/** - * @brief This function handles Alarm interrupt request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) -{ - if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA)) - { - /* Get the status of the Interrupt */ - if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET) - { - /* AlarmA callback */ - HAL_RTC_AlarmAEventCallback(hrtc); - - /* Clear the Alarm interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF); - } - } - - if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB)) - { - /* Get the status of the Interrupt */ - if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET) - { - /* AlarmB callback */ - HAL_RTCEx_AlarmBEventCallback(hrtc); - - /* Clear the Alarm interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF); - } - } - - /* Clear the EXTI's line Flag for RTC Alarm */ - __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -/** - * @brief Alarm A callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_AlarmAEventCallback could be implemented in the user file - */ -} - -/** - * @brief This function handles AlarmA Polling request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Alarm interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTC_Group4 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Wait for RTC Time and Date Synchronization - -@endverbatim - * @{ - */ - -/** - * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are - * synchronized with RTC APB clock. - * @note The RTC Resynchronization mode is write protected, use the - * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @note To read the calendar through the shadow registers after Calendar - * initialization, calendar update or after wakeup from low power modes - * the software must first clear the RSF flag. - * The software must then wait until it is set again before reading - * the calendar, which means that the calendar registers have been - * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) -{ - uint32_t tickstart = 0; - - /* Clear RSF flag */ - hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the registers to be synchronised */ - while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTC_Group5 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Get RTC state - -@endverbatim - * @{ - */ -/** - * @brief Returns the RTC state. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL state - */ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) -{ - return hrtc->State; -} - -/** - * @} - */ - -/** - * @brief Enters the RTC Initialization mode. - * @note The RTC Initialization mode is write protected, use the - * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) -{ - uint32_t tickstart = 0; - - /* Check if the Initialization mode is set */ - if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - /* Set the Initialization mode */ - hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till RTC is in INIT state and if Time out is reached exit */ - while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - return HAL_OK; -} - - -/** - * @brief Converts a 2 digit decimal to BCD format. - * @param Value: Byte to be converted - * @retval Converted byte - */ -uint8_t RTC_ByteToBcd2(uint8_t Value) -{ - uint32_t bcdhigh = 0; - - while(Value >= 10) - { - bcdhigh++; - Value -= 10; - } - - return ((uint8_t)(bcdhigh << 4) | Value); -} - -/** - * @brief Converts from 2 digit BCD to Binary. - * @param Value: BCD value to be converted - * @retval Converted word - */ -uint8_t RTC_Bcd2ToByte(uint8_t Value) -{ - uint32_t tmp = 0; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (Value & (uint8_t)0x0F)); -} - -/** - * @} - */ - -#endif /* HAL_RTC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c deleted file mode 100644 index 491ee9d..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c +++ /dev/null @@ -1,1831 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_rtc_ex.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief RTC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Real Time Clock (RTC) Extension peripheral: - * + RTC Time Stamp functions - * + RTC Tamper functions - * + RTC Wake-up functions - * + Extension Control functions - * + Extension RTC features functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (+) Enable the RTC domain access. - (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour - format using the HAL_RTC_Init() function. - - *** RTC Wakeup configuration *** - ================================ - [..] - (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer() - function. You can also configure the RTC Wakeup timer in interrupt mode - using the HAL_RTC_SetWakeUpTimer_IT() function. - (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer() - function. - - *** TimeStamp configuration *** - =============================== - [..] - (+) Enables the RTC TimeStamp using the HAL_RTC_SetTimeStamp() function. - You can also configure the RTC TimeStamp with interrupt mode using the - HAL_RTC_SetTimeStamp_IT() function. - (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp() - function. - - *** Internal TimeStamp configuration *** - =============================== - [..] - (+) Enables the RTC internal TimeStamp using the HAL_RTC_SetInternalTimeStamp() function. - (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp() - function. - - *** Tamper configuration *** - ============================ - [..] - (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge - or Level according to the Tamper filter (if equal to 0 Edge else Level) - value, sampling frequency, NoErase, MaskFlag, precharge or discharge and - Pull-UP using the HAL_RTC_SetTamper() function. You can configure RTC Tamper - with interrupt mode using HAL_RTC_SetTamper_IT() function. - (+) The default configuration of the Tamper erases the backup registers. To avoid - erase, enable the NoErase field on the RTC_TAMPCR register. - - *** Backup Data Registers configuration *** - =========================================== - [..] - (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite() - function. - (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead() - function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup RTCEx RTCEx - * @brief RTC Extended HAL module driver - * @{ - */ - -#ifdef HAL_RTC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions - * @{ - */ - - -/** @defgroup RTCEx_Group1 RTC TimeStamp and Tamper functions - * @brief RTC TimeStamp and Tamper functions - * -@verbatim - =============================================================================== - ##### RTC TimeStamp and Tamper functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure TimeStamp feature - -@endverbatim - * @{ - */ - -/** - * @brief Sets TimeStamp. - * @note This API must be called before enabling the TimeStamp feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is - * activated. - * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the - * rising edge of the related pin. - * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the - * falling edge of the related pin. - * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. - * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin. - * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. - * @arg RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); - assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - tmpreg|= TimeStampEdge; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL; - hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin); - - /* Configure the Time Stamp TSEDGE and Enable bits */ - hrtc->Instance->CR = (uint32_t)tmpreg; - - __HAL_RTC_TIMESTAMP_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Sets TimeStamp with Interrupt. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @note This API must be called before enabling the TimeStamp feature. - * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is - * activated. - * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the - * rising edge of the related pin. - * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the - * falling edge of the related pin. - * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin. - * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin. - * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. - * @arg RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); - assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - tmpreg |= TimeStampEdge; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the Time Stamp TSEDGE and Enable bits */ - hrtc->Instance->CR = (uint32_t)tmpreg; - - hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL; - hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin); - - __HAL_RTC_TIMESTAMP_ENABLE(hrtc); - - /* Enable IT timestamp */ - __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS); - - /* RTC timestamp Interrupt Configuration: EXTI configuration */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); - - EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivates TimeStamp. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) -{ - uint32_t tmpreg = 0; - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS); - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - /* Configure the Time Stamp TSEDGE and Enable bits */ - hrtc->Instance->CR = (uint32_t)tmpreg; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Sets Internal TimeStamp. - * @note This API must be called before enabling the internal TimeStamp feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the internal Time Stamp Enable bits */ - __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivates internal TimeStamp. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the internal Time Stamp Enable bits */ - __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Gets the RTC TimeStamp value. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sTimeStamp: Pointer to Time structure - * @param sTimeStampDate: Pointer to Date structure - * @param Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * FORMAT_BIN: Binary data format - * FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format) -{ - uint32_t tmptime = 0, tmpdate = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Get the TimeStamp time and date registers values */ - tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK); - tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK); - - /* Fill the Time structure fields with the read parameters */ - sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); - sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); - sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); - sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR; - - /* Fill the Date structure fields with the read parameters */ - sTimeStampDate->Year = 0; - sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); - sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if(Format == RTC_FORMAT_BIN) - { - /* Convert the TimeStamp structure parameters to Binary format */ - sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); - sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes); - sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds); - - /* Convert the DateTimeStamp structure parameters to Binary format */ - sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month); - sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date); - sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay); - } - - /* Clear the TIMESTAMP Flag */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); - - return HAL_OK; -} - -/** - * @brief Sets Tamper - * @note By calling this API we disable the tamper interrupt for all tampers. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sTamper: Pointer to Tamper Structure. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(sTamper->Tamper)); - assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); - assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); - assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); - assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) - { - sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); - } - - if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) - { - sTamper->NoErase = 0; - if((sTamper->Tamper & RTC_TAMPER_1) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; - } - if((sTamper->Tamper & RTC_TAMPER_2) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; - } - if((sTamper->Tamper & RTC_TAMPER_3) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; - } - } - - if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) - { - sTamper->MaskFlag = 0; - if((sTamper->Tamper & RTC_TAMPER_1) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; - } - if((sTamper->Tamper & RTC_TAMPER_2) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; - } - if((sTamper->Tamper & RTC_TAMPER_3) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; - } - } - - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\ - (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\ - (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); - - hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\ - (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\ - (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\ - (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE |\ - (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\ - (uint32_t)RTC_TAMPCR_TAMP2MF | (uint32_t)RTC_TAMPCR_TAMP3MF); - - hrtc->Instance->TAMPCR |= tmpreg; - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Sets Tamper with interrupt. - * @note By calling this API we force the tamper interrupt for all tampers. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sTamper: Pointer to RTC Tamper. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(sTamper->Tamper)); - assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt)); - assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); - assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); - assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); - assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Configure the tamper trigger */ - if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) - { - sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); - } - - if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) - { - sTamper->NoErase = 0; - if((sTamper->Tamper & RTC_TAMPER_1) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; - } - if((sTamper->Tamper & RTC_TAMPER_2) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; - } - if((sTamper->Tamper & RTC_TAMPER_3) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; - } - } - - if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) - { - sTamper->MaskFlag = 0; - if((sTamper->Tamper & RTC_TAMPER_1) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; - } - if((sTamper->Tamper & RTC_TAMPER_2) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; - } - if((sTamper->Tamper & RTC_TAMPER_3) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; - } - } - - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\ - (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\ - (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); - - hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\ - (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\ - (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\ - (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE |\ - (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\ - (uint32_t)RTC_TAMPCR_TAMP2MF | (uint32_t)RTC_TAMPCR_TAMP3MF); - - hrtc->Instance->TAMPCR |= tmpreg; - - /* RTC Tamper Interrupt Configuration: EXTI configuration */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); - - EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivates Tamper. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Tamper: Selected tamper pin. - * This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) -{ - assert_param(IS_RTC_TAMPER(Tamper)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - -/* Disable the selected Tamper pin */ - hrtc->Instance->TAMPCR &= (uint32_t)~Tamper; - - if ((Tamper & RTC_TAMPER_1) != 0) - { - /* Disable the Tamper1 interrupt */ - hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1); - } - if ((Tamper & RTC_TAMPER_2) != 0) - { - /* Disable the Tamper2 interrupt */ - hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2); - } - if ((Tamper & RTC_TAMPER_3) != 0) - { - /* Disable the Tamper2 interrupt */ - hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3); - } - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief This function handles TimeStamp interrupt request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) -{ - if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS)) - { - /* Get the status of the Interrupt */ - if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET) - { - /* TIMESTAMP callback */ - HAL_RTCEx_TimeStampEventCallback(hrtc); - - /* Clear the TIMESTAMP interrupt pending bit */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF); - } - } - - /* Get the status of the Interrupt */ - if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== SET) - { - /* Get the TAMPER Interrupt enable bit and pending bit */ - if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \ - (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP1IE)) != (uint32_t)RESET)) - { - /* Tamper callback */ - HAL_RTCEx_Tamper1EventCallback(hrtc); - - /* Clear the Tamper interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); - } - } - - /* Get the status of the Interrupt */ - if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F)== SET) - { - /* Get the TAMPER Interrupt enable bit and pending bit */ - if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \ - (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP2IE)) != (uint32_t)RESET)) - { - /* Tamper callback */ - HAL_RTCEx_Tamper2EventCallback(hrtc); - - /* Clear the Tamper interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); - } - } - - /* Get the status of the Interrupt */ - if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F)== SET) - { - /* Get the TAMPER Interrupt enable bit and pending bit */ - if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \ - (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP3IE)) != (uint32_t)RESET)) - { - /* Tamper callback */ - HAL_RTCEx_Tamper3EventCallback(hrtc); - - /* Clear the Tamper interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); - } - } - - /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -/** - * @brief TimeStamp callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_TimeStampEventCallback could be implemented in the user file - */ -} - -/** - * @brief Tamper 1 callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_Tamper1EventCallback could be implemented in the user file - */ -} - -/** - * @brief Tamper 2 callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_Tamper2EventCallback could be implemented in the user file - */ -} - -/** - * @brief Tamper 3 callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file - */ -} - -/** - * @brief This function handles TimeStamp polling request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET) - { - /* Clear the TIMESTAMP OverRun Flag */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); - - /* Change TIMESTAMP state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @brief This function handles Tamper1 Polling. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @brief This function handles Tamper2 Polling. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @brief This function handles Tamper3 Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP3F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTCEx_Group2 RTC Wake-up functions - * @brief RTC Wake-up functions - * -@verbatim - =============================================================================== - ##### RTC Wake-up functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure Wake-up feature - -@endverbatim - * @{ - */ - -/** - * @brief Sets wake up timer. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); - assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ - if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET) - { - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - - /* Clear the Wakeup Timer clock source bits in CR register */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - hrtc->Instance->CR |= (uint32_t)WakeUpClock; - - /* Configure the Wakeup Timer counter */ - hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - - /* Enable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Sets wake up timer with interrupt - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); - assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ - if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET) - { - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - - /* Configure the Wakeup Timer counter */ - hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - - /* Clear the Wakeup Timer clock source bits in CR register */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - hrtc->Instance->CR |= (uint32_t)WakeUpClock; - - /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); - - EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT; - - /* Configure the Interrupt in the RTC_CR register */ - __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT); - - /* Enable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivates wake up timer counter. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Disable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Gets wake up timer counter. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval Counter value - */ -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) -{ - /* Get the counter value */ - return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); -} - -/** - * @brief This function handles Wake Up Timer interrupt request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) -{ - if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT)) - { - /* Get the status of the Interrupt */ - if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET) - { - /* WAKEUPTIMER callback */ - HAL_RTCEx_WakeUpTimerEventCallback(hrtc); - - /* Clear the WAKEUPTIMER interrupt pending bit */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - } - } - - /* Clear the EXTI's line Flag for RTC WakeUpTimer */ - __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -/** - * @brief Wake Up Timer callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_WakeUpTimerEventCallback could be implemented in the user file - */ -} - -/** - * @brief This function handles Wake Up Timer Polling. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - } - - /* Clear the WAKEUPTIMER Flag */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - - -/** @defgroup RTCEx_Group3 Extension Peripheral Control functions - * @brief Extension Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Extension Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Write a data in a specified RTC Backup data register - (+) Read a data in a specified RTC Backup data register - (+) Set the Coarse calibration parameters. - (+) Deactivate the Coarse calibration parameters - (+) Set the Smooth calibration parameters. - (+) Configure the Synchronization Shift Control Settings. - (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - (+) Enable the RTC reference clock detection. - (+) Disable the RTC reference clock detection. - (+) Enable the Bypass Shadow feature. - (+) Disable the Bypass Shadow feature. - -@endverbatim - * @{ - */ - -/** - * @brief Writes a data in a specified RTC Backup data register. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param BackupRegister: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @param Data: Data to be written in the specified RTC Backup data register. - * @retval None - */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(BackupRegister)); - - tmp = (uint32_t)&(hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4); - - /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; -} - -/** - * @brief Reads data from the specified RTC Backup data Register. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param BackupRegister: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @retval Read value - */ -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(BackupRegister)); - - tmp = (uint32_t)&(hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4); - - /* Read the specified register */ - return (*(__IO uint32_t *)tmp); -} - -/** - * @brief Sets the Smooth calibration parameters. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param SmoothCalibPeriod: Select the Smooth Calibration Period. - * This parameter can be can be one of the following values : - * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. - * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. - * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. - * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit. - * This parameter can be one of the following values: - * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulses every 2*11 pulses. - * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. - * @param SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits. - * This parameter can be one any value from 0 to 0x000001FF. - * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses - * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field - * SmouthCalibMinusPulsesValue must be equal to 0. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); - assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); - assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* check if a calibration is pending*/ - if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* check if a calibration is pending*/ - while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - - /* Configure the Smooth calibration settings */ - hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Configures the Synchronization Shift Control Settings. - * @note When REFCKON is set, firmware must not write to Shift control register. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param ShiftAdd1S: Select to add or not 1 second to the time calendar. - * This parameter can be one of the following values : - * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. - * @arg RTC_SHIFTADD1S_RESET: No effect. - * @param ShiftSubFS: Select the number of Second Fractions to substitute. - * This parameter can be one any value from 0 to 0x7FFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); - assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until the shift is completed*/ - while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Check if the reference clock detection is disabled */ - if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET) - { - /* Configure the Shift settings */ - hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S); - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } - } - else - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param CalibOutput: Select the Calibration output Selection . - * This parameter can be one of the following values: - * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. - * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput) -{ - /* Check the parameters */ - assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Clear flags before config */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL; - - /* Configure the RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)CalibOutput; - - __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Enables the RTC reference clock detection. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Disable the RTC reference clock detection. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Enables the Bypass Shadow feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set the BYPSHAD bit */ - hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Disables the Bypass Shadow feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Reset the BYPSHAD bit */ - hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @} - */ - - /** @defgroup RTCEx_Group4 Extended features functions - * @brief Extended features functions - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) RTC Alram B callback - (+) RTC Poll for Alarm B request - -@endverbatim - * @{ - */ - -/** - * @brief Alarm B callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_AlarmBEventCallback could be implemented in the user file - */ -} - -/** - * @brief This function handles AlarmB Polling request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Alarm Flag */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RTC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai.c deleted file mode 100644 index eb7496e..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai.c +++ /dev/null @@ -1,2184 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_sai.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief SAI HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Serial Audio Interface (SAI) peripheral: - * + Initialization/de-initialization functions - * + I/O operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - - [..] - The SAI HAL driver can be used as follows: - - (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai). - (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API: - (##) Enable the SAI interface clock. - (##) SAI pins configuration: - (+++) Enable the clock for the SAI GPIOs. - (+++) Configure these SAI pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT() - and HAL_SAI_Receive_IT() APIs): - (+++) Configure the SAI interrupt priority. - (+++) Enable the NVIC SAI IRQ handle. - - (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA() - and HAL_SAI_Receive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx stream. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx Stream. - (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the - DMA Tx/Rx Stream. - - (#) The initialization can be done by two ways - (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init(). - (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol(). - - [..] - (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt) - will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT() - inside the transmit and receive process. - [..] - (@) Make sure that either: - (+@) I2S PLL is configured or - (+@) SAI PLL is configured or - (+@) External clock source is configured after setting correctly - the define constant EXTERNAL_CLOCK_VALUE in the stm32f7xx_hal_conf.h file. - [..] - (@) In master Tx mode: enabling the audio block immediately generates the bit clock - for the external slaves even if there is no data in the FIFO, However FS signal - generation is conditioned by the presence of data in the FIFO. - - [..] - (@) In master Rx mode: enabling the audio block immediately generates the bit clock - and FS signal for the external slaves. - - [..] - (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior: - (+@) First bit Offset <= (SLOT size - Data size) - (+@) Data size <= SLOT size - (+@) Number of SLOT x SLOT size = Frame length - (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected. - - [..] - Three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_SAI_Transmit() - (+) Receive an amount of data in blocking mode using HAL_SAI_Receive() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT() - (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SAI_TxCpltCallback() - (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT() - (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SAI_RxCpltCallback() - (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_SAI_ErrorCallback() - - *** DMA mode IO operation *** - ============================= - [..] - (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA() - (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SAI_TxCpltCallback() - (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA() - (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SAI_RxCpltCallback() - (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_SAI_ErrorCallback() - (+) Pause the DMA Transfer using HAL_SAI_DMAPause() - (+) Resume the DMA Transfer using HAL_SAI_DMAResume() - (+) Stop the DMA Transfer using HAL_SAI_DMAStop() - - *** SAI HAL driver additional function list *** - =============================================== - [..] - Below the list the others API available SAI HAL driver : - - (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode - (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode - (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode - (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode - (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo. - (+) HAL_SAI_Abort(): Abort the current transfer - - *** SAI HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in SAI HAL driver : - - (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral - (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral - (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts - (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts - (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is - enabled or disabled - (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup SAI SAI - * @brief SAI HAL module driver - * @{ - */ - -#ifdef HAL_SAI_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ - -/** @defgroup SAI_Private_Typedefs SAI Private Typedefs - * @{ - */ -typedef enum { - SAI_MODE_DMA, - SAI_MODE_IT -}SAI_ModeTypedef; -/** - * @} - */ - -/* Private define ------------------------------------------------------------*/ - -/** @defgroup SAI_Private_Constants SAI Private Constants - * @{ - */ -#define SAI_FIFO_SIZE 8 -#define SAI_DEFAULT_TIMEOUT 4 /* 4ms */ -#define SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT) -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/** @defgroup SAI_Private_Functions SAI Private Functions - * @{ - */ -static void SAI_FillFifo(SAI_HandleTypeDef *hsai); -static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode); -static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); -static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); - -static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai); -static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai); -static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai); -static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai); -static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai); -static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai); -static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai); - -static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma); -static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma); -static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma); -static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void SAI_DMAError(DMA_HandleTypeDef *hdma); -static void SAI_DMAAbort(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup SAI_Exported_Functions SAI Exported Functions - * @{ - */ - -/** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - de-initialize the SAIx peripheral: - - (+) User must implement HAL_SAI_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - - (+) Call the function HAL_SAI_Init() to configure the selected device with - the selected configuration: - (++) Mode (Master/slave TX/RX) - (++) Protocol - (++) Data Size - (++) MCLK Output - (++) Audio frequency - (++) FIFO Threshold - (++) Frame Config - (++) Slot Config - - (+) Call the function HAL_SAI_DeInit() to restore the default configuration - of the selected SAI peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the structure FrameInit, SlotInit and the low part of - * Init according to the specified parameters and call the function - * HAL_SAI_Init to initialize the SAI block. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param protocol: one of the supported protocol @ref SAI_Protocol - * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize - * the configuration information for SAI module. - * @param nbslot: Number of slot. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol)); - assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize)); - - switch(protocol) - { - case SAI_I2S_STANDARD : - case SAI_I2S_MSBJUSTIFIED : - case SAI_I2S_LSBJUSTIFIED : - status = SAI_InitI2S(hsai, protocol, datasize, nbslot); - break; - case SAI_PCM_LONG : - case SAI_PCM_SHORT : - status = SAI_InitPCM(hsai, protocol, datasize, nbslot); - break; - default : - status = HAL_ERROR; - break; - } - - if(status == HAL_OK) - { - status = HAL_SAI_Init(hsai); - } - - return status; -} - -/** - * @brief Initialize the SAI according to the specified parameters. - * in the SAI_InitTypeDef structure and initialize the associated handle. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) -{ - uint32_t tmpregisterGCR = 0; - uint32_t ckstr_bits = 0; - uint32_t syncen_bits = 0; - - /* Check the SAI handle allocation */ - if(hsai == NULL) - { - return HAL_ERROR; - } - - /* check the instance */ - assert_param(IS_SAI_ALL_INSTANCE(hsai->Instance)); - - /* Check the SAI Block parameters */ - assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency)); - assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol)); - assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode)); - assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize)); - assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit)); - assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing)); - assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro)); - assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive)); - assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider)); - assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold)); - assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode)); - assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode)); - assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState)); - assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt)); - - /* Check the SAI Block Frame parameters */ - assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength)); - assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength)); - assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition)); - assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity)); - assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset)); - - /* Check the SAI Block Slot parameters */ - assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset)); - assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize)); - assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber)); - assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive)); - - if(hsai->State == HAL_SAI_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hsai->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_SAI_MspInit(hsai); - } - - hsai->State = HAL_SAI_STATE_BUSY; - - /* Disable the selected SAI peripheral */ - SAI_Disable(hsai); - - /* SAI Block Synchro Configuration -----------------------------------------*/ - /* This setting must be done with both audio block (A & B) disabled */ - switch(hsai->Init.SynchroExt) - { - case SAI_SYNCEXT_DISABLE : - tmpregisterGCR = 0; - break; - case SAI_SYNCEXT_OUTBLOCKA_ENABLE : - tmpregisterGCR = SAI_GCR_SYNCOUT_0; - break; - case SAI_SYNCEXT_OUTBLOCKB_ENABLE : - tmpregisterGCR = SAI_GCR_SYNCOUT_1; - break; - default: - break; - } - - switch(hsai->Init.Synchro) - { - case SAI_ASYNCHRONOUS : - { - syncen_bits = 0; - } - break; - case SAI_SYNCHRONOUS : - { - syncen_bits = SAI_xCR1_SYNCEN_0; - } - break; - case SAI_SYNCHRONOUS_EXT_SAI1 : - { - syncen_bits = SAI_xCR1_SYNCEN_1; - } - break; - case SAI_SYNCHRONOUS_EXT_SAI2 : - { - syncen_bits = SAI_xCR1_SYNCEN_1; - tmpregisterGCR |= SAI_GCR_SYNCIN_0; - } - break; - default: - break; - } - - if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) - { - SAI1->GCR = tmpregisterGCR; - } - else - { - SAI2->GCR = tmpregisterGCR; - } - - if(hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV) - { - uint32_t freq = 0; - uint32_t tmpval; - - if((hsai->Instance == SAI1_Block_A ) || (hsai->Instance == SAI1_Block_B )) - { - freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); - } - if((hsai->Instance == SAI2_Block_A ) || (hsai->Instance == SAI2_Block_B )) - { - freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2); - } - - /* Configure Master Clock using the following formula : - MCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2) with MCLK_x = 256 * FS - FS = SAI_CK_x / (MCKDIV[3:0] * 2) * 256 - MCKDIV[3:0] = SAI_CK_x / FS * 512 */ - /* (freq x 10) to keep Significant digits */ - tmpval = (freq * 10) / (hsai->Init.AudioFrequency * 2 * 256); - hsai->Init.Mckdiv = tmpval / 10; - - /* Round result to the nearest integer */ - if((tmpval % 10) > 8) - { - hsai->Init.Mckdiv+= 1; - } - } - - /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */ - if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) - { /* Transmit */ - ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0 : SAI_xCR1_CKSTR; - } - else - { /* Receive */ - ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0; - } - - /* SAI Block Configuration -------------------------------------------------*/ - /* SAI CR1 Configuration */ - hsai->Instance->CR1&=~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \ - SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\ - SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \ - SAI_xCR1_NODIV | SAI_xCR1_MCKDIV); - - hsai->Instance->CR1|=(hsai->Init.AudioMode | hsai->Init.Protocol | \ - hsai->Init.DataSize | hsai->Init.FirstBit | \ - ckstr_bits | syncen_bits | \ - hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \ - hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20)); - - /* SAI CR2 Configuration */ - hsai->Instance->CR2&= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL); - hsai->Instance->CR2|= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState); - - /* SAI Frame Configuration -----------------------------------------*/ - hsai->Instance->FRCR&=(~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \ - SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF)); - hsai->Instance->FRCR|=((hsai->FrameInit.FrameLength - 1) | - hsai->FrameInit.FSOffset | - hsai->FrameInit.FSDefinition | - hsai->FrameInit.FSPolarity | - ((hsai->FrameInit.ActiveFrameLength - 1) << 8)); - - /* SAI Block_x SLOT Configuration ------------------------------------------*/ - /* This register has no meaning in AC 97 and SPDIF audio protocol */ - hsai->Instance->SLOTR&= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \ - SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN )); - - hsai->Instance->SLOTR|= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize - | (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1) << 8); - - /* Initialize the error code */ - hsai->ErrorCode = HAL_SAI_ERROR_NONE; - - /* Initialize the SAI state */ - hsai->State= HAL_SAI_STATE_READY; - - /* Release Lock */ - __HAL_UNLOCK(hsai); - - return HAL_OK; -} - -/** - * @brief DeInitialize the SAI peripheral. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai) -{ - /* Check the SAI handle allocation */ - if(hsai == NULL) - { - return HAL_ERROR; - } - - hsai->State = HAL_SAI_STATE_BUSY; - - /* Disabled All interrupt and clear all the flag */ - hsai->Instance->IMR = 0; - hsai->Instance->CLRFR = 0xFFFFFFFFU; - - /* Disable the SAI */ - SAI_Disable(hsai); - - /* Flush the fifo */ - SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_SAI_MspDeInit(hsai); - - /* Initialize the error code */ - hsai->ErrorCode = HAL_SAI_ERROR_NONE; - - /* Initialize the SAI state */ - hsai->State = HAL_SAI_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hsai); - - return HAL_OK; -} - -/** - * @brief Initialize the SAI MSP. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -__weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsai); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SAI_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize the SAI MSP. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -__weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsai); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SAI_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup SAI_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to manage the SAI data - transfers. - - (+) There are two modes of transfer: - (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts - or DMA. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the - dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - - (+) Blocking mode functions are : - (++) HAL_SAI_Transmit() - (++) HAL_SAI_Receive() - (++) HAL_SAI_TransmitReceive() - - (+) Non Blocking mode functions with Interrupt are : - (++) HAL_SAI_Transmit_IT() - (++) HAL_SAI_Receive_IT() - (++) HAL_SAI_TransmitReceive_IT() - - (+) Non Blocking mode functions with DMA are : - (++) HAL_SAI_Transmit_DMA() - (++) HAL_SAI_Receive_DMA() - (++) HAL_SAI_TransmitReceive_DMA() - - (+) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_SAI_TxCpltCallback() - (++) HAL_SAI_RxCpltCallback() - (++) HAL_SAI_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Transmit an amount of data in blocking mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - if(hsai->State == HAL_SAI_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsai); - - hsai->XferSize = Size; - hsai->XferCount = Size; - hsai->pBuffPtr = pData; - hsai->State = HAL_SAI_STATE_BUSY_TX; - hsai->ErrorCode = HAL_SAI_ERROR_NONE; - - /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) - { - /* fill the fifo with data before to enabled the SAI */ - SAI_FillFifo(hsai); - /* Enable SAI peripheral */ - __HAL_SAI_ENABLE(hsai); - } - - while(hsai->XferCount > 0) - { - /* Write data if the FIFO is not full */ - if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) - { - if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) - { - hsai->Instance->DR = (*hsai->pBuffPtr++); - } - else if(hsai->Init.DataSize <= SAI_DATASIZE_16) - { - hsai->Instance->DR = *((uint16_t *)hsai->pBuffPtr); - hsai->pBuffPtr+= 2; - } - else - { - hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr); - hsai->pBuffPtr+= 4; - } - hsai->XferCount--; - } - else - { - /* Check for the Timeout */ - if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart) > Timeout))) - { - /* Update error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; - - /* Clear all the flags */ - hsai->Instance->CLRFR = 0xFFFFFFFFU; - - /* Disable SAI peripheral */ - SAI_Disable(hsai); - - /* Flush the fifo */ - SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); - - /* Change the SAI state */ - hsai->State = HAL_SAI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_ERROR; - } - } - } - - hsai->State = HAL_SAI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in blocking mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - if(hsai->State == HAL_SAI_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsai); - - hsai->pBuffPtr = pData; - hsai->XferSize = Size; - hsai->XferCount = Size; - hsai->State = HAL_SAI_STATE_BUSY_RX; - hsai->ErrorCode = HAL_SAI_ERROR_NONE; - - /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) - { - /* Enable SAI peripheral */ - __HAL_SAI_ENABLE(hsai); - } - - /* Receive data */ - while(hsai->XferCount > 0) - { - if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY) - { - if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) - { - (*hsai->pBuffPtr++) = hsai->Instance->DR; - } - else if(hsai->Init.DataSize <= SAI_DATASIZE_16) - { - *((uint16_t*)hsai->pBuffPtr) = hsai->Instance->DR; - hsai->pBuffPtr+= 2; - } - else - { - *((uint32_t*)hsai->pBuffPtr) = hsai->Instance->DR; - hsai->pBuffPtr+= 4; - } - hsai->XferCount--; - } - else - { - /* Check for the Timeout */ - if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart) > Timeout))) - { - /* Update error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; - - /* Clear all the flags */ - hsai->Instance->CLRFR = 0xFFFFFFFFU; - - /* Disable SAI peripheral */ - SAI_Disable(hsai); - - /* Flush the fifo */ - SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); - - /* Change the SAI state */ - hsai->State = HAL_SAI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_ERROR; - } - } - } - - hsai->State = HAL_SAI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit an amount of data in non-blocking mode with Interrupt. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) -{ - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(hsai->State == HAL_SAI_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsai); - - hsai->pBuffPtr = pData; - hsai->XferSize = Size; - hsai->XferCount = Size; - hsai->ErrorCode = HAL_SAI_ERROR_NONE; - hsai->State = HAL_SAI_STATE_BUSY_TX; - - if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) - { - hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit; - } - else if(hsai->Init.DataSize <= SAI_DATASIZE_16) - { - hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit; - } - else - { - hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit; - } - - /* Fill the fifo before starting the communication */ - SAI_FillFifo(hsai); - - /* Enable FRQ and OVRUDR interrupts */ - __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - - /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) - { - /* Enable SAI peripheral */ - __HAL_SAI_ENABLE(hsai); - } - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in non-blocking mode with Interrupt. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) -{ - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(hsai->State == HAL_SAI_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsai); - - hsai->pBuffPtr = pData; - hsai->XferSize = Size; - hsai->XferCount = Size; - hsai->ErrorCode = HAL_SAI_ERROR_NONE; - hsai->State = HAL_SAI_STATE_BUSY_RX; - - if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) - { - hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit; - } - else if(hsai->Init.DataSize <= SAI_DATASIZE_16) - { - hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit; - } - else - { - hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit; - } - - /* Enable TXE and OVRUDR interrupts */ - __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - - /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) - { - /* Enable SAI peripheral */ - __HAL_SAI_ENABLE(hsai); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Pause the audio stream playing from the Media. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai) -{ - /* Process Locked */ - __HAL_LOCK(hsai); - - /* Pause the audio file playing by disabling the SAI DMA requests */ - hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_OK; -} - -/** - * @brief Resume the audio stream playing from the Media. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai) -{ - /* Process Locked */ - __HAL_LOCK(hsai); - - /* Enable the SAI DMA requests */ - hsai->Instance->CR1 |= SAI_xCR1_DMAEN; - - /* If the SAI peripheral is still not enabled, enable it */ - if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) - { - /* Enable SAI peripheral */ - __HAL_SAI_ENABLE(hsai); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_OK; -} - -/** - * @brief Stop the audio stream playing from the Media. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) -{ - /* Process Locked */ - __HAL_LOCK(hsai); - - /* Disable the SAI DMA request */ - hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; - - /* Abort the SAI DMA Streams */ - if(hsai->hdmatx != NULL) - { - if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) - { - return HAL_ERROR; - } - } - - if(hsai->hdmarx != NULL) - { - if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) - { - return HAL_ERROR; - } - } - - /* Disable SAI peripheral */ - SAI_Disable(hsai); - - hsai->State = HAL_SAI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_OK; -} - -/** - * @brief Abort the current transfer and disable the SAI. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) -{ - /* Process Locked */ - __HAL_LOCK(hsai); - - /* Check SAI DMA is enabled or not */ - if((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) - { - /* Disable the SAI DMA request */ - hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; - - /* Abort the SAI DMA Streams */ - if(hsai->hdmatx != NULL) - { - if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) - { - return HAL_ERROR; - } - } - - if(hsai->hdmarx != NULL) - { - if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) - { - return HAL_ERROR; - } - } - } - /* Disabled All interrupt and clear all the flag */ - hsai->Instance->IMR = 0; - hsai->Instance->CLRFR = 0xFFFFFFFFU; - - /* Disable SAI peripheral */ - SAI_Disable(hsai); - - /* Flush the fifo */ - SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); - - hsai->State = HAL_SAI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_OK; -} - -/** - * @brief Transmit an amount of data in non-blocking mode with DMA. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) -{ - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(hsai->State == HAL_SAI_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsai); - - hsai->pBuffPtr = pData; - hsai->XferSize = Size; - hsai->XferCount = Size; - hsai->ErrorCode = HAL_SAI_ERROR_NONE; - hsai->State = HAL_SAI_STATE_BUSY_TX; - - /* Set the SAI Tx DMA Half transfer complete callback */ - hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt; - - /* Set the SAI TxDMA transfer complete callback */ - hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt; - - /* Set the DMA error callback */ - hsai->hdmatx->XferErrorCallback = SAI_DMAError; - - /* Set the DMA Tx abort callback */ - hsai->hdmatx->XferAbortCallback = NULL; - - /* Enable the Tx DMA Stream */ - if(HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, hsai->XferSize) != HAL_OK) - { - __HAL_UNLOCK(hsai); - return HAL_ERROR; - } - - /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) - { - /* Enable SAI peripheral */ - __HAL_SAI_ENABLE(hsai); - } - - /* Enable the interrupts for error handling */ - __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); - - /* Enable SAI Tx DMA Request */ - hsai->Instance->CR1 |= SAI_xCR1_DMAEN; - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) -{ - - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(hsai->State == HAL_SAI_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsai); - - hsai->pBuffPtr = pData; - hsai->XferSize = Size; - hsai->XferCount = Size; - hsai->ErrorCode = HAL_SAI_ERROR_NONE; - hsai->State = HAL_SAI_STATE_BUSY_RX; - - /* Set the SAI Rx DMA Half transfer complete callback */ - hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt; - - /* Set the SAI Rx DMA transfer complete callback */ - hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt; - - /* Set the DMA error callback */ - hsai->hdmarx->XferErrorCallback = SAI_DMAError; - - /* Set the DMA Rx abort callback */ - hsai->hdmarx->XferAbortCallback = NULL; - - /* Enable the Rx DMA Stream */ - if(HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, hsai->XferSize) != HAL_OK) - { - __HAL_UNLOCK(hsai); - return HAL_ERROR; - } - - /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) - { - /* Enable SAI peripheral */ - __HAL_SAI_ENABLE(hsai); - } - - /* Enable the interrupts for error handling */ - __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); - - /* Enable SAI Rx DMA Request */ - hsai->Instance->CR1 |= SAI_xCR1_DMAEN; - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Enable the Tx mute mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param val: value sent during the mute @ref SAI_Block_Mute_Value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val) -{ - assert_param(IS_SAI_BLOCK_MUTE_VALUE(val)); - - if(hsai->State != HAL_SAI_STATE_RESET) - { - CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE); - SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | val); - return HAL_OK; - } - return HAL_ERROR; -} - -/** - * @brief Disable the Tx mute mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai) -{ - if(hsai->State != HAL_SAI_STATE_RESET) - { - CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE); - return HAL_OK; - } - return HAL_ERROR; -} - -/** - * @brief Enable the Rx mute detection. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param callback: function called when the mute is detected. - * @param counter: number a data before mute detection max 63. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter) -{ - assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter)); - - if(hsai->State != HAL_SAI_STATE_RESET) - { - /* set the mute counter */ - CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT); - SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_OFFSET)); - hsai->mutecallback = callback; - /* enable the IT interrupt */ - __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET); - return HAL_OK; - } - return HAL_ERROR; -} - -/** - * @brief Disable the Rx mute detection. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai) -{ - if(hsai->State != HAL_SAI_STATE_RESET) - { - /* set the mutecallback to NULL */ - hsai->mutecallback = (SAIcallback)NULL; - /* enable the IT interrupt */ - __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET); - return HAL_OK; - } - return HAL_ERROR; -} - -/** - * @brief Handle SAI interrupt request. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) -{ - if(hsai->State != HAL_SAI_STATE_RESET) - { - uint32_t itflags = hsai->Instance->SR; - uint32_t itsources = hsai->Instance->IMR; - uint32_t cr1config = hsai->Instance->CR1; - uint32_t tmperror; - - /* SAI Fifo request interrupt occured ------------------------------------*/ - if(((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ)) - { - hsai->InterruptServiceRoutine(hsai); - } - /* SAI Overrun error interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR)) - { - /* Clear the SAI Overrun flag */ - __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); - /* Get the SAI error code */ - tmperror = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR); - /* Change the SAI error code */ - hsai->ErrorCode |= tmperror; - /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */ - HAL_SAI_ErrorCallback(hsai); - } - /* SAI mutedet interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET)) - { - /* Clear the SAI mutedet flag */ - __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET); - /* call the call back function */ - if(hsai->mutecallback != (SAIcallback)NULL) - { - /* inform the user that an RX mute event has been detected */ - hsai->mutecallback(); - } - } - /* SAI AFSDET interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET)) - { - /* Change the SAI error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET; - /* Check SAI DMA is enabled or not */ - if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) - { - /* Abort the SAI DMA Streams */ - if(hsai->hdmatx != NULL) - { - /* Set the DMA Tx abort callback */ - hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; - - /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmatx); - } - else if(hsai->hdmarx != NULL) - { - /* Set the DMA Rx abort callback */ - hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; - /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmarx); - } - } - else - { - /* Abort SAI */ - HAL_SAI_Abort(hsai); - - /* Set error callback */ - HAL_SAI_ErrorCallback(hsai); - } - } - /* SAI LFSDET interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET)) - { - /* Change the SAI error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET; - - /* Check SAI DMA is enabled or not */ - if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) - { - /* Abort the SAI DMA Streams */ - if(hsai->hdmatx != NULL) - { - /* Set the DMA Tx abort callback */ - hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; - /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmatx); - } - else if(hsai->hdmarx != NULL) - { - /* Set the DMA Rx abort callback */ - hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; - /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmarx); - } - } - else - { - /* Abort SAI */ - HAL_SAI_Abort(hsai); - - /* Set error callback */ - HAL_SAI_ErrorCallback(hsai); - } - } - /* SAI WCKCFG interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG)) - { - /* Change the SAI error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG; - - /* Abort the SAI DMA Streams */ - if(hsai->hdmatx != NULL) - { - /* Set the DMA Tx abort callback */ - hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; - /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmatx); - } - else if(hsai->hdmarx != NULL) - { - /* Set the DMA Rx abort callback */ - hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; - /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmarx); - } - else - { - /* If WCKCFG occurs, SAI audio block is automatically disabled */ - /* Disable all interrupts and clear all flags */ - hsai->Instance->IMR = 0U; - hsai->Instance->CLRFR = 0xFFFFFFFFU; - /* Set the SAI state to ready to be able to start again the process */ - hsai->State = HAL_SAI_STATE_READY; - - /* Initialize XferCount */ - hsai->XferCount = 0U; - - /* SAI error Callback */ - HAL_SAI_ErrorCallback(hsai); - } - } - /* SAI CNRDY interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY)) - { - /* Clear the SAI CNRDY flag */ - __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY); - /* Change the SAI error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY; - /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */ - HAL_SAI_ErrorCallback(hsai); - } - else - { - /* Nothing to do */ - } - } -} - -/** - * @brief Tx Transfer completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -__weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsai); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SAI_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Tx Transfer Half completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ - __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsai); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SAI_TxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -__weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsai); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SAI_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer half completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -__weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsai); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SAI_RxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief SAI error callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -__weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsai); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SAI_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - - -/** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the SAI handle state. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval HAL state - */ -HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) -{ - return hsai->State; -} - -/** -* @brief Return the SAI error code. -* @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for the specified SAI Block. -* @retval SAI Error Code -*/ -uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai) -{ - return hsai->ErrorCode; -} -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup SAI_Private_Functions - * @brief Private functions - * @{ - */ - -/** - * @brief Initialize the SAI I2S protocol according to the specified parameters - * in the SAI_InitTypeDef and create the associated handle. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param protocol: one of the supported protocol. - * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize - * the configuration information for SAI module. - * @param nbslot: number of slot minimum value is 2 and max is 16. - * the value must be a multiple of 2. - * @retval HAL status - */ -static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) -{ - hsai->Init.Protocol = SAI_FREE_PROTOCOL; - hsai->Init.FirstBit = SAI_FIRSTBIT_MSB; - /* Compute ClockStrobing according AudioMode */ - if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) - { /* Transmit */ - hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; - } - else - { /* Receive */ - hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; - } - hsai->FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION; - hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL; - hsai->SlotInit.FirstBitOffset = 0; - hsai->SlotInit.SlotNumber = nbslot; - - /* in IS2 the number of slot must be even */ - if((nbslot & 0x1) != 0 ) - { - return HAL_ERROR; - } - - switch(protocol) - { - case SAI_I2S_STANDARD : - hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; - hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; - break; - case SAI_I2S_MSBJUSTIFIED : - case SAI_I2S_LSBJUSTIFIED : - hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH; - hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT; - break; - default : - return HAL_ERROR; - } - - /* Frame definition */ - switch(datasize) - { - case SAI_PROTOCOL_DATASIZE_16BIT: - hsai->Init.DataSize = SAI_DATASIZE_16; - hsai->FrameInit.FrameLength = 32*(nbslot/2); - hsai->FrameInit.ActiveFrameLength = 16*(nbslot/2); - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; - break; - case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : - hsai->Init.DataSize = SAI_DATASIZE_16; - hsai->FrameInit.FrameLength = 64*(nbslot/2); - hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2); - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - case SAI_PROTOCOL_DATASIZE_24BIT: - hsai->Init.DataSize = SAI_DATASIZE_24; - hsai->FrameInit.FrameLength = 64*(nbslot/2); - hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2); - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - case SAI_PROTOCOL_DATASIZE_32BIT: - hsai->Init.DataSize = SAI_DATASIZE_32; - hsai->FrameInit.FrameLength = 64*(nbslot/2); - hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2); - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - default : - return HAL_ERROR; - } - if(protocol == SAI_I2S_LSBJUSTIFIED) - { - if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) - { - hsai->SlotInit.FirstBitOffset = 16; - } - if (datasize == SAI_PROTOCOL_DATASIZE_24BIT) - { - hsai->SlotInit.FirstBitOffset = 8; - } - } - return HAL_OK; -} - -/** - * @brief Initialize the SAI PCM protocol according to the specified parameters - * in the SAI_InitTypeDef and create the associated handle. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param protocol: one of the supported protocol - * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize - * @param nbslot: number of slot minimum value is 1 and the max is 16. - * @retval HAL status - */ -static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) -{ - hsai->Init.Protocol = SAI_FREE_PROTOCOL; - hsai->Init.FirstBit = SAI_FIRSTBIT_MSB; - /* Compute ClockStrobing according AudioMode */ - if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) - { /* Transmit */ - hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; - } - else - { /* Receive */ - hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; - } - hsai->FrameInit.FSDefinition = SAI_FS_STARTFRAME; - hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH; - hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; - hsai->SlotInit.FirstBitOffset = 0; - hsai->SlotInit.SlotNumber = nbslot; - hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL; - - switch(protocol) - { - case SAI_PCM_SHORT : - hsai->FrameInit.ActiveFrameLength = 1; - break; - case SAI_PCM_LONG : - hsai->FrameInit.ActiveFrameLength = 13; - break; - default : - return HAL_ERROR; - } - - switch(datasize) - { - case SAI_PROTOCOL_DATASIZE_16BIT: - hsai->Init.DataSize = SAI_DATASIZE_16; - hsai->FrameInit.FrameLength = 16 * nbslot; - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; - break; - case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : - hsai->Init.DataSize = SAI_DATASIZE_16; - hsai->FrameInit.FrameLength = 32 * nbslot; - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - case SAI_PROTOCOL_DATASIZE_24BIT : - hsai->Init.DataSize = SAI_DATASIZE_24; - hsai->FrameInit.FrameLength = 32 * nbslot; - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - case SAI_PROTOCOL_DATASIZE_32BIT: - hsai->Init.DataSize = SAI_DATASIZE_32; - hsai->FrameInit.FrameLength = 32 * nbslot; - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - default : - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Fill the fifo. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -static void SAI_FillFifo(SAI_HandleTypeDef *hsai) -{ - /* fill the fifo with data before to enabled the SAI */ - while(((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0)) - { - if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) - { - hsai->Instance->DR = (*hsai->pBuffPtr++); - } - else if(hsai->Init.DataSize <= SAI_DATASIZE_16) - { - hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr); - hsai->pBuffPtr+= 2; - } - else - { - hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr); - hsai->pBuffPtr+= 4; - } - hsai->XferCount--; - } -} - -/** - * @brief Return the interrupt flag to set according the SAI setup. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param mode: SAI_MODE_DMA or SAI_MODE_IT - * @retval the list of the IT flag to enable - */ -static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) -{ - uint32_t tmpIT = SAI_IT_OVRUDR; - - if(mode == SAI_MODE_IT) - { - tmpIT|= SAI_IT_FREQ; - } - - if((hsai->Init.Protocol == SAI_AC97_PROTOCOL) && - ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX))) - { - tmpIT|= SAI_IT_CNRDY; - } - - if((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) - { - tmpIT|= SAI_IT_AFSDET | SAI_IT_LFSDET; - } - else - { - /* hsai has been configured in master mode */ - tmpIT|= SAI_IT_WCKCFG; - } - return tmpIT; -} - -/** - * @brief Disable the SAI and wait for the disabling. - * @param hsai : pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai) -{ - register uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock /7/1000); - HAL_StatusTypeDef status = HAL_OK; - - /* Disable the SAI instance */ - __HAL_SAI_DISABLE(hsai); - - do - { - /* Check for the Timeout */ - if (count-- == 0) - { - /* Update error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; - status = HAL_TIMEOUT; - break; - } - } while((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET); - - return status; -} - -/** - * @brief Tx Handler for Transmit in Interrupt mode 8-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai) -{ - if(hsai->XferCount == 0) - { - /* Handle the end of the transmission */ - /* Disable FREQ and OVRUDR interrupts */ - __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - hsai->State = HAL_SAI_STATE_READY; - HAL_SAI_TxCpltCallback(hsai); - } - else - { - /* Write data on DR register */ - hsai->Instance->DR = (*hsai->pBuffPtr++); - hsai->XferCount--; - } -} - -/** - * @brief Tx Handler for Transmit in Interrupt mode for 16-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai) -{ - if(hsai->XferCount == 0) - { - /* Handle the end of the transmission */ - /* Disable FREQ and OVRUDR interrupts */ - __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - hsai->State = HAL_SAI_STATE_READY; - HAL_SAI_TxCpltCallback(hsai); - } - else - { - /* Write data on DR register */ - hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr; - hsai->pBuffPtr+=2; - hsai->XferCount--; - } -} - -/** - * @brief Tx Handler for Transmit in Interrupt mode for 32-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai) -{ - if(hsai->XferCount == 0) - { - /* Handle the end of the transmission */ - /* Disable FREQ and OVRUDR interrupts */ - __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - hsai->State = HAL_SAI_STATE_READY; - HAL_SAI_TxCpltCallback(hsai); - } - else - { - /* Write data on DR register */ - hsai->Instance->DR = *(uint32_t *)hsai->pBuffPtr; - hsai->pBuffPtr+=4; - hsai->XferCount--; - } -} - -/** - * @brief Rx Handler for Receive in Interrupt mode 8-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai) -{ - /* Receive data */ - (*hsai->pBuffPtr++) = hsai->Instance->DR; - hsai->XferCount--; - - /* Check end of the transfer */ - if(hsai->XferCount == 0) - { - /* Disable TXE and OVRUDR interrupts */ - __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - - /* Clear the SAI Overrun flag */ - __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); - - hsai->State = HAL_SAI_STATE_READY; - HAL_SAI_RxCpltCallback(hsai); - } -} - -/** - * @brief Rx Handler for Receive in Interrupt mode for 16-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai) -{ - /* Receive data */ - *(uint16_t*)hsai->pBuffPtr = hsai->Instance->DR; - hsai->pBuffPtr+=2; - hsai->XferCount--; - - /* Check end of the transfer */ - if(hsai->XferCount == 0) - { - /* Disable TXE and OVRUDR interrupts */ - __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - - /* Clear the SAI Overrun flag */ - __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); - - hsai->State = HAL_SAI_STATE_READY; - HAL_SAI_RxCpltCallback(hsai); - } -} -/** - * @brief Rx Handler for Receive in Interrupt mode for 32-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai) -{ - /* Receive data */ - *(uint32_t*)hsai->pBuffPtr = hsai->Instance->DR; - hsai->pBuffPtr+=4; - hsai->XferCount--; - - /* Check end of the transfer */ - if(hsai->XferCount == 0) - { - /* Disable TXE and OVRUDR interrupts */ - __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - - /* Clear the SAI Overrun flag */ - __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); - - hsai->State = HAL_SAI_STATE_READY; - HAL_SAI_RxCpltCallback(hsai); - } -} - -/** - * @brief DMA SAI transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) -{ - SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent; - - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) - { - hsai->XferCount = 0; - - /* Disable SAI Tx DMA Request */ - hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN); - - /* Stop the interrupts error handling */ - __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); - - hsai->State= HAL_SAI_STATE_READY; - } - HAL_SAI_TxCpltCallback(hsai); -} - -/** - * @brief DMA SAI transmit process half complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) -{ - SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - HAL_SAI_TxHalfCpltCallback(hsai); -} - -/** - * @brief DMA SAI receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma) -{ - SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) - { - /* Disable Rx DMA Request */ - hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN); - hsai->XferCount = 0; - - /* Stop the interrupts error handling */ - __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); - - hsai->State = HAL_SAI_STATE_READY; - } - HAL_SAI_RxCpltCallback(hsai); -} - -/** - * @brief DMA SAI receive process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - HAL_SAI_RxHalfCpltCallback(hsai); -} -/** - * @brief DMA SAI communication error callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SAI_DMAError(DMA_HandleTypeDef *hdma) -{ - SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Set SAI error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_DMA; - - if((hsai->hdmatx->ErrorCode == HAL_DMA_ERROR_TE) || (hsai->hdmarx->ErrorCode == HAL_DMA_ERROR_TE)) - { - /* Disable the SAI DMA request */ - hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; - - /* Disable SAI peripheral */ - SAI_Disable(hsai); - - /* Set the SAI state ready to be able to start again the process */ - hsai->State = HAL_SAI_STATE_READY; - - /* Initialize XferCount */ - hsai->XferCount = 0U; - } - /* SAI error Callback */ - HAL_SAI_ErrorCallback(hsai); -} - -/** - * @brief DMA SAI Abort callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SAI_DMAAbort(DMA_HandleTypeDef *hdma) -{ - SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Disable DMA request */ - hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; - - /* Disable all interrupts and clear all flags */ - hsai->Instance->IMR = 0U; - hsai->Instance->CLRFR = 0xFFFFFFFFU; - - if(hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG) - { - /* Disable SAI peripheral */ - SAI_Disable(hsai); - - /* Flush the fifo */ - SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); - } - /* Set the SAI state to ready to be able to start again the process */ - hsai->State = HAL_SAI_STATE_READY; - - /* Initialize XferCount */ - hsai->XferCount = 0U; - - /* SAI error Callback */ - HAL_SAI_ErrorCallback(hsai); -} - -/** - * @} - */ - -#endif /* HAL_SAI_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai_ex.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai_ex.c deleted file mode 100644 index f31d76d..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai_ex.c +++ /dev/null @@ -1,52 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_sai_ex.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief Empty file; This file is no longer used to set synchronization and - * to get SAI block frequency. Its content is now moved to common files - * (stm32f7xx_hal_sai.c/.h) as there's no device's dependency within F7 - * family. It's just kept for compatibility reasons. - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c deleted file mode 100644 index 938a7a3..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c +++ /dev/null @@ -1,3405 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_sd.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief SD card HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Secure Digital (SD) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - This driver implements a high level communication layer for read and write from/to - this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by - the user in HAL_SD_MspInit() function (MSP layer). - Basically, the MSP layer configuration should be the same as we provide in the - examples. - You can easily tailor this configuration according to hardware resources. - - [..] - This driver is a generic layered driver for SDMMC memories which uses the HAL - SDMMC driver functions to interface with SD and uSD cards devices. - It is used as follows: - - (#)Initialize the SDMMC low level resources by implement the HAL_SD_MspInit() API: - (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE(); - (##) SDMMC pins configuration for SD card - (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); - (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init() - and according to your pin assignment; - (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA() - and HAL_SD_WriteBlocks_DMA() APIs). - (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); - (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. - (##) NVIC configuration if you need to use interrupt process when using DMA transfer. - (+++) Configure the SDMMC and DMA interrupt priorities using functions - HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority - (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ() - (+++) SDMMC interrupts are managed using the macros __HAL_SD_SDMMC_ENABLE_IT() - and __HAL_SD_SDMMC_DISABLE_IT() inside the communication process. - (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_SDMMC_GET_IT() - and __HAL_SD_SDMMC_CLEAR_IT() - (#) At this stage, you can perform SD read/write/erase operations after SD card initialization - - - *** SD Card Initialization and configuration *** - ================================================ - [..] - To initialize the SD Card, use the HAL_SD_Init() function. It Initializes - the SD Card and put it into StandBy State (Ready for data transfer). - This function provide the following operations: - - (#) Apply the SD Card initialization process at 400KHz and check the SD Card - type (Standard Capacity or High Capacity). You can change or adapt this - frequency by adjusting the "ClockDiv" field. - The SD Card frequency (SDMMC_CK) is computed as follows: - - SDMMC_CK = SDMMCCLK / (ClockDiv + 2) - - In initialization mode and according to the SD Card standard, - make sure that the SDMMC_CK frequency doesn't exceed 400KHz. - - (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo - structure. This structure provide also ready computed SD Card capacity - and Block size. - - -@- These information are stored in SD handle structure in case of future use. - - (#) Configure the SD Card Data transfer frequency. By Default, the card transfer - frequency is set to 24MHz. You can change or adapt this frequency by adjusting - the "ClockDiv" field. - In transfer mode and according to the SD Card standard, make sure that the - SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch. - To be able to use a frequency higher than 24MHz, you should use the SDMMC - peripheral in bypass mode. Refer to the corresponding reference manual - for more details. - - (#) Select the corresponding SD Card according to the address read with the step 2. - - (#) Configure the SD Card in wide bus mode: 4-bits data. - - *** SD Card Read operation *** - ============================== - [..] - (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). - This function support only 512-bytes block length (the block size should be - chosen as 512 bytes). - You can choose either one block read operation or multiple block read operation - by adjusting the "NumberOfBlocks" parameter. - - (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA(). - This function support only 512-bytes block length (the block size should be - chosen as 512 bytes). - You can choose either one block read operation or multiple block read operation - by adjusting the "NumberOfBlocks" parameter. - After this, you have to call the function HAL_SD_CheckReadOperation(), to insure - that the read transfer is done correctly in both DMA and SD sides. - - *** SD Card Write operation *** - =============================== - [..] - (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). - This function support only 512-bytes block length (the block size should be - chosen as 512 bytes). - You can choose either one block read operation or multiple block read operation - by adjusting the "NumberOfBlocks" parameter. - - (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA(). - This function support only 512-bytes block length (the block size should be - chosen as 512 byte). - You can choose either one block read operation or multiple block read operation - by adjusting the "NumberOfBlocks" parameter. - After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure - that the write transfer is done correctly in both DMA and SD sides. - - *** SD card status *** - ====================== - [..] - (+) At any time, you can check the SD Card status and get the SD card state - by using the HAL_SD_GetStatus() function. This function checks first if the - SD card is still connected and then get the internal SD Card transfer state. - (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus() - function. - - *** SD HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in SD HAL driver. - - (+) __HAL_SD_SDMMC_ENABLE : Enable the SD device - (+) __HAL_SD_SDMMC_DISABLE : Disable the SD device - (+) __HAL_SD_SDMMC_DMA_ENABLE: Enable the SDMMC DMA transfer - (+) __HAL_SD_SDMMC_DMA_DISABLE: Disable the SDMMC DMA transfer - (+) __HAL_SD_SDMMC_ENABLE_IT: Enable the SD device interrupt - (+) __HAL_SD_SDMMC_DISABLE_IT: Disable the SD device interrupt - (+) __HAL_SD_SDMMC_GET_FLAG:Check whether the specified SD flag is set or not - (+) __HAL_SD_SDMMC_CLEAR_FLAG: Clear the SD's pending flags - - (@) You can refer to the SD HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup SD - * @{ - */ - -#ifdef HAL_SD_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup SD_Private_Defines - * @{ - */ -/** - * @brief SDMMC Data block size - */ -#define DATA_BLOCK_SIZE ((uint32_t)(9 << 4)) -/** - * @brief SDMMC Static flags, Timeout, FIFO Address - */ -#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ - SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ - SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ - SDMMC_FLAG_DBCKEND)) - -#define SDMMC_CMD0TIMEOUT ((uint32_t)0x00010000U) - -/** - * @brief Mask for errors Card Status R1 (OCR Register) - */ -#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U) -#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U) -#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U) -#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U) -#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U) -#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U) -#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U) -#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U) -#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U) -#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U) -#define SD_OCR_CC_ERROR ((uint32_t)0x00100000U) -#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U) -#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U) -#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U) -#define SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U) -#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U) -#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U) -#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000U) -#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U) -#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008U) - -/** - * @brief Masks for R6 Response - */ -#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U) -#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000U) -#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000U) - -#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U) -#define SD_HIGH_CAPACITY ((uint32_t)0x40000000U) -#define SD_STD_CAPACITY ((uint32_t)0x00000000U) -#define SD_CHECK_PATTERN ((uint32_t)0x000001AAU) - -#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) -#define SD_ALLZERO ((uint32_t)0x00000000U) - -#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U) -#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) -#define SD_CARD_LOCKED ((uint32_t)0x02000000U) - -#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) -#define SD_0TO7BITS ((uint32_t)0x000000FFU) -#define SD_8TO15BITS ((uint32_t)0x0000FF00U) -#define SD_16TO23BITS ((uint32_t)0x00FF0000U) -#define SD_24TO31BITS ((uint32_t)0xFF000000U) -#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU) - -#define SD_HALFFIFO ((uint32_t)0x00000008U) -#define SD_HALFFIFOBYTES ((uint32_t)0x00000020U) - -/** - * @brief Command Class Supported - */ -#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080U) -#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040U) -#define SD_CCCC_ERASE ((uint32_t)0x00000020U) - -/** - * @brief Following commands are SD Card Specific commands. - * SDMMC_APP_CMD should be sent before sending these commands. - */ -#define SD_SDMMC_SEND_IF_COND ((uint32_t)SD_CMD_HS_SEND_EXT_CSD) -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @defgroup SD_Private_Functions SD Private Functions - * @{ - */ -static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr); -static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus); -static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus); -static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD); -static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA); -static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR); -static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma); -static void SD_DMA_RxError(DMA_HandleTypeDef *hdma); -static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma); -static void SD_DMA_TxError(DMA_HandleTypeDef *hdma); -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup SD_Exported_Functions - * @{ - */ - -/** @addtogroup SD_Exported_Functions_Group1 - * @brief Initialization and de-initialization functions - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to initialize/de-initialize the SD - card device to be ready for use. - - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the SD card according to the specified parameters in the - SD_HandleTypeDef and create the associated handle. - * @param hsd: SD handle - * @param SDCardInfo: HAL_SD_CardInfoTypedef structure for SD card information - * @retval HAL SD error state - */ -HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo) -{ - __IO HAL_SD_ErrorTypedef errorstate = SD_OK; - SD_InitTypeDef tmpinit; - - /* Allocate lock resource and initialize it */ - hsd->Lock = HAL_UNLOCKED; - - /* Initialize the low level hardware (MSP) */ - HAL_SD_MspInit(hsd); - - /* Default SDMMC peripheral configuration for SD card initialization */ - tmpinit.ClockEdge = SDMMC_CLOCK_EDGE_RISING; - tmpinit.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; - tmpinit.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; - tmpinit.BusWide = SDMMC_BUS_WIDE_1B; - tmpinit.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; - tmpinit.ClockDiv = SDMMC_INIT_CLK_DIV; - - /* Initialize SDMMC peripheral interface with default configuration */ - SDMMC_Init(hsd->Instance, tmpinit); - - /* Identify card operating voltage */ - errorstate = SD_PowerON(hsd); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Initialize the present SDMMC card(s) and put them in idle state */ - errorstate = SD_Initialize_Cards(hsd); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Read CSD/CID MSD registers */ - errorstate = HAL_SD_Get_CardInfo(hsd, SDCardInfo); - - if (errorstate == SD_OK) - { - /* Select the Card */ - errorstate = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16)); - } - - /* Configure SDMMC peripheral interface */ - SDMMC_Init(hsd->Instance, hsd->Init); - - return errorstate; -} - -/** - * @brief De-Initializes the SD card. - * @param hsd: SD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) -{ - - /* Set SD power state to off */ - SD_PowerOFF(hsd); - - /* De-Initialize the MSP layer */ - HAL_SD_MspDeInit(hsd); - - return HAL_OK; -} - - -/** - * @brief Initializes the SD MSP. - * @param hsd: SD handle - * @retval None - */ -__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_MspInit could be implemented in the user file - */ -} - -/** - * @brief De-Initialize SD MSP. - * @param hsd: SD handle - * @retval None - */ -__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @addtogroup SD_Exported_Functions_Group2 - * @brief Data transfer functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to manage the data - transfer from/to SD card. - -@endverbatim - * @{ - */ - -/** - * @brief Reads block(s) from a specified address in a card. The Data transfer - * is managed by polling mode. - * @param hsd: SD handle - * @param pReadBuffer: pointer to the buffer that will contain the received data - * @param ReadAddr: Address from where data is to be read - * @param BlockSize: SD card Data block size - * @note BlockSize must be 512 bytes. - * @param NumberOfBlocks: Number of SD blocks to read - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - SDMMC_DataInitTypeDef sdmmc_datainitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t count = 0, *tempbuff = (uint32_t *)pReadBuffer; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0; - - if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - ReadAddr /= 512; - } - - /* Set Block Size for Card */ - sdmmc_cmdinitstructure.Argument = (uint32_t) BlockSize; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdmmc_datainitstructure.DataLength = NumberOfBlocks * BlockSize; - sdmmc_datainitstructure.DataBlockSize = DATA_BLOCK_SIZE; - sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure); - - if(NumberOfBlocks > 1) - { - /* Send CMD18 READ_MULT_BLOCK with argument data address */ - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK; - } - else - { - /* Send CMD17 READ_SINGLE_BLOCK */ - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK; - } - - sdmmc_cmdinitstructure.Argument = (uint32_t)ReadAddr; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Read block(s) in polling mode */ - if(NumberOfBlocks > 1) - { - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Poll on SDMMC flags */ - while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) - { - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) - { - /* Read data from SDMMC Rx FIFO */ - for (count = 0; count < 8; count++) - { - *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance); - } - - tempbuff += 8; - } - } - } - else - { - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* In case of single block transfer, no need of stop transfer at all */ - while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND)) - { - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) - { - /* Read data from SDMMC Rx FIFO */ - for (count = 0; count < 8; count++) - { - *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance); - } - - tempbuff += 8; - } - } - } - - /* Send stop transmission command in case of multiblock read */ - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1)) - { - if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) ||\ - (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ - (hsd->CardType == HIGH_CAPACITY_SD_CARD)) - { - /* Send stop transmission command */ - errorstate = HAL_SD_StopTransfer(hsd); - } - } - - /* Get error state */ - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); - - errorstate = SD_DATA_TIMEOUT; - - return errorstate; - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); - - errorstate = SD_DATA_CRC_FAIL; - - return errorstate; - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); - - errorstate = SD_RX_OVERRUN; - - return errorstate; - } - else - { - /* No error flag set */ - } - - count = SD_DATATIMEOUT; - - /* Empty FIFO if there is still any data */ - while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0)) - { - *tempbuff = SDMMC_ReadFIFO(hsd->Instance); - tempbuff++; - count--; - } - - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - return errorstate; -} - -/** - * @brief Allows to write block(s) to a specified address in a card. The Data - * transfer is managed by polling mode. - * @param hsd: SD handle - * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit - * @param WriteAddr: Address from where data is to be written - * @param BlockSize: SD card Data block size - * @note BlockSize must be 512 bytes. - * @param NumberOfBlocks: Number of SD blocks to write - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - SDMMC_DataInitTypeDef sdmmc_datainitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t totalnumberofbytes = 0, bytestransferred = 0, count = 0, restwords = 0; - uint32_t *tempbuff = (uint32_t *)pWriteBuffer; - uint8_t cardstate = 0; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0; - - if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - WriteAddr /= 512; - } - - /* Set Block Size for Card */ - sdmmc_cmdinitstructure.Argument = (uint32_t)BlockSize; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) - { - return errorstate; - } - - if(NumberOfBlocks > 1) - { - /* Send CMD25 WRITE_MULT_BLOCK with argument data address */ - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK; - } - else - { - /* Send CMD24 WRITE_SINGLE_BLOCK */ - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK; - } - - sdmmc_cmdinitstructure.Argument = (uint32_t)WriteAddr; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - if(NumberOfBlocks > 1) - { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK); - } - else - { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK); - } - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Set total number of bytes to write */ - totalnumberofbytes = NumberOfBlocks * BlockSize; - - /* Configure the SD DPSM (Data Path State Machine) */ - sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdmmc_datainitstructure.DataLength = NumberOfBlocks * BlockSize; - sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; - sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure); - - /* Write block(s) in polling mode */ - if(NumberOfBlocks > 1) - { - while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) - { - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE)) - { - if ((totalnumberofbytes - bytestransferred) < 32) - { - restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1); - - /* Write data to SDMMC Tx FIFO */ - for (count = 0; count < restwords; count++) - { - SDMMC_WriteFIFO(hsd->Instance, tempbuff); - tempbuff++; - bytestransferred += 4; - } - } - else - { - /* Write data to SDMMC Tx FIFO */ - for (count = 0; count < 8; count++) - { - SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count)); - } - - tempbuff += 8; - bytestransferred += 32; - } - } - } - } - else - { - /* In case of single data block transfer no need of stop command at all */ - while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND)) - { - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE)) - { - if ((totalnumberofbytes - bytestransferred) < 32) - { - restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1); - - /* Write data to SDMMC Tx FIFO */ - for (count = 0; count < restwords; count++) - { - SDMMC_WriteFIFO(hsd->Instance, tempbuff); - tempbuff++; - bytestransferred += 4; - } - } - else - { - /* Write data to SDMMC Tx FIFO */ - for (count = 0; count < 8; count++) - { - SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count)); - } - - tempbuff += 8; - bytestransferred += 32; - } - } - } - } - - /* Send stop transmission command in case of multiblock write */ - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1)) - { - if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ - (hsd->CardType == HIGH_CAPACITY_SD_CARD)) - { - /* Send stop transmission command */ - errorstate = HAL_SD_StopTransfer(hsd); - } - } - - /* Get error state */ - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); - - errorstate = SD_DATA_TIMEOUT; - - return errorstate; - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); - - errorstate = SD_DATA_CRC_FAIL; - - return errorstate; - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_TXUNDERR); - - errorstate = SD_TX_UNDERRUN; - - return errorstate; - } - else - { - /* No error flag set */ - } - - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - /* Wait till the card is in programming state */ - errorstate = SD_IsCardProgramming(hsd, &cardstate); - - while ((errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING))) - { - errorstate = SD_IsCardProgramming(hsd, &cardstate); - } - - return errorstate; -} - -/** - * @brief Reads block(s) from a specified address in a card. The Data transfer - * is managed by DMA mode. - * @note This API should be followed by the function HAL_SD_CheckReadOperation() - * to check the completion of the read process - * @param hsd: SD handle - * @param pReadBuffer: Pointer to the buffer that will contain the received data - * @param ReadAddr: Address from where data is to be read - * @param BlockSize: SD card Data block size - * @note BlockSize must be 512 bytes. - * @param NumberOfBlocks: Number of blocks to read. - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - SDMMC_DataInitTypeDef sdmmc_datainitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0; - - /* Initialize handle flags */ - hsd->SdTransferCplt = 0; - hsd->DmaTransferCplt = 0; - hsd->SdTransferErr = SD_OK; - - /* Initialize SD Read operation */ - if(NumberOfBlocks > 1) - { - hsd->SdOperation = SD_READ_MULTIPLE_BLOCK; - } - else - { - hsd->SdOperation = SD_READ_SINGLE_BLOCK; - } - - /* Enable transfer interrupts */ - __HAL_SD_SDMMC_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL |\ - SDMMC_IT_DTIMEOUT |\ - SDMMC_IT_DATAEND |\ - SDMMC_IT_RXOVERR)); - - /* Enable SDMMC DMA transfer */ - __HAL_SD_SDMMC_DMA_ENABLE(hsd); - - /* Configure DMA user callbacks */ - hsd->hdmarx->XferCpltCallback = SD_DMA_RxCplt; - hsd->hdmarx->XferErrorCallback = SD_DMA_RxError; - - /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)/4); - - if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - ReadAddr /= 512; - } - - /* Set Block Size for Card */ - sdmmc_cmdinitstructure.Argument = (uint32_t)BlockSize; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdmmc_datainitstructure.DataLength = BlockSize * NumberOfBlocks; - sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure); - - /* Check number of blocks command */ - if(NumberOfBlocks > 1) - { - /* Send CMD18 READ_MULT_BLOCK with argument data address */ - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK; - } - else - { - /* Send CMD17 READ_SINGLE_BLOCK */ - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK; - } - - sdmmc_cmdinitstructure.Argument = (uint32_t)ReadAddr; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - if(NumberOfBlocks > 1) - { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK); - } - else - { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); - } - - /* Update the SD transfer error in SD handle */ - hsd->SdTransferErr = errorstate; - - return errorstate; -} - - -/** - * @brief Writes block(s) to a specified address in a card. The Data transfer - * is managed by DMA mode. - * @note This API should be followed by the function HAL_SD_CheckWriteOperation() - * to check the completion of the write process (by SD current status polling). - * @param hsd: SD handle - * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit - * @param WriteAddr: Address from where data is to be read - * @param BlockSize: the SD card Data block size - * @note BlockSize must be 512 bytes. - * @param NumberOfBlocks: Number of blocks to write - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - SDMMC_DataInitTypeDef sdmmc_datainitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0; - - /* Initialize handle flags */ - hsd->SdTransferCplt = 0; - hsd->DmaTransferCplt = 0; - hsd->SdTransferErr = SD_OK; - - /* Initialize SD Write operation */ - if(NumberOfBlocks > 1) - { - hsd->SdOperation = SD_WRITE_MULTIPLE_BLOCK; - } - else - { - hsd->SdOperation = SD_WRITE_SINGLE_BLOCK; - } - - /* Enable transfer interrupts */ - __HAL_SD_SDMMC_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL |\ - SDMMC_IT_DTIMEOUT |\ - SDMMC_IT_DATAEND |\ - SDMMC_IT_TXUNDERR)); - - /* Configure DMA user callbacks */ - hsd->hdmatx->XferCpltCallback = SD_DMA_TxCplt; - hsd->hdmatx->XferErrorCallback = SD_DMA_TxError; - - /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)/4); - - /* Enable SDMMC DMA transfer */ - __HAL_SD_SDMMC_DMA_ENABLE(hsd); - - if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - WriteAddr /= 512; - } - - /* Set Block Size for Card */ - sdmmc_cmdinitstructure.Argument = (uint32_t)BlockSize; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Check number of blocks command */ - if(NumberOfBlocks <= 1) - { - /* Send CMD24 WRITE_SINGLE_BLOCK */ - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK; - } - else - { - /* Send CMD25 WRITE_MULT_BLOCK with argument data address */ - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK; - } - - sdmmc_cmdinitstructure.Argument = (uint32_t)WriteAddr; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - if(NumberOfBlocks > 1) - { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK); - } - else - { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK); - } - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdmmc_datainitstructure.DataLength = BlockSize * NumberOfBlocks; - sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; - sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure); - - hsd->SdTransferErr = errorstate; - - return errorstate; -} - -/** - * @brief This function waits until the SD DMA data read transfer is finished. - * This API should be called after HAL_SD_ReadBlocks_DMA() function - * to insure that all data sent by the card is already transferred by the - * DMA controller. - * @param hsd: SD handle - * @param Timeout: Timeout duration - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t timeout = Timeout; - uint32_t tmp1, tmp2; - HAL_SD_ErrorTypedef tmp3; - - /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */ - tmp1 = hsd->DmaTransferCplt; - tmp2 = hsd->SdTransferCplt; - tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; - - while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0)) - { - tmp1 = hsd->DmaTransferCplt; - tmp2 = hsd->SdTransferCplt; - tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; - timeout--; - } - - timeout = Timeout; - - /* Wait until the Rx transfer is no longer active */ - while((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXACT)) && (timeout > 0)) - { - timeout--; - } - - /* Send stop command in multiblock read */ - if (hsd->SdOperation == SD_READ_MULTIPLE_BLOCK) - { - errorstate = HAL_SD_StopTransfer(hsd); - } - - if ((timeout == 0) && (errorstate == SD_OK)) - { - errorstate = SD_DATA_TIMEOUT; - } - - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - /* Return error state */ - if (hsd->SdTransferErr != SD_OK) - { - return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr); - } - - return errorstate; -} - -/** - * @brief This function waits until the SD DMA data write transfer is finished. - * This API should be called after HAL_SD_WriteBlocks_DMA() function - * to insure that all data sent by the card is already transferred by the - * DMA controller. - * @param hsd: SD handle - * @param Timeout: Timeout duration - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t timeout = Timeout; - uint32_t tmp1, tmp2; - HAL_SD_ErrorTypedef tmp3; - - /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */ - tmp1 = hsd->DmaTransferCplt; - tmp2 = hsd->SdTransferCplt; - tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; - - while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0)) - { - tmp1 = hsd->DmaTransferCplt; - tmp2 = hsd->SdTransferCplt; - tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; - timeout--; - } - - timeout = Timeout; - - /* Wait until the Tx transfer is no longer active */ - while((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXACT)) && (timeout > 0)) - { - timeout--; - } - - /* Send stop command in multiblock write */ - if (hsd->SdOperation == SD_WRITE_MULTIPLE_BLOCK) - { - errorstate = HAL_SD_StopTransfer(hsd); - } - - if ((timeout == 0) && (errorstate == SD_OK)) - { - errorstate = SD_DATA_TIMEOUT; - } - - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - /* Return error state */ - if (hsd->SdTransferErr != SD_OK) - { - return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr); - } - - /* Wait until write is complete */ - while(HAL_SD_GetStatus(hsd) != SD_TRANSFER_OK) - { - } - - return errorstate; -} - -/** - * @brief Erases the specified memory area of the given SD card. - * @param hsd: SD handle - * @param startaddr: Start byte address - * @param endaddr: End byte address - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - - uint32_t delay = 0; - __IO uint32_t maxdelay = 0; - uint8_t cardstate = 0; - - /* Check if the card command class supports erase command */ - if (((hsd->CSD[1] >> 20) & SD_CCCC_ERASE) == 0) - { - errorstate = SD_REQUEST_NOT_APPLICABLE; - - return errorstate; - } - - /* Get max delay value */ - maxdelay = 120000 / (((hsd->Instance->CLKCR) & 0xFF) + 2); - - if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) - { - errorstate = SD_LOCK_UNLOCK_FAILED; - - return errorstate; - } - - /* Get start and end block for high capacity cards */ - if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - startaddr /= 512; - endaddr /= 512; - } - - /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ - if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ - (hsd->CardType == HIGH_CAPACITY_SD_CARD)) - { - /* Send CMD32 SD_ERASE_GRP_START with argument as addr */ - sdmmc_cmdinitstructure.Argument =(uint32_t)startaddr; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_START; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Send CMD33 SD_ERASE_GRP_END with argument as addr */ - sdmmc_cmdinitstructure.Argument = (uint32_t)endaddr; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_END; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END); - - if (errorstate != SD_OK) - { - return errorstate; - } - } - - /* Send CMD38 ERASE */ - sdmmc_cmdinitstructure.Argument = 0; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_ERASE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_ERASE); - - if (errorstate != SD_OK) - { - return errorstate; - } - - for (; delay < maxdelay; delay++) - { - } - - /* Wait until the card is in programming state */ - errorstate = SD_IsCardProgramming(hsd, &cardstate); - - delay = SD_DATATIMEOUT; - - while ((delay > 0) && (errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING))) - { - errorstate = SD_IsCardProgramming(hsd, &cardstate); - delay--; - } - - return errorstate; -} - -/** - * @brief This function handles SD card interrupt request. - * @param hsd: SD handle - * @retval None - */ -void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) -{ - /* Check for SDMMC interrupt flags */ - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DATAEND)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_IT_DATAEND); - - /* SD transfer is complete */ - hsd->SdTransferCplt = 1; - - /* No transfer error */ - hsd->SdTransferErr = SD_OK; - - HAL_SD_XferCpltCallback(hsd); - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); - - hsd->SdTransferErr = SD_DATA_CRC_FAIL; - - HAL_SD_XferErrorCallback(hsd); - - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); - - hsd->SdTransferErr = SD_DATA_TIMEOUT; - - HAL_SD_XferErrorCallback(hsd); - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_RXOVERR)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); - - hsd->SdTransferErr = SD_RX_OVERRUN; - - HAL_SD_XferErrorCallback(hsd); - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_TXUNDERR)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_TXUNDERR); - - hsd->SdTransferErr = SD_TX_UNDERRUN; - - HAL_SD_XferErrorCallback(hsd); - } - else - { - /* No error flag set */ - } - - /* Disable all SDMMC peripheral interrupt sources */ - __HAL_SD_SDMMC_DISABLE_IT(hsd, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_DATAEND |\ - SDMMC_IT_TXFIFOHE | SDMMC_IT_RXFIFOHF | SDMMC_IT_TXUNDERR |\ - SDMMC_IT_RXOVERR); -} - - -/** - * @brief SD end of transfer callback. - * @param hsd: SD handle - * @retval None - */ -__weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_XferCpltCallback could be implemented in the user file - */ -} - -/** - * @brief SD Transfer Error callback. - * @param hsd: SD handle - * @retval None - */ -__weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsd); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_XferErrorCallback could be implemented in the user file - */ -} - -/** - * @brief SD Transfer complete Rx callback in non blocking mode. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -__weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_DMA_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief SD DMA transfer complete Rx error callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -__weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_DMA_RxErrorCallback could be implemented in the user file - */ -} - -/** - * @brief SD Transfer complete Tx callback in non blocking mode. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -__weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_DMA_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief SD DMA transfer complete error Tx callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -__weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_DMA_TxErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @addtogroup SD_Exported_Functions_Group3 - * @brief management functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the SD card - operations. - -@endverbatim - * @{ - */ - -/** - * @brief Returns information about specific card. - * @param hsd: SD handle - * @param pCardInfo: Pointer to a HAL_SD_CardInfoTypedef structure that - * contains all SD cardinformation - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t tmp = 0; - - pCardInfo->CardType = (uint8_t)(hsd->CardType); - pCardInfo->RCA = (uint16_t)(hsd->RCA); - - /* Byte 0 */ - tmp = (hsd->CSD[0] & 0xFF000000U) >> 24; - pCardInfo->SD_csd.CSDStruct = (uint8_t)((tmp & 0xC0) >> 6); - pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2); - pCardInfo->SD_csd.Reserved1 = tmp & 0x03; - - /* Byte 1 */ - tmp = (hsd->CSD[0] & 0x00FF0000) >> 16; - pCardInfo->SD_csd.TAAC = (uint8_t)tmp; - - /* Byte 2 */ - tmp = (hsd->CSD[0] & 0x0000FF00) >> 8; - pCardInfo->SD_csd.NSAC = (uint8_t)tmp; - - /* Byte 3 */ - tmp = hsd->CSD[0] & 0x000000FF; - pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp; - - /* Byte 4 */ - tmp = (hsd->CSD[1] & 0xFF000000U) >> 24; - pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4); - - /* Byte 5 */ - tmp = (hsd->CSD[1] & 0x00FF0000U) >> 16; - pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4); - pCardInfo->SD_csd.RdBlockLen = (uint8_t)(tmp & 0x0F); - - /* Byte 6 */ - tmp = (hsd->CSD[1] & 0x0000FF00U) >> 8; - pCardInfo->SD_csd.PartBlockRead = (uint8_t)((tmp & 0x80) >> 7); - pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6); - pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5); - pCardInfo->SD_csd.DSRImpl = (uint8_t)((tmp & 0x10) >> 4); - pCardInfo->SD_csd.Reserved2 = 0; /*!< Reserved */ - - if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0)) - { - pCardInfo->SD_csd.DeviceSize = (tmp & 0x03) << 10; - - /* Byte 7 */ - tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU); - pCardInfo->SD_csd.DeviceSize |= (tmp) << 2; - - /* Byte 8 */ - tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24); - pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6; - - pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; - pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07); - - /* Byte 9 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16); - pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; - pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; - pCardInfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1; - /* Byte 10 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8); - pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7; - - pCardInfo->CardCapacity = (pCardInfo->SD_csd.DeviceSize + 1) ; - pCardInfo->CardCapacity *= (1 << (pCardInfo->SD_csd.DeviceSizeMul + 2)); - pCardInfo->CardBlockSize = 1 << (pCardInfo->SD_csd.RdBlockLen); - pCardInfo->CardCapacity *= pCardInfo->CardBlockSize; - } - else if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - /* Byte 7 */ - tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU); - pCardInfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16; - - /* Byte 8 */ - tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24); - - pCardInfo->SD_csd.DeviceSize |= (tmp << 8); - - /* Byte 9 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16); - - pCardInfo->SD_csd.DeviceSize |= (tmp); - - /* Byte 10 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8); - - pCardInfo->CardCapacity = (uint64_t)(((uint64_t)pCardInfo->SD_csd.DeviceSize + 1) * 512 * 1024); - pCardInfo->CardBlockSize = 512; - } - else - { - /* Not supported card type */ - errorstate = SD_ERROR; - } - - pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6; - pCardInfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1; - - /* Byte 11 */ - tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF); - pCardInfo->SD_csd.EraseGrMul |= (tmp & 0x80) >> 7; - pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7F); - - /* Byte 12 */ - tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000U) >> 24); - pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7; - pCardInfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5; - pCardInfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2; - pCardInfo->SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2; - - /* Byte 13 */ - tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16); - pCardInfo->SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6; - pCardInfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5; - pCardInfo->SD_csd.Reserved3 = 0; - pCardInfo->SD_csd.ContentProtectAppli = (tmp & 0x01); - - /* Byte 14 */ - tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8); - pCardInfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7; - pCardInfo->SD_csd.CopyFlag = (tmp & 0x40) >> 6; - pCardInfo->SD_csd.PermWrProtect = (tmp & 0x20) >> 5; - pCardInfo->SD_csd.TempWrProtect = (tmp & 0x10) >> 4; - pCardInfo->SD_csd.FileFormat = (tmp & 0x0C) >> 2; - pCardInfo->SD_csd.ECC = (tmp & 0x03); - - /* Byte 15 */ - tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF); - pCardInfo->SD_csd.CSD_CRC = (tmp & 0xFE) >> 1; - pCardInfo->SD_csd.Reserved4 = 1; - - /* Byte 0 */ - tmp = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24); - pCardInfo->SD_cid.ManufacturerID = tmp; - - /* Byte 1 */ - tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16); - pCardInfo->SD_cid.OEM_AppliID = tmp << 8; - - /* Byte 2 */ - tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8); - pCardInfo->SD_cid.OEM_AppliID |= tmp; - - /* Byte 3 */ - tmp = (uint8_t)(hsd->CID[0] & 0x000000FF); - pCardInfo->SD_cid.ProdName1 = tmp << 24; - - /* Byte 4 */ - tmp = (uint8_t)((hsd->CID[1] & 0xFF000000U) >> 24); - pCardInfo->SD_cid.ProdName1 |= tmp << 16; - - /* Byte 5 */ - tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16); - pCardInfo->SD_cid.ProdName1 |= tmp << 8; - - /* Byte 6 */ - tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8); - pCardInfo->SD_cid.ProdName1 |= tmp; - - /* Byte 7 */ - tmp = (uint8_t)(hsd->CID[1] & 0x000000FF); - pCardInfo->SD_cid.ProdName2 = tmp; - - /* Byte 8 */ - tmp = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24); - pCardInfo->SD_cid.ProdRev = tmp; - - /* Byte 9 */ - tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16); - pCardInfo->SD_cid.ProdSN = tmp << 24; - - /* Byte 10 */ - tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8); - pCardInfo->SD_cid.ProdSN |= tmp << 16; - - /* Byte 11 */ - tmp = (uint8_t)(hsd->CID[2] & 0x000000FF); - pCardInfo->SD_cid.ProdSN |= tmp << 8; - - /* Byte 12 */ - tmp = (uint8_t)((hsd->CID[3] & 0xFF000000U) >> 24); - pCardInfo->SD_cid.ProdSN |= tmp; - - /* Byte 13 */ - tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16); - pCardInfo->SD_cid.Reserved1 |= (tmp & 0xF0) >> 4; - pCardInfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8; - - /* Byte 14 */ - tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8); - pCardInfo->SD_cid.ManufactDate |= tmp; - - /* Byte 15 */ - tmp = (uint8_t)(hsd->CID[3] & 0x000000FF); - pCardInfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1; - pCardInfo->SD_cid.Reserved2 = 1; - - return errorstate; -} - -/** - * @brief Enables wide bus operation for the requested card if supported by - * card. - * @param hsd: SD handle - * @param WideMode: Specifies the SD card wide bus mode - * This parameter can be one of the following values: - * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer (Only for MMC) - * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer - * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - SDMMC_InitTypeDef tmpinit; - - /* MMC Card does not support this feature */ - if (hsd->CardType == MULTIMEDIA_CARD) - { - errorstate = SD_UNSUPPORTED_FEATURE; - - return errorstate; - } - else if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ - (hsd->CardType == HIGH_CAPACITY_SD_CARD)) - { - if (WideMode == SDMMC_BUS_WIDE_8B) - { - errorstate = SD_UNSUPPORTED_FEATURE; - } - else if (WideMode == SDMMC_BUS_WIDE_4B) - { - errorstate = SD_WideBus_Enable(hsd); - } - else if (WideMode == SDMMC_BUS_WIDE_1B) - { - errorstate = SD_WideBus_Disable(hsd); - } - else - { - /* WideMode is not a valid argument*/ - errorstate = SD_INVALID_PARAMETER; - } - - if (errorstate == SD_OK) - { - /* Configure the SDMMC peripheral */ - tmpinit.ClockEdge = hsd->Init.ClockEdge; - tmpinit.ClockBypass = hsd->Init.ClockBypass; - tmpinit.ClockPowerSave = hsd->Init.ClockPowerSave; - tmpinit.BusWide = WideMode; - tmpinit.HardwareFlowControl = hsd->Init.HardwareFlowControl; - tmpinit.ClockDiv = hsd->Init.ClockDiv; - SDMMC_Init(hsd->Instance, tmpinit); - } - } - - return errorstate; -} - -/** - * @brief Aborts an ongoing data transfer. - * @param hsd: SD handle - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - /* Send CMD12 STOP_TRANSMISSION */ - sdmmc_cmdinitstructure.Argument = 0; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_STOP_TRANSMISSION; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION); - - return errorstate; -} - -/** - * @brief Switches the SD card to High Speed mode. - * This API must be used after "Transfer State" - * @note This operation should be followed by the configuration - * of PLL to have SDMMCCK clock between 67 and 75 MHz - * @param hsd: SD handle - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - SDMMC_DataInitTypeDef sdmmc_datainitstructure; - - uint8_t SD_hs[64] = {0}; - uint32_t SD_scr[2] = {0, 0}; - uint32_t SD_SPEC = 0 ; - uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs; - - /* Initialize the Data control register */ - hsd->Instance->DCTRL = 0; - - /* Get SCR Register */ - errorstate = SD_FindSCR(hsd, SD_scr); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Test the Version supported by the card*/ - SD_SPEC = (SD_scr[1] & 0x01000000) | (SD_scr[1] & 0x02000000); - - if (SD_SPEC != SD_ALLZERO) - { - /* Set Block Size for Card */ - sdmmc_cmdinitstructure.Argument = (uint32_t)64; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdmmc_datainitstructure.DataLength = 64; - sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ; - sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure); - - /* Send CMD6 switch mode */ - sdmmc_cmdinitstructure.Argument = 0x80FFFF01U; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_HS_SWITCH; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH); - - if (errorstate != SD_OK) - { - return errorstate; - } - - while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND)) - { - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) - { - for (count = 0; count < 8; count++) - { - *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance); - } - - tempbuff += 8; - } - } - - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); - - errorstate = SD_DATA_TIMEOUT; - - return errorstate; - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); - - errorstate = SD_DATA_CRC_FAIL; - - return errorstate; - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); - - errorstate = SD_RX_OVERRUN; - - return errorstate; - } - else - { - /* No error flag set */ - } - - count = SD_DATATIMEOUT; - - while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0)) - { - *tempbuff = SDMMC_ReadFIFO(hsd->Instance); - tempbuff++; - count--; - } - - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - /* Test if the switch mode HS is ok */ - if ((SD_hs[13]& 2) != 2) - { - errorstate = SD_UNSUPPORTED_FEATURE; - } - } - - return errorstate; -} - -/** - * @} - */ - -/** @addtogroup SD_Exported_Functions_Group4 - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in runtime the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the current SD card's status. - * @param hsd: SD handle - * @param pSDstatus: Pointer to the buffer that will contain the SD card status - * SD Status register) - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - SDMMC_DataInitTypeDef sdmmc_datainitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t count = 0; - - /* Check SD response */ - if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) - { - errorstate = SD_LOCK_UNLOCK_FAILED; - - return errorstate; - } - - /* Set block size for card if it is not equal to current block size for card */ - sdmmc_cmdinitstructure.Argument = 64; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Send CMD55 */ - sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdmmc_datainitstructure.DataLength = 64; - sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B; - sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure); - - /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */ - sdmmc_cmdinitstructure.Argument = 0; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_STATUS; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STATUS); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Get status data */ - while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND)) - { - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) - { - for (count = 0; count < 8; count++) - { - *(pSDstatus + count) = SDMMC_ReadFIFO(hsd->Instance); - } - - pSDstatus += 8; - } - } - - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); - - errorstate = SD_DATA_TIMEOUT; - - return errorstate; - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); - - errorstate = SD_DATA_CRC_FAIL; - - return errorstate; - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); - - errorstate = SD_RX_OVERRUN; - - return errorstate; - } - else - { - /* No error flag set */ - } - - count = SD_DATATIMEOUT; - while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0)) - { - *pSDstatus = SDMMC_ReadFIFO(hsd->Instance); - pSDstatus++; - count--; - } - - /* Clear all the static status flags*/ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - return errorstate; -} - -/** - * @brief Gets the current sd card data status. - * @param hsd: SD handle - * @retval Data Transfer state - */ -HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd) -{ - HAL_SD_CardStateTypedef cardstate = SD_CARD_TRANSFER; - - /* Get SD card state */ - cardstate = SD_GetState(hsd); - - /* Find SD status according to card state*/ - if (cardstate == SD_CARD_TRANSFER) - { - return SD_TRANSFER_OK; - } - else if(cardstate == SD_CARD_ERROR) - { - return SD_TRANSFER_ERROR; - } - else - { - return SD_TRANSFER_BUSY; - } -} - -/** - * @brief Gets the SD card status. - * @param hsd: SD handle - * @param pCardStatus: Pointer to the HAL_SD_CardStatusTypedef structure that - * will contain the SD card status information - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t tmp = 0; - uint32_t sd_status[16]; - - errorstate = HAL_SD_SendSDStatus(hsd, sd_status); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Byte 0 */ - tmp = (sd_status[0] & 0xC0) >> 6; - pCardStatus->DAT_BUS_WIDTH = (uint8_t)tmp; - - /* Byte 0 */ - tmp = (sd_status[0] & 0x20) >> 5; - pCardStatus->SECURED_MODE = (uint8_t)tmp; - - /* Byte 2 */ - tmp = (sd_status[0] & 0x00FF0000) >> 16; - pCardStatus->SD_CARD_TYPE = (uint16_t)(tmp << 8); - - /* Byte 3 */ - tmp = (sd_status[0] & 0xFF000000) >> 24; - pCardStatus->SD_CARD_TYPE |= (uint16_t)tmp; - - /* Byte 4 */ - tmp = (sd_status[1] & 0xFF); - pCardStatus->SIZE_OF_PROTECTED_AREA = (uint32_t)(tmp << 24); - - /* Byte 5 */ - tmp = (sd_status[1] & 0xFF00) >> 8; - pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)(tmp << 16); - - /* Byte 6 */ - tmp = (sd_status[1] & 0xFF0000) >> 16; - pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)(tmp << 8); - - /* Byte 7 */ - tmp = (sd_status[1] & 0xFF000000) >> 24; - pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)tmp; - - /* Byte 8 */ - tmp = (sd_status[2] & 0xFF); - pCardStatus->SPEED_CLASS = (uint8_t)tmp; - - /* Byte 9 */ - tmp = (sd_status[2] & 0xFF00) >> 8; - pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp; - - /* Byte 10 */ - tmp = (sd_status[2] & 0xF00000) >> 20; - pCardStatus->AU_SIZE = (uint8_t)tmp; - - /* Byte 11 */ - tmp = (sd_status[2] & 0xFF000000) >> 24; - pCardStatus->ERASE_SIZE = (uint16_t)(tmp << 8); - - /* Byte 12 */ - tmp = (sd_status[3] & 0xFF); - pCardStatus->ERASE_SIZE |= (uint16_t)tmp; - - /* Byte 13 */ - tmp = (sd_status[3] & 0xFC00) >> 10; - pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp; - - /* Byte 13 */ - tmp = (sd_status[3] & 0x0300) >> 8; - pCardStatus->ERASE_OFFSET = (uint8_t)tmp; - - return errorstate; -} - -/** - * @} - */ - -/** - * @} - */ - -/* Private function ----------------------------------------------------------*/ -/** @addtogroup SD_Private_Functions - * @{ - */ - -/** - * @brief SD DMA transfer complete Rx callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma) -{ - SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* DMA transfer is complete */ - hsd->DmaTransferCplt = 1; - - /* Wait until SD transfer is complete */ - while(hsd->SdTransferCplt == 0) - { - } - - /* Disable the DMA channel */ - HAL_DMA_Abort(hdma); - - /* Transfer complete user callback */ - HAL_SD_DMA_RxCpltCallback(hsd->hdmarx); -} - -/** - * @brief SD DMA transfer Error Rx callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SD_DMA_RxError(DMA_HandleTypeDef *hdma) -{ - SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Transfer complete user callback */ - HAL_SD_DMA_RxErrorCallback(hsd->hdmarx); -} - -/** - * @brief SD DMA transfer complete Tx callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma) -{ - SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* DMA transfer is complete */ - hsd->DmaTransferCplt = 1; - - /* Wait until SD transfer is complete */ - while(hsd->SdTransferCplt == 0) - { - } - - /* Disable the DMA channel */ - HAL_DMA_Abort(hdma); - - /* Transfer complete user callback */ - HAL_SD_DMA_TxCpltCallback(hsd->hdmatx); -} - -/** - * @brief SD DMA transfer Error Tx callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SD_DMA_TxError(DMA_HandleTypeDef *hdma) -{ - SD_HandleTypeDef *hsd = ( SD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Transfer complete user callback */ - HAL_SD_DMA_TxErrorCallback(hsd->hdmatx); -} - -/** - * @brief Returns the SD current state. - * @param hsd: SD handle - * @retval SD card current state - */ -static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd) -{ - uint32_t resp1 = 0; - - if (SD_SendStatus(hsd, &resp1) != SD_OK) - { - return SD_CARD_ERROR; - } - else - { - return (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F); - } -} - -/** - * @brief Initializes all cards or single card as the case may be Card(s) come - * into standby state. - * @param hsd: SD handle - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint16_t sd_rca = 1; - - if(SDMMC_GetPowerState(hsd->Instance) == 0) /* Power off */ - { - errorstate = SD_REQUEST_NOT_APPLICABLE; - - return errorstate; - } - - if(hsd->CardType != SECURE_DIGITAL_IO_CARD) - { - /* Send CMD2 ALL_SEND_CID */ - sdmmc_cmdinitstructure.Argument = 0; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_ALL_SEND_CID; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_LONG; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp2Error(hsd); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Get Card identification number data */ - hsd->CID[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - hsd->CID[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); - hsd->CID[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); - hsd->CID[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); - } - - if((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ - (hsd->CardType == SECURE_DIGITAL_IO_COMBO_CARD) || (hsd->CardType == HIGH_CAPACITY_SD_CARD)) - { - /* Send CMD3 SET_REL_ADDR with argument 0 */ - /* SD Card publishes its RCA. */ - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_REL_ADDR; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca); - - if(errorstate != SD_OK) - { - return errorstate; - } - } - - if (hsd->CardType != SECURE_DIGITAL_IO_CARD) - { - /* Get the SD card RCA */ - hsd->RCA = sd_rca; - - /* Send CMD9 SEND_CSD with argument as card's RCA */ - sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SEND_CSD; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_LONG; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp2Error(hsd); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Get Card Specific Data */ - hsd->CSD[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - hsd->CSD[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); - hsd->CSD[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); - hsd->CSD[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); - } - - /* All cards are initialized */ - return errorstate; -} - -/** - * @brief Selects od Deselects the corresponding card. - * @param hsd: SD handle - * @param addr: Address of the card to be selected - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - /* Send CMD7 SDMMC_SEL_DESEL_CARD */ - sdmmc_cmdinitstructure.Argument = (uint32_t)addr; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SEL_DESEL_CARD; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD); - - return errorstate; -} - -/** - * @brief Enquires cards about their operating voltage and configures clock - * controls and stores SD information that will be needed in future - * in the SD handle. - * @param hsd: SD handle - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - __IO HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t response = 0, count = 0, validvoltage = 0; - uint32_t sdtype = SD_STD_CAPACITY; - - /* Power ON Sequence -------------------------------------------------------*/ - /* Disable SDMMC Clock */ - __HAL_SD_SDMMC_DISABLE(hsd); - - /* Set Power State to ON */ - SDMMC_PowerState_ON(hsd->Instance); - - /* 1ms: required power up waiting time before starting the SD initialization - sequence */ - HAL_Delay(1); - - /* Enable SDMMC Clock */ - __HAL_SD_SDMMC_ENABLE(hsd); - - /* CMD0: GO_IDLE_STATE -----------------------------------------------------*/ - /* No CMD response required */ - sdmmc_cmdinitstructure.Argument = 0; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_GO_IDLE_STATE; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_NO; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdError(hsd); - - if(errorstate != SD_OK) - { - /* CMD Response Timeout (wait for CMDSENT flag) */ - return errorstate; - } - - /* CMD8: SEND_IF_COND ------------------------------------------------------*/ - /* Send CMD8 to verify SD card interface operating condition */ - /* Argument: - [31:12]: Reserved (shall be set to '0') - - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) - - [7:0]: Check Pattern (recommended 0xAA) */ - /* CMD Response: R7 */ - sdmmc_cmdinitstructure.Argument = SD_CHECK_PATTERN; - sdmmc_cmdinitstructure.CmdIndex = SD_SDMMC_SEND_IF_COND; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp7Error(hsd); - - if (errorstate == SD_OK) - { - /* SD Card 2.0 */ - hsd->CardType = STD_CAPACITY_SD_CARD_V2_0; - sdtype = SD_HIGH_CAPACITY; - } - - /* Send CMD55 */ - sdmmc_cmdinitstructure.Argument = 0; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - /* If errorstate is Command Timeout, it is a MMC card */ - /* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch) - or SD card 1.x */ - if(errorstate == SD_OK) - { - /* SD CARD */ - /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ - while((!validvoltage) && (count < SD_MAX_VOLT_TRIAL)) - { - - /* SEND CMD55 APP_CMD with RCA as 0 */ - sdmmc_cmdinitstructure.Argument = 0; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Send CMD41 */ - sdmmc_cmdinitstructure.Argument = SD_VOLTAGE_WINDOW_SD | sdtype; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_OP_COND; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp3Error(hsd); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Get command response */ - response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - - /* Get operating voltage*/ - validvoltage = (((response >> 31) == 1) ? 1 : 0); - - count++; - } - - if(count >= SD_MAX_VOLT_TRIAL) - { - errorstate = SD_INVALID_VOLTRANGE; - - return errorstate; - } - - if((response & SD_HIGH_CAPACITY) == SD_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ - { - hsd->CardType = HIGH_CAPACITY_SD_CARD; - } - - } /* else MMC Card */ - - return errorstate; -} - -/** - * @brief Turns the SDMMC output signals off. - * @param hsd: SD handle - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - - /* Set Power State to OFF */ - SDMMC_PowerState_OFF(hsd->Instance); - - return errorstate; -} - -/** - * @brief Returns the current card's status. - * @param hsd: SD handle - * @param pCardStatus: pointer to the buffer that will contain the SD card - * status (Card Status register) - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - if(pCardStatus == NULL) - { - errorstate = SD_INVALID_PARAMETER; - - return errorstate; - } - - /* Send Status command */ - sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Get SD card status */ - *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - - return errorstate; -} - -/** - * @brief Checks for error conditions for CMD0. - * @param hsd: SD handle - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t timeout, tmp; - - timeout = SDMMC_CMD0TIMEOUT; - - tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDSENT); - - while((timeout > 0) && (!tmp)) - { - tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDSENT); - timeout--; - } - - if(timeout == 0) - { - errorstate = SD_CMD_RSP_TIMEOUT; - return errorstate; - } - - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - return errorstate; -} - -/** - * @brief Checks for error conditions for R7 response. - * @param hsd: SD handle - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd) -{ - HAL_SD_ErrorTypedef errorstate = SD_ERROR; - uint32_t timeout = SDMMC_CMD0TIMEOUT, tmp; - - tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT); - - while((!tmp) && (timeout > 0)) - { - tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT); - timeout--; - } - - tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT); - - if((timeout == 0) || tmp) - { - /* Card is not V2.0 compliant or card does not support the set voltage range */ - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT); - - return errorstate; - } - - if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDREND)) - { - /* Card is SD V2.0 compliant */ - errorstate = SD_OK; - - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CMDREND); - - return errorstate; - } - - return errorstate; -} - -/** - * @brief Checks for error conditions for R1 response. - * @param hsd: SD handle - * @param SD_CMD: The sent command index - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t response_r1; - - while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) - { - } - - if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT)) - { - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT); - - return errorstate; - } - else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL)) - { - errorstate = SD_CMD_CRC_FAIL; - - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL); - - return errorstate; - } - - /* Check response received is of desired command */ - if(SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD) - { - errorstate = SD_ILLEGAL_CMD; - - return errorstate; - } - - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - /* We have received response, retrieve it for analysis */ - response_r1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - - if((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO) - { - return errorstate; - } - - if((response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE) - { - return(SD_ADDR_OUT_OF_RANGE); - } - - if((response_r1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED) - { - return(SD_ADDR_MISALIGNED); - } - - if((response_r1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR) - { - return(SD_BLOCK_LEN_ERR); - } - - if((response_r1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR) - { - return(SD_ERASE_SEQ_ERR); - } - - if((response_r1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM) - { - return(SD_BAD_ERASE_PARAM); - } - - if((response_r1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION) - { - return(SD_WRITE_PROT_VIOLATION); - } - - if((response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED) - { - return(SD_LOCK_UNLOCK_FAILED); - } - - if((response_r1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED) - { - return(SD_COM_CRC_FAILED); - } - - if((response_r1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD) - { - return(SD_ILLEGAL_CMD); - } - - if((response_r1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED) - { - return(SD_CARD_ECC_FAILED); - } - - if((response_r1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR) - { - return(SD_CC_ERROR); - } - - if((response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR) - { - return(SD_GENERAL_UNKNOWN_ERROR); - } - - if((response_r1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN) - { - return(SD_STREAM_READ_UNDERRUN); - } - - if((response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN) - { - return(SD_STREAM_WRITE_OVERRUN); - } - - if((response_r1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE) - { - return(SD_CID_CSD_OVERWRITE); - } - - if((response_r1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP) - { - return(SD_WP_ERASE_SKIP); - } - - if((response_r1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED) - { - return(SD_CARD_ECC_DISABLED); - } - - if((response_r1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET) - { - return(SD_ERASE_RESET); - } - - if((response_r1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR) - { - return(SD_AKE_SEQ_ERROR); - } - - return errorstate; -} - -/** - * @brief Checks for error conditions for R3 (OCR) response. - * @param hsd: SD handle - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - - while (!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) - { - } - - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT)) - { - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT); - - return errorstate; - } - - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - return errorstate; -} - -/** - * @brief Checks for error conditions for R2 (CID or CSD) response. - * @param hsd: SD handle - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - - while (!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) - { - } - - if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT)) - { - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT); - - return errorstate; - } - else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL)) - { - errorstate = SD_CMD_CRC_FAIL; - - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL); - - return errorstate; - } - else - { - /* No error flag set */ - } - - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - return errorstate; -} - -/** - * @brief Checks for error conditions for R6 (RCA) response. - * @param hsd: SD handle - * @param SD_CMD: The sent command index - * @param pRCA: Pointer to the variable that will contain the SD card relative - * address RCA - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t response_r1; - - while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) - { - } - - if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT)) - { - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT); - - return errorstate; - } - else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL)) - { - errorstate = SD_CMD_CRC_FAIL; - - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL); - - return errorstate; - } - else - { - /* No error flag set */ - } - - /* Check response received is of desired command */ - if(SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD) - { - errorstate = SD_ILLEGAL_CMD; - - return errorstate; - } - - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - /* We have received response, retrieve it. */ - response_r1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - - if((response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO) - { - *pRCA = (uint16_t) (response_r1 >> 16); - - return errorstate; - } - - if((response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR) - { - return(SD_GENERAL_UNKNOWN_ERROR); - } - - if((response_r1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD) - { - return(SD_ILLEGAL_CMD); - } - - if((response_r1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED) - { - return(SD_COM_CRC_FAILED); - } - - return errorstate; -} - -/** - * @brief Enables the SDMMC wide bus mode. - * @param hsd: SD handle - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - uint32_t scr[2] = {0, 0}; - - if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) - { - errorstate = SD_LOCK_UNLOCK_FAILED; - - return errorstate; - } - - /* Get SCR Register */ - errorstate = SD_FindSCR(hsd, scr); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* If requested card supports wide bus operation */ - if((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO) - { - /* Send CMD55 APP_CMD with argument as card's RCA.*/ - sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ - sdmmc_cmdinitstructure.Argument = 2; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH); - - if(errorstate != SD_OK) - { - return errorstate; - } - - return errorstate; - } - else - { - errorstate = SD_REQUEST_NOT_APPLICABLE; - - return errorstate; - } -} - -/** - * @brief Disables the SDMMC wide bus mode. - * @param hsd: SD handle - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - uint32_t scr[2] = {0, 0}; - - if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) - { - errorstate = SD_LOCK_UNLOCK_FAILED; - - return errorstate; - } - - /* Get SCR Register */ - errorstate = SD_FindSCR(hsd, scr); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* If requested card supports 1 bit mode operation */ - if((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO) - { - /* Send CMD55 APP_CMD with argument as card's RCA */ - sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */ - sdmmc_cmdinitstructure.Argument = 0; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH); - - if(errorstate != SD_OK) - { - return errorstate; - } - - return errorstate; - } - else - { - errorstate = SD_REQUEST_NOT_APPLICABLE; - - return errorstate; - } -} - - -/** - * @brief Finds the SD card SCR register value. - * @param hsd: SD handle - * @param pSCR: pointer to the buffer that will contain the SCR value - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - SDMMC_DataInitTypeDef sdmmc_datainitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t index = 0; - uint32_t tempscr[2] = {0, 0}; - - /* Set Block Size To 8 Bytes */ - /* Send CMD55 APP_CMD with argument as card's RCA */ - sdmmc_cmdinitstructure.Argument = (uint32_t)8; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Send CMD55 APP_CMD with argument as card's RCA */ - sdmmc_cmdinitstructure.Argument = (uint32_t)((hsd->RCA) << 16); - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - if(errorstate != SD_OK) - { - return errorstate; - } - sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdmmc_datainitstructure.DataLength = 8; - sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B; - sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure); - - /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ - sdmmc_cmdinitstructure.Argument = 0; - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_SEND_SCR; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR); - - if(errorstate != SD_OK) - { - return errorstate; - } - - while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND)) - { - if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) - { - *(tempscr + index) = SDMMC_ReadFIFO(hsd->Instance); - index++; - } - } - - if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); - - errorstate = SD_DATA_TIMEOUT; - - return errorstate; - } - else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); - - errorstate = SD_DATA_CRC_FAIL; - - return errorstate; - } - else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) - { - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); - - errorstate = SD_RX_OVERRUN; - - return errorstate; - } - else - { - /* No error flag set */ - } - - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - *(pSCR + 1) = ((tempscr[0] & SD_0TO7BITS) << 24) | ((tempscr[0] & SD_8TO15BITS) << 8) |\ - ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24); - - *(pSCR) = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) |\ - ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24); - - return errorstate; -} - -/** - * @brief Checks if the SD card is in programming state. - * @param hsd: SD handle - * @param pStatus: pointer to the variable that will contain the SD card state - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - __IO uint32_t responseR1 = 0; - - sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS; - sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); - - while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) - { - } - - if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT)) - { - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT); - - return errorstate; - } - else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL)) - { - errorstate = SD_CMD_CRC_FAIL; - - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL); - - return errorstate; - } - else - { - /* No error flag set */ - } - - /* Check response received is of desired command */ - if((uint32_t)SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD_SEND_STATUS) - { - errorstate = SD_ILLEGAL_CMD; - - return errorstate; - } - - /* Clear all the static flags */ - __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - - /* We have received response, retrieve it for analysis */ - responseR1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - - /* Find out card status */ - *pStatus = (uint8_t)((responseR1 >> 9) & 0x0000000F); - - if((responseR1 & SD_OCR_ERRORBITS) == SD_ALLZERO) - { - return errorstate; - } - - if((responseR1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE) - { - return(SD_ADDR_OUT_OF_RANGE); - } - - if((responseR1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED) - { - return(SD_ADDR_MISALIGNED); - } - - if((responseR1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR) - { - return(SD_BLOCK_LEN_ERR); - } - - if((responseR1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR) - { - return(SD_ERASE_SEQ_ERR); - } - - if((responseR1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM) - { - return(SD_BAD_ERASE_PARAM); - } - - if((responseR1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION) - { - return(SD_WRITE_PROT_VIOLATION); - } - - if((responseR1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED) - { - return(SD_LOCK_UNLOCK_FAILED); - } - - if((responseR1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED) - { - return(SD_COM_CRC_FAILED); - } - - if((responseR1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD) - { - return(SD_ILLEGAL_CMD); - } - - if((responseR1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED) - { - return(SD_CARD_ECC_FAILED); - } - - if((responseR1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR) - { - return(SD_CC_ERROR); - } - - if((responseR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR) - { - return(SD_GENERAL_UNKNOWN_ERROR); - } - - if((responseR1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN) - { - return(SD_STREAM_READ_UNDERRUN); - } - - if((responseR1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN) - { - return(SD_STREAM_WRITE_OVERRUN); - } - - if((responseR1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE) - { - return(SD_CID_CSD_OVERWRITE); - } - - if((responseR1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP) - { - return(SD_WP_ERASE_SKIP); - } - - if((responseR1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED) - { - return(SD_CARD_ECC_DISABLED); - } - - if((responseR1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET) - { - return(SD_ERASE_RESET); - } - - if((responseR1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR) - { - return(SD_AKE_SEQ_ERROR); - } - - return errorstate; -} - -/** - * @} - */ - -#endif /* HAL_SD_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c deleted file mode 100644 index 8db4670..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c +++ /dev/null @@ -1,859 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_sdram.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief SDRAM HAL module driver. - * This file provides a generic firmware to drive SDRAM memories mounted - * as external device. - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - This driver is a generic layered driver which contains a set of APIs used to - control SDRAM memories. It uses the FMC layer functions to interface - with SDRAM devices. - The following sequence should be followed to configure the FMC to interface - with SDRAM memories: - - (#) Declare a SDRAM_HandleTypeDef handle structure, for example: - SDRAM_HandleTypeDef hdsram - - (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed - values of the structure member. - - (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined - base register instance for NOR or SDRAM device - - (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example: - FMC_SDRAM_TimingTypeDef Timing; - and fill its fields with the allowed values of the structure member. - - (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function - performs the following sequence: - - (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit() - (##) Control register configuration using the FMC SDRAM interface function - FMC_SDRAM_Init() - (##) Timing register configuration using the FMC SDRAM interface function - FMC_SDRAM_Timing_Init() - (##) Program the SDRAM external device by applying its initialization sequence - according to the device plugged in your hardware. This step is mandatory - for accessing the SDRAM device. - - (#) At this stage you can perform read/write accesses from/to the memory connected - to the SDRAM Bank. You can perform either polling or DMA transfer using the - following APIs: - (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access - (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer - - (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/ - HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or - the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM - device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef - structure. - - (#) You can continuously monitor the SDRAM device HAL state by calling the function - HAL_SDRAM_GetState() - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup SDRAM SDRAM - * @brief SDRAM driver modules - * @{ - */ -#ifdef HAL_SDRAM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions - * @{ - */ - -/** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - ============================================================================== - ##### SDRAM Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to initialize/de-initialize - the SDRAM memory - -@endverbatim - * @{ - */ - -/** - * @brief Performs the SDRAM device initialization sequence. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param Timing: Pointer to SDRAM control timing structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) -{ - /* Check the SDRAM handle parameter */ - if(hsdram == NULL) - { - return HAL_ERROR; - } - - if(hsdram->State == HAL_SDRAM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hsdram->Lock = HAL_UNLOCKED; - /* Initialize the low level hardware (MSP) */ - HAL_SDRAM_MspInit(hsdram); - } - - /* Initialize the SDRAM controller state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Initialize SDRAM control Interface */ - FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); - - /* Initialize SDRAM timing Interface */ - FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); - - /* Update the SDRAM controller state */ - hsdram->State = HAL_SDRAM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Perform the SDRAM device initialization sequence. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) -{ - /* Initialize the low level hardware (MSP) */ - HAL_SDRAM_MspDeInit(hsdram); - - /* Configure the SDRAM registers with their reset values */ - FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank); - - /* Reset the SDRAM controller state */ - hsdram->State = HAL_SDRAM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hsdram); - - return HAL_OK; -} - -/** - * @brief SDRAM MSP Init. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @retval None - */ -__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsdram); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_SDRAM_MspInit could be implemented in the user file - */ -} - -/** - * @brief SDRAM MSP DeInit. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @retval None - */ -__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsdram); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_SDRAM_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief This function handles SDRAM refresh error interrupt request. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @retval HAL status -*/ -void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) -{ - /* Check SDRAM interrupt Rising edge flag */ - if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT)) - { - /* SDRAM refresh error interrupt callback */ - HAL_SDRAM_RefreshErrorCallback(hsdram); - - /* Clear SDRAM refresh error interrupt pending bit */ - __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR); - } -} - -/** - * @brief SDRAM Refresh error callback. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @retval None - */ -__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsdram); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file - */ -} - -/** - * @brief DMA transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file - */ -} - -/** - * @brief DMA transfer complete error callback. - * @param hdma: DMA handle - * @retval None - */ -__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions - * @brief Input Output and memory control functions - * - @verbatim - ============================================================================== - ##### SDRAM Input and Output functions ##### - ============================================================================== - [..] - This section provides functions allowing to use and control the SDRAM memory - -@endverbatim - * @{ - */ - -/** - * @brief Reads 8-bit data buffer from the SDRAM memory. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) -{ - __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; - - /* Process Locked */ - __HAL_LOCK(hsdram); - - /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) - { - return HAL_ERROR; - } - - /* Read data from source */ - for(; BufferSize != 0; BufferSize--) - { - *pDstBuffer = *(__IO uint8_t *)pSdramAddress; - pDstBuffer++; - pSdramAddress++; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - - return HAL_OK; -} - - -/** - * @brief Writes 8-bit data buffer to SDRAM memory. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) -{ - __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; - uint32_t tmp = 0; - - /* Process Locked */ - __HAL_LOCK(hsdram); - - /* Check the SDRAM controller state */ - tmp = hsdram->State; - - if(tmp == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) - { - return HAL_ERROR; - } - - /* Write data to memory */ - for(; BufferSize != 0; BufferSize--) - { - *(__IO uint8_t *)pSdramAddress = *pSrcBuffer; - pSrcBuffer++; - pSdramAddress++; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - - return HAL_OK; -} - - -/** - * @brief Reads 16-bit data buffer from the SDRAM memory. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) -{ - __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; - - /* Process Locked */ - __HAL_LOCK(hsdram); - - /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) - { - return HAL_ERROR; - } - - /* Read data from source */ - for(; BufferSize != 0; BufferSize--) - { - *pDstBuffer = *(__IO uint16_t *)pSdramAddress; - pDstBuffer++; - pSdramAddress++; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - - return HAL_OK; -} - -/** - * @brief Writes 16-bit data buffer to SDRAM memory. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) -{ - __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; - uint32_t tmp = 0; - - /* Process Locked */ - __HAL_LOCK(hsdram); - - /* Check the SDRAM controller state */ - tmp = hsdram->State; - - if(tmp == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) - { - return HAL_ERROR; - } - - /* Write data to memory */ - for(; BufferSize != 0; BufferSize--) - { - *(__IO uint16_t *)pSdramAddress = *pSrcBuffer; - pSrcBuffer++; - pSdramAddress++; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - - return HAL_OK; -} - -/** - * @brief Reads 32-bit data buffer from the SDRAM memory. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) -{ - __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; - - /* Process Locked */ - __HAL_LOCK(hsdram); - - /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) - { - return HAL_ERROR; - } - - /* Read data from source */ - for(; BufferSize != 0; BufferSize--) - { - *pDstBuffer = *(__IO uint32_t *)pSdramAddress; - pDstBuffer++; - pSdramAddress++; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - - return HAL_OK; -} - -/** - * @brief Writes 32-bit data buffer to SDRAM memory. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) -{ - __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; - uint32_t tmp = 0; - - /* Process Locked */ - __HAL_LOCK(hsdram); - - /* Check the SDRAM controller state */ - tmp = hsdram->State; - - if(tmp == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) - { - return HAL_ERROR; - } - - /* Write data to memory */ - for(; BufferSize != 0; BufferSize--) - { - *(__IO uint32_t *)pSdramAddress = *pSrcBuffer; - pSrcBuffer++; - pSdramAddress++; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - - return HAL_OK; -} - -/** - * @brief Reads a Words data from the SDRAM memory using DMA transfer. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) -{ - uint32_t tmp = 0; - - /* Process Locked */ - __HAL_LOCK(hsdram); - - /* Check the SDRAM controller state */ - tmp = hsdram->State; - - if(tmp == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - else if(tmp == HAL_SDRAM_STATE_PRECHARGED) - { - return HAL_ERROR; - } - - /* Configure DMA user callbacks */ - hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; - hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - - return HAL_OK; -} - -/** - * @brief Writes a Words data buffer to SDRAM memory using DMA transfer. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) -{ - uint32_t tmp = 0; - - /* Process Locked */ - __HAL_LOCK(hsdram); - - /* Check the SDRAM controller state */ - tmp = hsdram->State; - - if(tmp == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) - { - return HAL_ERROR; - } - - /* Configure DMA user callbacks */ - hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; - hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup SDRAM_Exported_Functions_Group3 Control functions - * @brief management functions - * -@verbatim - ============================================================================== - ##### SDRAM Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the SDRAM interface. - -@endverbatim - * @{ - */ - -/** - * @brief Enables dynamically SDRAM write protection. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) -{ - /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Enable write protection */ - FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank); - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; - - return HAL_OK; -} - -/** - * @brief Disables dynamically SDRAM write protection. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) -{ - /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Disable write protection */ - FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank); - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Sends Command to the SDRAM bank. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param Command: SDRAM command structure - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) -{ - /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Send SDRAM command */ - FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); - - /* Update the SDRAM controller state state */ - if(Command->CommandMode == FMC_SDRAM_CMD_PALL) - { - hsdram->State = HAL_SDRAM_STATE_PRECHARGED; - } - else - { - hsdram->State = HAL_SDRAM_STATE_READY; - } - - return HAL_OK; -} - -/** - * @brief Programs the SDRAM Memory Refresh rate. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param RefreshRate: The SDRAM refresh rate value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) -{ - /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Program the refresh rate */ - FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate); - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param AutoRefreshNumber: The SDRAM auto Refresh number - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber) -{ - /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Set the Auto-Refresh number */ - FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber); - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Returns the SDRAM memory current mode. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @retval The SDRAM memory mode. - */ -uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) -{ - /* Return the SDRAM memory current mode */ - return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank)); -} - -/** - * @} - */ - -/** @defgroup SDRAM_Exported_Functions_Group4 State functions - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### SDRAM State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the SDRAM controller - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the SDRAM state. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @retval HAL state - */ -HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) -{ - return hsdram->State; -} - -/** - * @} - */ - -/** - * @} - */ -#endif /* HAL_SDRAM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard.c deleted file mode 100644 index 3b3b7dc..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard.c +++ /dev/null @@ -1,1359 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_smartcard.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief SMARTCARD HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the SMARTCARD peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and Errors functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The SMARTCARD HAL driver can be used as follow: - - (#) Declare a SMARTCARD_HandleTypeDef handle structure. - (#) Associate a USART to the SMARTCARD handle hsc. - (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API: - (##) Enable the USARTx interface clock. - (##) SMARTCARD pins configuration: - (+++) Enable the clock for the SMARTCARD GPIOs. - (+++) Configure these SMARTCARD pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT() - and HAL_SMARTCARD_Receive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. - (+++) The specific USART interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process. - (##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA() - and HAL_SMARTCARD_Receive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx stream. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx Stream. - (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream. - - (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly, - the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission - error enabling or disabling in the hsc Init structure. - - (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...) - in the hsc AdvancedInit structure. - - (#) Initialize the SMARTCARD associated USART registers by calling - the HAL_SMARTCARD_Init() API. - - [..] - (@) HAL_SMARTCARD_Init() API also configure also the low level Hardware GPIO, CLOCK, CORTEX...etc) by - calling the customized HAL_SMARTCARD_MspInit() API. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup SMARTCARD SMARTCARD - * @brief HAL USART SMARTCARD module driver - * @{ - */ -#ifdef HAL_SMARTCARD_MODULE_ENABLED -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants - * @{ - */ -#define TEACK_REACK_TIMEOUT 1000U -#define HAL_SMARTCARD_TXDMA_TIMEOUTVALUE 22000U -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) -#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) -#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP)) -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT)) -/** - * @} - */ -/* Private macros -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup SMARTCARD_Private_Functions - * @{ - */ -static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma); -static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma); -static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc); -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); -static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsc); -static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc); -static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc); -static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc); -static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc); -static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc); -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions - * @{ - */ - -/** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USART - associated to the SmartCard. - (+) These parameters can be configured: - (++) Baud Rate - (++) Parity: parity should be enabled, - Frame Length is fixed to 8 bits plus parity. - (++) Receiver/transmitter modes - (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters) - (++) Prescaler value - (++) Guard bit time - (++) NACK enabling or disabling on transmission error - - (+) The following advanced features can be configured as well: - (++) TX and/or RX pin level inversion - (++) data logical level inversion - (++) RX and TX pins swap - (++) RX overrun detection disabling - (++) DMA disabling on RX error - (++) MSB first on communication line - (++) Time out enabling (and if activated, timeout value) - (++) Block length - (++) Auto-retry counter - - [..] - The HAL_SMARTCARD_Init() API follow respectively the USART (a)synchronous configuration procedures - (details for the procedures are available in reference manual). - -@endverbatim - - The USART frame format is given in the following table: - - +---------------------------------------------------------------+ - | M1M0 bits | PCE bit | USART frame | - |-----------------------|---------------------------------------| - | 01 | 1 | | SB | 8 bit data | PB | STB | | - +---------------------------------------------------------------+ - - * @{ - */ - -/** - * @brief Initializes the SMARTCARD mode according to the specified - * parameters in the SMARTCARD_InitTypeDef and create the associated handle . - * @param hsc: SMARTCARD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc) -{ - /* Check the SMARTCARD handle allocation */ - if(hsc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance)); - - if(hsc->gState == HAL_SMARTCARD_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hsc->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK, CORTEX */ - HAL_SMARTCARD_MspInit(hsc); - } - - hsc->gState = HAL_SMARTCARD_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_SMARTCARD_DISABLE(hsc); - - /* Set the SMARTCARD Communication parameters */ - SMARTCARD_SetConfig(hsc); - - if(hsc->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT) - { - SMARTCARD_AdvFeatureConfig(hsc); - } - - /* In SmartCard mode, the following bits must be kept cleared: - - LINEN in the USART_CR2 register, - - HDSEL and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(hsc->Instance->CR2, USART_CR2_LINEN); - CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); - - /* set the USART in SMARTCARD mode */ - SET_BIT(hsc->Instance->CR3, USART_CR3_SCEN); - - /* Enable the Peripheral */ - __HAL_SMARTCARD_ENABLE(hsc); - - /* TEACK and/or REACK to check before moving hsc->State to Ready */ - return (SMARTCARD_CheckIdleState(hsc)); -} - -/** - * @brief DeInitializes the SMARTCARD peripheral - * @param hsc: SMARTCARD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) -{ - /* Check the SMARTCARD handle allocation */ - if(hsc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance)); - - hsc->gState = HAL_SMARTCARD_STATE_BUSY; - - /* DeInit the low level hardware */ - HAL_SMARTCARD_MspDeInit(hsc); - - hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsc->gState = HAL_SMARTCARD_STATE_RESET; - hsc->RxState = HAL_SMARTCARD_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hsc); - - return HAL_OK; -} - -/** - * @brief SMARTCARD MSP Init - * @param hsc: SMARTCARD handle - * @retval None - */ - __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SMARTCARD_MspInit could be implemented in the user file - */ -} - -/** - * @brief SMARTCARD MSP DeInit - * @param hsc: SMARTCARD handle - * @retval None - */ - __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SMARTCARD_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions - * @brief SMARTCARD Transmit and Receive functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of functions allowing to manage the SMARTCARD data transfers. - - (#) There are two modes of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) No-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks - will be executed respectively at the end of the Transmit or Receive process - The HAL_SMARTCARD_ErrorCallback()user callback will be executed when a communication error is detected - - (#) Blocking mode API's are : - (+) HAL_SMARTCARD_Transmit() - (+) HAL_SMARTCARD_Receive() - - (#) Non-Blocking mode API's with Interrupt are : - (+) HAL_SMARTCARD_Transmit_IT() - (+) HAL_SMARTCARD_Receive_IT() - (+) HAL_SMARTCARD_IRQHandler() - (+) SMARTCARD_Transmit_IT() - (+) SMARTCARD_Receive_IT() - - (#) No-Blocking mode functions with DMA are : - (+) HAL_SMARTCARD_Transmit_DMA() - (+) HAL_SMARTCARD_Receive_DMA() - - (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: - (+) HAL_SMARTCARD_TxCpltCallback() - (+) HAL_SMARTCARD_RxCpltCallback() - (+) HAL_SMARTCARD_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Send an amount of data in blocking mode - * @param hsc: SMARTCARD handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - if(hsc->gState == HAL_SMARTCARD_STATE_READY) - { - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsc); - hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX; - - /* Init tickstart for timeout managment*/ - tickstart = HAL_GetTick(); - - hsc->TxXferSize = Size; - hsc->TxXferCount = Size; - while(hsc->TxXferCount > 0U) - { - hsc->TxXferCount--; - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - hsc->Instance->TDR = (*pData++ & (uint8_t)0xFFU); - } - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* At end of Tx process, restore hsc->gState to Ready */ - hsc->gState = HAL_SMARTCARD_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in blocking mode - * @param hsc: SMARTCARD handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - if(hsc->RxState == HAL_SMARTCARD_STATE_READY) - { - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsc); - - hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX; - - /* Init tickstart for timeout managment*/ - tickstart = HAL_GetTick(); - - hsc->RxXferSize = Size; - hsc->RxXferCount = Size; - /* Check the remain data to be received */ - while(hsc->RxXferCount > 0U) - { - hsc->RxXferCount--; - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - *pData++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0x00FFU); - } - - /* At end of Rx process, restore hsc->RxState to Ready */ - hsc->RxState = HAL_SMARTCARD_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in interrupt mode - * @param hsc: SMARTCARD handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) -{ - /* Check that a Tx process is not already ongoing */ - if(hsc->gState == HAL_SMARTCARD_STATE_READY) - { - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsc); - - hsc->pTxBuffPtr = pData; - hsc->TxXferSize = Size; - hsc->TxXferCount = Size; - - hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX; - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - - /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); - - /* Enable the SMARTCARD Transmit Complete Interrupt */ - CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TCIE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in interrupt mode - * @param hsc: SMARTCARD handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) -{ - /* Check that a Rx process is not already ongoing */ - if(hsc->RxState == HAL_SMARTCARD_STATE_READY) - { - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsc); - - hsc->pRxBuffPtr = pData; - hsc->RxXferSize = Size; - hsc->RxXferCount = Size; - - hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX; - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - - /* Enable the SMARTCARD Parity Error Interrupt */ - SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE); - - /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(hsc->Instance->CR3, USART_CR3_EIE); - - /* Enable the SMARTCARD Data Register not empty Interrupt */ - SET_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in DMA mode - * @param hsc: SMARTCARD handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) -{ - uint32_t *tmp; - - /* Check that a Tx process is not already ongoing */ - if(hsc->gState == HAL_SMARTCARD_STATE_READY) - { - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsc); - - hsc->pTxBuffPtr = pData; - hsc->TxXferSize = Size; - hsc->TxXferCount = Size; - - hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX; - - /* Set the SMARTCARD DMA transfer complete callback */ - hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt; - - /* Set the SMARTCARD error callback */ - hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError; - - /* Set the DMA abort callback */ - hsc->hdmatx->XferAbortCallback = NULL; - - /* Enable the SMARTCARD transmit DMA Stream */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->TDR, Size); - - /* Clear the TC flag in the SR register by writing 0 to it */ - __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_FLAG_TC); - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the SMARTCARD associated USART CR3 register */ - SET_BIT(hsc->Instance->CR3, USART_CR3_DMAT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in DMA mode - * @param hsc: SMARTCARD handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @note The SMARTCARD-associated USART parity is enabled (PCE = 1), - * the received data contain the parity bit (MSB position) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) -{ - uint32_t *tmp; - - /* Check that a Rx process is not already ongoing */ - if(hsc->RxState == HAL_SMARTCARD_STATE_READY) - { - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsc); - - hsc->pRxBuffPtr = pData; - hsc->RxXferSize = Size; - - hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX; - - /* Set the SMARTCARD DMA transfer complete callback */ - hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt; - - /* Set the SMARTCARD DMA error callback */ - hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError; - - /* Set the DMA abort callback */ - hsc->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA Stream */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->RDR, *(uint32_t*)tmp, Size); - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - - /* Enable the SMARTCARD Parity Error Interrupt */ - SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE); - - /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(hsc->Instance->CR3, USART_CR3_EIE); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the SMARTCARD associated USART CR3 register */ - SET_BIT(hsc->Instance->CR3, USART_CR3_DMAR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief SMARTCARD interrupt requests handling. - * @param hsc: SMARTCARD handle - * @retval None - */ -void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) -{ - uint32_t isrflags = READ_REG(hsc->Instance->ISR); - uint32_t cr1its = READ_REG(hsc->Instance->CR1); - uint32_t cr3its = READ_REG(hsc->Instance->CR3); - uint32_t dmarequest = 0x00U; - uint32_t errorflags = 0x00U; - - /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); - if(errorflags == RESET) - { - /* SMARTCARD in mode Receiver -------------------------------------------------*/ - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) - { - SMARTCARD_Receive_IT(hsc); - return; - } - } - - /* If some errors occur */ - if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET)) - { - /* SMARTCARD parity error interrupt occurred ---------------------------*/ - if(((isrflags & SMARTCARD_FLAG_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) - { - hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE; - } - - /* SMARTCARD frame error interrupt occurred ----------------------------*/ - if(((isrflags & SMARTCARD_FLAG_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) - { - hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE; - } - - /* SMARTCARD noise error interrupt occurred ----------------------------*/ - if(((isrflags & SMARTCARD_FLAG_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) - { - hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE; - } - - /* SMARTCARD Over-Run interrupt occurred -------------------------------*/ - if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) - { - hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; - } - /* Call the Error call Back in case of Errors */ - if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE) - { - /* SMARTCARD in mode Receiver -----------------------------------------------*/ - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) - { - SMARTCARD_Receive_IT(hsc); - } - - /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ - dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR); - if(((hsc->ErrorCode & HAL_SMARTCARD_ERROR_ORE) != RESET) || dmarequest) - { - /* Blocking error : transfer is aborted - Set the SMARTCARD state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ - SMARTCARD_EndRxTransfer(hsc); - /* Disable the SMARTCARD DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR); - - /* Abort the SMARTCARD DMA Rx channel */ - if(hsc->hdmarx != NULL) - { - /* Set the SMARTCARD DMA Abort callback : - will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ - hsc->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError; - - if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - hsc->hdmarx->XferAbortCallback(hsc->hdmarx); - } - } - else - { - /* Call user error callback */ - HAL_SMARTCARD_ErrorCallback(hsc); - } - } - else - { - /* Call user error callback */ - HAL_SMARTCARD_ErrorCallback(hsc); - } - } - else - { - /* Call user error callback */ - HAL_SMARTCARD_ErrorCallback(hsc); - hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - } - } - return; - } /* End if some error occurs */ - - /* SMARTCARD in mode Transmitter -------------------------------------------*/ - if(((isrflags & SMARTCARD_FLAG_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) - { - SMARTCARD_Transmit_IT(hsc); - return; - } - - /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ - if(((isrflags & SMARTCARD_FLAG_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) - { - /* Disable the SMARTCARD Transmit Complete Interrupt */ - CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TCIE); - - /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); - - /* Tx process is ended, restore hsmartcard->gState to Ready */ - hsc->gState = HAL_SMARTCARD_STATE_READY; - - HAL_SMARTCARD_TxCpltCallback(hsc); - - return; - } -} - -/** - * @brief Tx Transfer completed callbacks - * @param hsc: SMARTCARD handle - * @retval None - */ - __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callbacks - * @param hsc: SMARTCARD handle - * @retval None - */ -__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief SMARTCARD error callbacks - * @param hsc: SMARTCARD handle - * @retval None - */ - __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SMARTCARD_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State functions - * @brief SMARTCARD State functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the SMARTCARD. - (+) HAL_SMARTCARD_GetState() API is helpful to check in run-time the state of the SMARTCARD peripheral - (+) SMARTCARD_SetConfig() API configures the SMARTCARD peripheral - (+) SMARTCARD_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization - -@endverbatim - * @{ - */ - - -/** - * @brief return the SMARTCARD state - * @param hsc: SMARTCARD handle - * @retval HAL state - */ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc) -{ - uint32_t temp1= 0x00U, temp2 = 0x00U; - temp1 = hsc->gState; - temp2 = hsc->RxState; - - return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2); -} - -/** - * @brief Return the SMARTCARD error code - * @param hsc : pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD. - * @retval SMARTCARD Error Code - */ -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc) -{ - return hsc->ErrorCode; -} - -/** - * @} - */ - -/** - * @brief Send an amount of data in non blocking mode - * @param hsc: SMARTCARD handle. - * Function called under interruption only, once - * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() - * @retval HAL status - */ -static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc) -{ - if(hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX) - { - if(hsc->TxXferCount == 0) - { - /* Disable the SMARTCARD Transmit Complete Interrupt */ - CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE); - - /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); - - /* Tx process is ended, restore hsmartcard->gState to Ready */ - hsc->gState = HAL_SMARTCARD_STATE_READY; - } - - HAL_SMARTCARD_TxCpltCallback(hsc); - - return HAL_OK; - } - else - { - hsc->Instance->TDR = (*hsc->pTxBuffPtr++ & (uint8_t)0xFFU); - hsc->TxXferCount--; - - return HAL_OK; - } -} - -/** - * @brief Receive an amount of data in non blocking mode - * @param hsc: SMARTCARD handle. - * Function called under interruption only, once - * interruptions have been enabled by HAL_SMARTCARD_Receive_IT() - * @retval HAL status - */ -static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc) -{ - /* Check that a Rx process is ongoing */ - if(hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX) - { - *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0xFFU); - - if(--hsc->RxXferCount == 0) - { - CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE); - - /* Disable the SMARTCARD Parity Error Interrupt */ - CLEAR_BIT(hsc->Instance->CR1, USART_CR1_PEIE); - - /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); - - hsc->RxState = HAL_SMARTCARD_STATE_READY; - - HAL_SMARTCARD_RxCpltCallback(hsc); - - return HAL_OK; - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Configure the SMARTCARD associated USART peripheral - * @param hsc: SMARTCARD handle - * @retval None - */ -static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc) -{ - uint32_t tmpreg = 0x00000000U; - uint32_t clocksource = 0x00000000U; - - /* Check the parameters */ - assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance)); - assert_param(IS_SMARTCARD_BAUDRATE(hsc->Init.BaudRate)); - assert_param(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength)); - assert_param(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits)); - assert_param(IS_SMARTCARD_PARITY(hsc->Init.Parity)); - assert_param(IS_SMARTCARD_MODE(hsc->Init.Mode)); - assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity)); - assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase)); - assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit)); - assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsc->Init.OneBitSampling)); - assert_param(IS_SMARTCARD_NACK(hsc->Init.NACKState)); - assert_param(IS_SMARTCARD_TIMEOUT(hsc->Init.TimeOutEnable)); - assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsc->Init.AutoRetryCount)); - - /*-------------------------- USART CR1 Configuration -----------------------*/ - /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity). - * Oversampling is forced to 16 (OVER8 = 0). - * Configure the Parity and Mode: - * set PS bit according to hsc->Init.Parity value - * set TE and RE bits according to hsc->Init.Mode value */ - tmpreg = (uint32_t) hsc->Init.Parity | hsc->Init.Mode; - /* in case of TX-only mode, if NACK is enabled, the USART must be able to monitor - the bidirectional line to detect a NACK signal in case of parity error. - Therefore, the receiver block must be enabled as well (RE bit must be set). */ - if((hsc->Init.Mode == SMARTCARD_MODE_TX) && (hsc->Init.NACKState == SMARTCARD_NACK_ENABLE)) - { - tmpreg |= USART_CR1_RE; - } - tmpreg |= (uint32_t) hsc->Init.WordLength; - MODIFY_REG(hsc->Instance->CR1, USART_CR1_FIELDS, tmpreg); - - /*-------------------------- USART CR2 Configuration -----------------------*/ - /* Stop bits are forced to 1.5 (STOP = 11) */ - tmpreg = hsc->Init.StopBits; - /* Synchronous mode is activated by default */ - tmpreg |= (uint32_t) USART_CR2_CLKEN | hsc->Init.CLKPolarity; - tmpreg |= (uint32_t) hsc->Init.CLKPhase | hsc->Init.CLKLastBit; - tmpreg |= (uint32_t) hsc->Init.TimeOutEnable; - MODIFY_REG(hsc->Instance->CR2, USART_CR2_FIELDS, tmpreg); - - /*-------------------------- USART CR3 Configuration -----------------------*/ - /* Configure - * - one-bit sampling method versus three samples' majority rule - * according to hsc->Init.OneBitSampling - * - NACK transmission in case of parity error according - * to hsc->Init.NACKEnable - * - autoretry counter according to hsc->Init.AutoRetryCount */ - tmpreg = (uint32_t) hsc->Init.OneBitSampling | hsc->Init.NACKState; - tmpreg |= (uint32_t) (hsc->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS); - MODIFY_REG(hsc->Instance-> CR3,USART_CR3_FIELDS, tmpreg); - - /*-------------------------- USART GTPR Configuration ----------------------*/ - tmpreg = (uint32_t) (hsc->Init.Prescaler | (hsc->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS)); - MODIFY_REG(hsc->Instance->GTPR, (uint32_t)(USART_GTPR_GT|USART_GTPR_PSC), tmpreg); - - /*-------------------------- USART RTOR Configuration ----------------------*/ - tmpreg = (uint32_t) (hsc->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS); - if(hsc->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE) - { - assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsc->Init.TimeOutValue)); - tmpreg |= (uint32_t) hsc->Init.TimeOutValue; - } - MODIFY_REG(hsc->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg); - - /*-------------------------- USART BRR Configuration -----------------------*/ - SMARTCARD_GETCLOCKSOURCE(hsc, clocksource); - switch (clocksource) - { - case SMARTCARD_CLOCKSOURCE_PCLK1: - hsc->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate); - break; - case SMARTCARD_CLOCKSOURCE_PCLK2: - hsc->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate); - break; - case SMARTCARD_CLOCKSOURCE_HSI: - hsc->Instance->BRR = (uint16_t)((HSI_VALUE + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate); - break; - case SMARTCARD_CLOCKSOURCE_SYSCLK: - hsc->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate); - break; - case SMARTCARD_CLOCKSOURCE_LSE: - hsc->Instance->BRR = (uint16_t)((LSE_VALUE + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate); - break; - default: - break; - } -} - -/** - * @brief Check the SMARTCARD Idle State - * @param hsc: SMARTCARD handle - * @retval HAL status - */ -static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsc) -{ - uint32_t tickstart = 0U; - - /* Initialize the SMARTCARD ErrorCode */ - hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - - /* Init tickstart for timeout managment*/ - tickstart = HAL_GetTick(); - - /* Check if the Transmitter is enabled */ - if((hsc->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - { - /* Wait until TEACK flag is set */ - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, USART_ISR_TEACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK) - { - return HAL_TIMEOUT; - } - } - /* Check if the Receiver is enabled */ - if((hsc->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - /* Wait until REACK flag is set */ - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, USART_ISR_REACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK) - { - return HAL_TIMEOUT; - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - - /* Initialize the SMARTCARD state*/ - hsc->gState= HAL_SMARTCARD_STATE_READY; - hsc->RxState= HAL_SMARTCARD_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Configure the SMARTCARD associated USART peripheral advanced features - * @param hsc: SMARTCARD handle - * @retval None - */ -static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc) -{ - /* Check whether the set of advanced features to configure is properly set */ - assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsc->AdvancedInit.AdvFeatureInit)); - - /* if required, configure TX pin active level inversion */ - if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT)) - { - assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsc->AdvancedInit.TxPinLevelInvert)); - MODIFY_REG(hsc->Instance->CR2, USART_CR2_TXINV, hsc->AdvancedInit.TxPinLevelInvert); - } - - /* if required, configure RX pin active level inversion */ - if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT)) - { - assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsc->AdvancedInit.RxPinLevelInvert)); - MODIFY_REG(hsc->Instance->CR2, USART_CR2_RXINV, hsc->AdvancedInit.RxPinLevelInvert); - } - - /* if required, configure data inversion */ - if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT)) - { - assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsc->AdvancedInit.DataInvert)); - MODIFY_REG(hsc->Instance->CR2, USART_CR2_DATAINV, hsc->AdvancedInit.DataInvert); - } - - /* if required, configure RX/TX pins swap */ - if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT)) - { - assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsc->AdvancedInit.Swap)); - MODIFY_REG(hsc->Instance->CR2, USART_CR2_SWAP, hsc->AdvancedInit.Swap); - } - - /* if required, configure RX overrun detection disabling */ - if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT)) - { - assert_param(IS_SMARTCARD_OVERRUN(hsc->AdvancedInit.OverrunDisable)); - MODIFY_REG(hsc->Instance->CR3, USART_CR3_OVRDIS, hsc->AdvancedInit.OverrunDisable); - } - - /* if required, configure DMA disabling on reception error */ - if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT)) - { - assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsc->AdvancedInit.DMADisableonRxError)); - MODIFY_REG(hsc->Instance->CR3, USART_CR3_DDRE, hsc->AdvancedInit.DMADisableonRxError); - } - - /* if required, configure MSB first on communication line */ - if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT)) - { - assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsc->AdvancedInit.MSBFirst)); - MODIFY_REG(hsc->Instance->CR2, USART_CR2_MSBFIRST, hsc->AdvancedInit.MSBFirst); - } -} - -/** - * @brief This function handles SMARTCARD Communication Timeout. - * @param hsc SMARTCARD handle - * @param Flag specifies the SMARTCARD flag to check. - * @param Status The new Flag status (SET or RESET). - * @param Tickstart Tick start value - * @param Timeout Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) -{ - /* Wait until flag is set */ - while((__HAL_SMARTCARD_GET_FLAG(hsc, Flag) ? SET : RESET) == Status) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE); - CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE); - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE); - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR); - CLEAR_BIT(hsc->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); - - hsc->gState= HAL_SMARTCARD_STATE_READY; - hsc->RxState= HAL_SMARTCARD_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/* - * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion). - * @param hsc: SMARTCARD handle. - * @retval None - */ -static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc) -{ - /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - - /* At end of Tx process, restore hsc->gState to Ready */ - hsc->gState = HAL_SMARTCARD_STATE_READY; -} - - -/** - * @brief End ongoing Rx transfer on SMARTCARD peripheral (following error detection or Reception completion). - * @param hsc: SMARTCARD handle. - * @retval None - */ -static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); - - /* At end of Rx process, restore hsc->RxState to Ready */ - hsc->RxState = HAL_SMARTCARD_STATE_READY; -} - -/** - * @brief DMA SMARTCARD transmit process complete callback - * @param hdma: DMA handle - * @retval None - */ -static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hsc->TxXferCount = 0; - - /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT); - - /* Enable the SMARTCARD Transmit Complete Interrupt */ - SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE); -} - -/** - * @brief DMA SMARTCARD receive process complete callback - * @param hdma: DMA handle - * @retval None - */ -static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hsc->RxXferCount = 0; - - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); - - /* Disable the DMA transfer for the receiver request by setting the DMAR bit - in the SMARTCARD associated USART CR3 register */ - CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR); - - /* At end of Rx process, restore hsc->RxState to Ready */ - hsc->RxState = HAL_SMARTCARD_STATE_READY; - - HAL_SMARTCARD_RxCpltCallback(hsc); -} - -/** - * @brief DMA SMARTCARD communication error callback - * @param hdma: DMA handle - * @retval None - */ -static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) -{ - SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hsc->RxXferCount = 0U; - hsc->TxXferCount = 0U; - hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA; - - /* Stop SMARTCARD DMA Tx request if ongoing */ - if ( (hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX) - &&(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT)) ) - { - SMARTCARD_EndTxTransfer(hsc); - } - - /* Stop SMARTCARD DMA Rx request if ongoing */ - if ( (hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX) - &&(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR)) ) - { - SMARTCARD_EndRxTransfer(hsc); - } - - HAL_SMARTCARD_ErrorCallback(hsc); -} - -/** - * @brief DMA SMARTCARD communication abort callback, when call by HAL services on Error - * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma: DMA handle. - * @retval None - */ -static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma) -{ - SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hsc->RxXferCount = 0U; - hsc->TxXferCount = 0U; - - HAL_SMARTCARD_ErrorCallback(hsc); -} - -/** - * @} - */ - -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard_ex.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard_ex.c deleted file mode 100644 index a6541bf..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard_ex.c +++ /dev/null @@ -1,184 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_smartcard_ex.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief SMARTCARD HAL module driver. - * - * This file provides extended firmware functions to manage the following - * functionalities of the SmartCard. - * + Initialization and de-initialization functions - * + Peripheral Control functions - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The Extended SMARTCARD HAL driver can be used as follow: - - (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(), - then if required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, - auto-retry counter,...) in the hsc AdvancedInit structure. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup SMARTCARDEx SMARTCARDEx - * @brief SMARTCARD Extended HAL module driver - * @{ - */ -#ifdef HAL_SMARTCARD_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARDEx Exported Functions - * @{ - */ - -/** @defgroup SMARTCARDEx_Group1 Extended Peripheral Control functions - * @brief Extended control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the SMARTCARD. - (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly - (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly - (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature - (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature - -@endverbatim - * @{ - */ - -/** - * @brief Update on the fly the SMARTCARD block length in RTOR register - * @param hsc: SMARTCARD handle - * @param BlockLength: SMARTCARD block length (8-bit long at most) - * @retval None - */ -void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsc, uint8_t BlockLength) -{ - MODIFY_REG(hsc->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS)); -} - -/** - * @brief Update on the fly the receiver timeout value in RTOR register - * @param hsc: SMARTCARD handle - * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout - * value must be less or equal to 0x0FFFFFFFF. - * @retval None - */ -void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsc, uint32_t TimeOutValue) -{ - assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsc->Init.TimeOutValue)); - MODIFY_REG(hsc->Instance->RTOR, USART_RTOR_RTO, TimeOutValue); -} - -/** - * @brief Enable the SMARTCARD receiver timeout feature - * @param hsc: SMARTCARD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc) -{ - /* Process Locked */ - __HAL_LOCK(hsc); - - hsc->gState = HAL_SMARTCARD_STATE_BUSY; - - /* Set the USART RTOEN bit */ - hsc->Instance->CR2 |= USART_CR2_RTOEN; - - hsc->gState = HAL_SMARTCARD_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - - return HAL_OK; -} - -/** - * @brief Disable the SMARTCARD receiver timeout feature - * @param hsc: SMARTCARD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc) -{ - /* Process Locked */ - __HAL_LOCK(hsc); - - hsc->gState = HAL_SMARTCARD_STATE_BUSY; - - /* Clear the USART RTOEN bit */ - hsc->Instance->CR2 &= ~(USART_CR2_RTOEN); - - hsc->gState = HAL_SMARTCARD_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spdifrx.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spdifrx.c deleted file mode 100644 index a0df564..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spdifrx.c +++ /dev/null @@ -1,1257 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_spdifrx.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the SPDIFRX audio interface: - * + Initialization and Configuration - * + Data transfers functions - * + DMA transfers management - * + Interrupts and flags management - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The SPDIFRX HAL driver can be used as follow: - - (#) Declare SPDIFRX_HandleTypeDef handle structure. - (#) Initialize the SPDIFRX low level resources by implement the HAL_SPDIFRX_MspInit() API: - (##) Enable the SPDIFRX interface clock. - (##) SPDIFRX pins configuration: - (+++) Enable the clock for the SPDIFRX GPIOs. - (+++) Configure these SPDIFRX pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveControlFlow_IT() and HAL_SPDIFRX_ReceiveDataFlow_IT() API's). - (+++) Configure the SPDIFRX interrupt priority. - (+++) Enable the NVIC SPDIFRX IRQ handle. - (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveControlFlow_DMA() API's). - (+++) Declare a DMA handle structure for the reception of the Data Flow channel. - (+++) Declare a DMA handle structure for the reception of the Control Flow channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters. - (+++) Configure the DMA Channel. - (+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the - DMA CtrlRx/DataRx channel. - - (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits - using HAL_SPDIFRX_Init() function. - - -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros - __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process. - -@- Make sure that ck_spdif clock is configured. - - (#) Three operation modes are available within this driver : - - *** Polling mode for reception operation (for debug purpose) *** - ================================================================ - [..] - (+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow() - (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveControlFlow() - - *** Interrupt mode for reception operation *** - ========================================= - [..] - (+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT() - (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveControlFlow_IT() - (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback - (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback - (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback - - *** DMA mode for reception operation *** - ======================================== - [..] - (+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA() - (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveControlFlow_DMA() - (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback - (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback - (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback - (+) Stop the DMA Transfer using HAL_SPDIFRX_DMAStop() - - *** SPDIFRX HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in USART HAL driver. - (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State) - (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State) - (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State) - (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts - (+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts - (+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not. - - [..] - (@) You can refer to the SPDIFRX HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -/** @defgroup SPDIFRX SPDIFRX -* @brief SPDIFRX HAL module driver -* @{ -*/ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define SPDIFRX_TIMEOUT_VALUE 0xFFFF - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup SPDIFRX_Private_Functions - * @{ - */ -static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma); -static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma); -static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma); -static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma); -static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif); -static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif); -static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart); -/** - * @} - */ -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup SPDIFRX_Exported_Functions SPDIFRX Exported Functions - * @{ - */ - -/** @defgroup SPDIFRX_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - de-initialize the SPDIFRX peripheral: - - (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - - (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with - the selected configuration: - (++) Input Selection (IN0, IN1,...) - (++) Maximum allowed re-tries during synchronization phase - (++) Wait for activity on SPDIF selected input - (++) Channel status selection (from channel A or B) - (++) Data format (LSB, MSB, ...) - (++) Stereo mode - (++) User bits masking (PT,C,U,V,...) - - (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration - of the selected SPDIFRXx peripheral. - @endverbatim - * @{ - */ - -/** - * @brief Initializes the SPDIFRX according to the specified parameters - * in the SPDIFRX_InitTypeDef and create the associated handle. - * @param hspdif: SPDIFRX handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) -{ - uint32_t tmpreg = 0; - - /* Check the SPDIFRX handle allocation */ - if(hspdif == NULL) - { - return HAL_ERROR; - } - - /* Check the SPDIFRX parameters */ - assert_param(IS_STEREO_MODE(hspdif->Init.StereoMode)); - assert_param(IS_SPDIFRX_INPUT_SELECT(hspdif->Init.InputSelection)); - assert_param(IS_SPDIFRX_MAX_RETRIES(hspdif->Init.Retries)); - assert_param(IS_SPDIFRX_WAIT_FOR_ACTIVITY(hspdif->Init.WaitForActivity)); - assert_param(IS_SPDIFRX_CHANNEL(hspdif->Init.ChannelSelection)); - assert_param(IS_SPDIFRX_DATA_FORMAT(hspdif->Init.DataFormat)); - assert_param(IS_PREAMBLE_TYPE_MASK(hspdif->Init.PreambleTypeMask)); - assert_param(IS_CHANNEL_STATUS_MASK(hspdif->Init.ChannelStatusMask)); - assert_param(IS_VALIDITY_MASK(hspdif->Init.ValidityBitMask)); - assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask)); - - if(hspdif->State == HAL_SPDIFRX_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hspdif->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ - HAL_SPDIFRX_MspInit(hspdif); - } - - /* SPDIFRX peripheral state is BUSY*/ - hspdif->State = HAL_SPDIFRX_STATE_BUSY; - - /* Disable SPDIFRX interface (IDLE State) */ - __HAL_SPDIFRX_IDLE(hspdif); - - /* Reset the old SPDIFRX CR configuration */ - tmpreg = hspdif->Instance->CR; - - tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK | - SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | - SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA | SPDIFRX_CR_INSEL); - - /* Sets the new configuration of the SPDIFRX peripheral */ - tmpreg |= ((uint16_t) hspdif->Init.StereoMode | - hspdif->Init.InputSelection | - hspdif->Init.Retries | - hspdif->Init.WaitForActivity | - hspdif->Init.ChannelSelection | - hspdif->Init.DataFormat | - hspdif->Init.PreambleTypeMask | - hspdif->Init.ChannelStatusMask | - hspdif->Init.ValidityBitMask | - hspdif->Init.ParityErrorMask); - - hspdif->Instance->CR = tmpreg; - - hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; - - /* SPDIFRX peripheral state is READY*/ - hspdif->State = HAL_SPDIFRX_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the SPDIFRX peripheral - * @param hspdif: SPDIFRX handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Check the SPDIFRX handle allocation */ - if(hspdif == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SPDIFRX_ALL_INSTANCE(hspdif->Instance)); - - hspdif->State = HAL_SPDIFRX_STATE_BUSY; - - /* Disable SPDIFRX interface (IDLE state) */ - __HAL_SPDIFRX_IDLE(hspdif); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ - HAL_SPDIFRX_MspDeInit(hspdif); - - hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; - - /* SPDIFRX peripheral state is RESET*/ - hspdif->State = HAL_SPDIFRX_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hspdif); - - return HAL_OK; -} - -/** - * @brief SPDIFRX MSP Init - * @param hspdif: SPDIFRX handle - * @retval None - */ -__weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspdif); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPDIFRX_MspInit could be implemented in the user file - */ -} - -/** - * @brief SPDIFRX MSP DeInit - * @param hspdif: SPDIFRX handle - * @retval None - */ -__weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspdif); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPDIFRX_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Sets the SPDIFRX dtat format according to the specified parameters - * in the SPDIFRX_InitTypeDef. - * @param hspdif: SPDIFRX handle - * @param sDataFormat: SPDIFRX data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat) -{ - uint32_t tmpreg = 0; - - /* Check the SPDIFRX handle allocation */ - if(hspdif == NULL) - { - return HAL_ERROR; - } - - /* Check the SPDIFRX parameters */ - assert_param(IS_STEREO_MODE(sDataFormat.StereoMode)); - assert_param(IS_SPDIFRX_DATA_FORMAT(sDataFormat.DataFormat)); - assert_param(IS_PREAMBLE_TYPE_MASK(sDataFormat.PreambleTypeMask)); - assert_param(IS_CHANNEL_STATUS_MASK(sDataFormat.ChannelStatusMask)); - assert_param(IS_VALIDITY_MASK(sDataFormat.ValidityBitMask)); - assert_param(IS_PARITY_ERROR_MASK(sDataFormat.ParityErrorMask)); - - /* Reset the old SPDIFRX CR configuration */ - tmpreg = hspdif->Instance->CR; - - if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) && - (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) || - ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode))) - { - return HAL_ERROR; - } - - tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK | - SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK); - - /* Sets the new configuration of the SPDIFRX peripheral */ - tmpreg |= ((uint16_t) sDataFormat.StereoMode | - sDataFormat.DataFormat | - sDataFormat.PreambleTypeMask | - sDataFormat.ChannelStatusMask | - sDataFormat.ValidityBitMask | - sDataFormat.ParityErrorMask); - - hspdif->Instance->CR = tmpreg; - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup SPDIFRX_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * -@verbatim -=============================================================================== - ##### IO operation functions ##### -=============================================================================== - [..] - This subsection provides a set of functions allowing to manage the SPDIFRX data - transfers. - - (#) There is two mode of transfer: - (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts - or DMA. These functions return the status of the transfer start-up. - The end of the data processing will be indicated through the - dedicated SPDIFRX IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - - (#) Blocking mode functions are : - (++) HAL_SPDIFRX_ReceiveDataFlow() - (++) HAL_SPDIFRX_ReceiveControlFlow() - (+@) Do not use blocking mode to receive both control and data flow at the same time. - - (#) No-Blocking mode functions with Interrupt are : - (++) HAL_SPDIFRX_ReceiveControlFlow_IT() - (++) HAL_SPDIFRX_ReceiveDataFlow_IT() - - (#) No-Blocking mode functions with DMA are : - (++) HAL_SPDIFRX_ReceiveControlFlow_DMA() - (++) HAL_SPDIFRX_ReceiveDataFlow_DMA() - - (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: - (++) HAL_SPDIFRX_RxCpltCallback() - (++) HAL_SPDIFRX_ErrorCallback() - -@endverbatim -* @{ -*/ - - -/** - * @brief Receives an amount of data (Data Flow) in blocking mode. - * @param hspdif: pointer to SPDIFRX_HandleTypeDef structure that contains - * the configuration information for SPDIFRX module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - if((pData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - if(hspdif->State == HAL_SPDIFRX_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hspdif); - - hspdif->State = HAL_SPDIFRX_STATE_BUSY; - - /* Start synchronisation */ - __HAL_SPDIFRX_SYNC(hspdif); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until SYNCD flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Start reception */ - __HAL_SPDIFRX_RCV(hspdif); - - /* Receive data flow */ - while(Size > 0U) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until RXNE flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - (*pData++) = hspdif->Instance->DR; - Size--; - } - - /* SPDIFRX ready */ - hspdif->State = HAL_SPDIFRX_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives an amount of data (Control Flow) in blocking mode. - * @param hspdif: pointer to a SPDIFRX_HandleTypeDef structure that contains - * the configuration information for SPDIFRX module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - if((pData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - if(hspdif->State == HAL_SPDIFRX_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hspdif); - - hspdif->State = HAL_SPDIFRX_STATE_BUSY; - - /* Start synchronization */ - __HAL_SPDIFRX_SYNC(hspdif); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until SYNCD flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Start reception */ - __HAL_SPDIFRX_RCV(hspdif); - - /* Receive control flow */ - while(Size > 0U) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until CSRNE flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - (*pData++) = hspdif->Instance->CSR; - Size--; - } - - /* SPDIFRX ready */ - hspdif->State = HAL_SPDIFRX_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt - * @param hspdif: SPDIFRX handle - * @param pData: a 32-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be received . - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0U; - - if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX)) - { - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hspdif); - - hspdif->pRxBuffPtr = pData; - hspdif->RxXferSize = Size; - hspdif->RxXferCount = Size; - - hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; - - /* Check if a receive process is ongoing or not */ - hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX; - - - /* Enable the SPDIFRX PE Error Interrupt */ - __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE); - - /* Enable the SPDIFRX OVR Error Interrupt */ - __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE); - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - /* Enable the SPDIFRX RXNE interrupt */ - __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE); - - if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) - { - /* Start synchronization */ - __HAL_SPDIFRX_SYNC(hspdif); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until SYNCD flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Start reception */ - __HAL_SPDIFRX_RCV(hspdif); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data (Control Flow) with Interrupt - * @param hspdif: SPDIFRX handle - * @param pData: a 32-bit pointer to the Receive data buffer. - * @param Size: number of data sample (Control Flow) to be received : - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0U; - - if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX)) - { - if((pData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hspdif); - - hspdif->pCsBuffPtr = pData; - hspdif->CsXferSize = Size; - hspdif->CsXferCount = Size; - - hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; - - /* Check if a receive process is ongoing or not */ - hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX; - - - /* Enable the SPDIFRX PE Error Interrupt */ - __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE); - - /* Enable the SPDIFRX OVR Error Interrupt */ - __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE); - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - /* Enable the SPDIFRX CSRNE interrupt */ - __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE); - - if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) - { - /* Start synchronization */ - __HAL_SPDIFRX_SYNC(hspdif); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until SYNCD flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Start reception */ - __HAL_SPDIFRX_RCV(hspdif); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data (Data Flow) mode with DMA - * @param hspdif: SPDIFRX handle - * @param pData: a 32-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be received : - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0U; - - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX)) - { - hspdif->pRxBuffPtr = pData; - hspdif->RxXferSize = Size; - hspdif->RxXferCount = Size; - - /* Process Locked */ - __HAL_LOCK(hspdif); - - hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; - hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX; - - /* Set the SPDIFRX Rx DMA Half transfer complete callback */ - hspdif->hdmaDrRx->XferHalfCpltCallback = SPDIFRX_DMARxHalfCplt; - - /* Set the SPDIFRX Rx DMA transfer complete callback */ - hspdif->hdmaDrRx->XferCpltCallback = SPDIFRX_DMARxCplt; - - /* Set the DMA error callback */ - hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError; - - /* Enable the DMA request */ - HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size); - - /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/ - hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN; - - if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) - { - /* Start synchronization */ - __HAL_SPDIFRX_SYNC(hspdif); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until SYNCD flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Start reception */ - __HAL_SPDIFRX_RCV(hspdif); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data (Control Flow) with DMA - * @param hspdif: SPDIFRX handle - * @param pData: a 32-bit pointer to the Receive data buffer. - * @param Size: number of data (Control Flow) sample to be received : - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0U; - - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX)) - { - hspdif->pCsBuffPtr = pData; - hspdif->CsXferSize = Size; - hspdif->CsXferCount = Size; - - /* Process Locked */ - __HAL_LOCK(hspdif); - - hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; - hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX; - - /* Set the SPDIFRX Rx DMA Half transfer complete callback */ - hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt; - - /* Set the SPDIFRX Rx DMA transfer complete callback */ - hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt; - - /* Set the DMA error callback */ - hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError; - - /* Enable the DMA request */ - HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size); - - /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/ - hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN; - - if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) - { - /* Start synchronization */ - __HAL_SPDIFRX_SYNC(hspdif); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until SYNCD flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Start reception */ - __HAL_SPDIFRX_RCV(hspdif); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief stop the audio stream receive from the Media. - * @param hspdif: SPDIFRX handle - * @retval None - */ -HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Process Locked */ - __HAL_LOCK(hspdif); - - /* Disable the SPDIFRX DMA requests */ - hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN); - hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN); - - /* Disable the SPDIFRX DMA channel */ - __HAL_DMA_DISABLE(hspdif->hdmaDrRx); - __HAL_DMA_DISABLE(hspdif->hdmaCsRx); - - /* Disable SPDIFRX peripheral */ - __HAL_SPDIFRX_IDLE(hspdif); - - hspdif->State = HAL_SPDIFRX_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - return HAL_OK; -} - -/** - * @brief This function handles SPDIFRX interrupt request. - * @param hspdif: SPDIFRX handle - * @retval HAL status - */ -void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif) -{ - /* SPDIFRX in mode Data Flow Reception ------------------------------------------------*/ - if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_RXNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_RXNE) != RESET)) - { - __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE); - SPDIFRX_ReceiveDataFlow_IT(hspdif); - } - - /* SPDIFRX in mode Control Flow Reception ------------------------------------------------*/ - if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_CSRNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_CSRNE) != RESET)) - { - __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE); - SPDIFRX_ReceiveControlFlow_IT(hspdif); - } - - /* SPDIFRX Overrun error interrupt occurred ---------------------------------*/ - if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_OVR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_OVRIE) != RESET)) - { - __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_OVR); - - /* Change the SPDIFRX error code */ - hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_OVR; - - /* the transfer is not stopped */ - HAL_SPDIFRX_ErrorCallback(hspdif); - } - - /* SPDIFRX Parity error interrupt occurred ---------------------------------*/ - if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_PERR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_PERRIE) != RESET)) - { - __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_PERR); - - /* Change the SPDIFRX error code */ - hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_PE; - - /* the transfer is not stopped */ - HAL_SPDIFRX_ErrorCallback(hspdif); - } -} - -/** - * @brief Rx Transfer (Data flow) half completed callbacks - * @param hspdif: SPDIFRX handle - * @retval None - */ -__weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspdif); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer (Data flow) completed callbacks - * @param hspdif: SPDIFRX handle - * @retval None - */ -__weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspdif); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx (Control flow) Transfer half completed callbacks - * @param hspdif: SPDIFRX handle - * @retval None - */ -__weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspdif); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer (Control flow) completed callbacks - * @param hspdif: SPDIFRX handle - * @retval None - */ -__weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspdif); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief SPDIFRX error callbacks - * @param hspdif: SPDIFRX handle - * @retval None - */ -__weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspdif); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPDIFRX_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup SPDIFRX_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State functions - * -@verbatim -=============================================================================== -##### Peripheral State and Errors functions ##### -=============================================================================== -[..] -This subsection permit to get in run-time the status of the peripheral -and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the SPDIFRX state - * @param hspdif : SPDIFRX handle - * @retval HAL state - */ -HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif) -{ - return hspdif->State; -} - -/** - * @brief Return the SPDIFRX error code - * @param hspdif : SPDIFRX handle - * @retval SPDIFRX Error Code - */ -uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif) -{ - return hspdif->ErrorCode; -} - -/** - * @} - */ - -/** - * @brief DMA SPDIFRX receive process (Data flow) complete callback - * @param hdma : DMA handle - * @retval None - */ -static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma) -{ - SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Disable Rx DMA Request */ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) - { - hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN); - hspdif->RxXferCount = 0; - hspdif->State = HAL_SPDIFRX_STATE_READY; - } - HAL_SPDIFRX_RxCpltCallback(hspdif); -} - -/** - * @brief DMA SPDIFRX receive process (Data flow) half complete callback - * @param hdma : DMA handle - * @retval None - */ -static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - HAL_SPDIFRX_RxHalfCpltCallback(hspdif); -} - - -/** - * @brief DMA SPDIFRX receive process (Control flow) complete callback - * @param hdma : DMA handle - * @retval None - */ -static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma) -{ - SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Disable Cb DMA Request */ - hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN); - hspdif->CsXferCount = 0; - - hspdif->State = HAL_SPDIFRX_STATE_READY; - HAL_SPDIFRX_CxCpltCallback(hspdif); -} - -/** - * @brief DMA SPDIFRX receive process (Control flow) half complete callback - * @param hdma : DMA handle - * @retval None - */ -static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma) -{ - SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - HAL_SPDIFRX_CxHalfCpltCallback(hspdif); -} - -/** - * @brief DMA SPDIFRX communication error callback - * @param hdma : DMA handle - * @retval None - */ -static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma) -{ - SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Disable Rx and Cb DMA Request */ - hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN)); - hspdif->RxXferCount = 0; - - hspdif->State= HAL_SPDIFRX_STATE_READY; - - /* Set the error code and execute error callback*/ - hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA; - HAL_SPDIFRX_ErrorCallback(hspdif); -} - -/** - * @brief Receive an amount of data (Data Flow) with Interrupt - * @param hspdif: SPDIFRX handle - * @retval None - */ -static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Receive data */ - (*hspdif->pRxBuffPtr++) = hspdif->Instance->DR; - hspdif->RxXferCount--; - - if(hspdif->RxXferCount == 0) - { - /* Disable RXNE/PE and OVR interrupts */ - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE); - - hspdif->State = HAL_SPDIFRX_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - HAL_SPDIFRX_RxCpltCallback(hspdif); - } -} - -/** - * @brief Receive an amount of data (Control Flow) with Interrupt - * @param hspdif: SPDIFRX handle - * @retval None - */ -static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Receive data */ - (*hspdif->pCsBuffPtr++) = hspdif->Instance->CSR; - hspdif->CsXferCount--; - - if(hspdif->CsXferCount == 0) - { - /* Disable CSRNE interrupt */ - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); - - hspdif->State = HAL_SPDIFRX_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - HAL_SPDIFRX_CxCpltCallback(hspdif); - } -} - -/** - * @brief This function handles SPDIFRX Communication Timeout. - * @param hspdif: SPDIFRX handle - * @param Flag: Flag checked - * @param Status: Value of the flag expected - * @param Timeout: Duration of the timeout - * @param tickstart: Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart) -{ - /* Wait until flag is set */ - if(Status == RESET) - { - while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - - hspdif->State= HAL_SPDIFRX_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - return HAL_TIMEOUT; - } - } - } - } - else - { - while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) != RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - - hspdif->State= HAL_SPDIFRX_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - return HAL_TIMEOUT; - } - } - } - } - return HAL_OK; -} - -/** -* @} -*/ - -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c deleted file mode 100644 index 745b59c..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c +++ /dev/null @@ -1,2963 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_spi.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief SPI HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Serial Peripheral Interface (SPI) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The SPI HAL driver can be used as follows: - - (#) Declare a SPI_HandleTypeDef handle structure, for example: - SPI_HandleTypeDef hspi; - - (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: - (##) Enable the SPIx interface clock - (##) SPI pins configuration - (+++) Enable the clock for the SPI GPIOs - (+++) Configure these SPI pins as alternate function push-pull - (##) NVIC configuration if you need to use interrupt process - (+++) Configure the SPIx interrupt priority - (+++) Enable the NVIC SPI IRQ handle - (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel - (+++) Enable the DMAx clock - (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx channel - (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel - - (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS - management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. - - (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: - (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customized HAL_SPI_MspInit() API. - [..] - Circular mode restriction: - (#) The DMA circular mode cannot be used when the SPI is configured in these modes: - (##) Master 2Lines RxOnly - (##) Master 1Line Rx - (#) The CRC feature is not managed when the DMA circular mode is enabled - (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs - the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup SPI SPI - * @brief SPI HAL module driver - * @{ - */ -#ifdef HAL_SPI_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup SPI_Private_Constants SPI Private Constants - * @{ - */ -#define SPI_DEFAULT_TIMEOUT 50 -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup SPI_Private_Functions SPI Private Functions - * @{ - */ -static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); -static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); -static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); -static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); -static void SPI_DMAError(DMA_HandleTypeDef *hdma); -static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout); -static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout); -static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); -static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); -static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); -#if (USE_SPI_CRC != 0U) -static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); -static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); -static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); -static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); -#endif -static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); -static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); -static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi); -static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi); -static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi); -static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); -static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); -static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); -static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout); -static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup SPI_Exported_Functions SPI Exported Functions - * @{ - */ - -/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - de-initialize the SPIx peripheral: - - (+) User must implement HAL_SPI_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - - (+) Call the function HAL_SPI_Init() to configure the selected device with - the selected configuration: - (++) Mode - (++) Direction - (++) Data Size - (++) Clock Polarity and Phase - (++) NSS Management - (++) BaudRate Prescaler - (++) FirstBit - (++) TIMode - (++) CRC Calculation - (++) CRC Polynomial if CRC enabled - (++) CRC Length, used only with Data8 and Data16 - (++) FIFO reception threshold - - (+) Call the function HAL_SPI_DeInit() to restore the default configuration - of the selected SPIx peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the SPI according to the specified parameters - * in the SPI_InitTypeDef and initialize the associated handle. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) -{ - uint32_t frxth; - - /* Check the SPI handle allocation */ - if(hspi == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); - assert_param(IS_SPI_MODE(hspi->Init.Mode)); - assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); - assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); - assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); - assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); - assert_param(IS_SPI_NSS(hspi->Init.NSS)); - assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); - assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); - assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); - assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); -#if (USE_SPI_CRC != 0U) - assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); - assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); - } - /* Align the CRC Length on the data size */ - if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) - { - /* CRC Length aligned on the data size : value set by default */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; - } - else - { - hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; - } - } -#endif - - if(hspi->State == HAL_SPI_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hspi->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - HAL_SPI_MspInit(hspi); - } - - hspi->State = HAL_SPI_STATE_BUSY; - - /* Disable the selected SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - - /* Align by default the rs fifo threshold on the data size */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - frxth = SPI_RXFIFO_THRESHOLD_HF; - } - else - { - frxth = SPI_RXFIFO_THRESHOLD_QF; - } - - /* CRC calculation is valid only for 16Bit and 8 Bit */ - if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT )) - { - /* CRC must be disabled */ - hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; - } - - /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/ - /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, - Communication speed, First bit, CRC calculation state, CRC Length */ - hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction | - hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | - hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation); - - if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) - { - hspi->Instance->CR1|= SPI_CR1_CRCL; - } - - /* Configure : NSS management */ - /* Configure : Rx Fifo Threshold */ - hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode | - hspi->Init.DataSize ) | frxth; - -#if (USE_SPI_CRC != 0U) - /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ - /* Configure : CRC Polynomial */ - WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); -#endif - - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->State= HAL_SPI_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitialize the SPI peripheral. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) -{ - /* Check the SPI handle allocation */ - if(hspi == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); - - hspi->State = HAL_SPI_STATE_BUSY; - - /* Disable the SPI Peripheral Clock */ - __HAL_SPI_DISABLE(hspi); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ - HAL_SPI_MspDeInit(hspi); - - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->State = HAL_SPI_STATE_RESET; - - __HAL_UNLOCK(hspi); - - return HAL_OK; -} - -/** - * @brief SPI MSP Init - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_MspInit should be implemented in the user file - */ -} - -/** - * @brief SPI MSP DeInit - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_MspDeInit should be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup SPI_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the SPI - data transfers. - - [..] The SPI supports master and slave mode : - - (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These APIs return the HAL status. - The end of the data processing will be indicated through the - dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected - - (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) - exist for 1Line (simplex) and 2Lines (full duplex) modes. - -@endverbatim - * @{ - */ - -/** - * @brief Transmit an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - HAL_StatusTypeDef errorcode = HAL_OK; - - assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - - /* Process Locked */ - __HAL_LOCK(hspi); - - if(hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - - if((pData == NULL ) || (Size == 0)) - { - errorcode = HAL_ERROR; - goto error; - } - - /* Set the transaction information */ - hspi->State = HAL_SPI_STATE_BUSY_TX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = pData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - hspi->pRxBuffPtr = (uint8_t *)NULL; - hspi->RxXferSize = 0; - hspi->RxXferCount = 0; - - /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_TX(hspi); - } - -#if (USE_SPI_CRC != 0U) - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } -#endif - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - /* Transmit data in 16 Bit mode */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - /* Transmit data in 16 Bit mode */ - while (hspi->TxXferCount > 0) - { - /* Wait until TXE flag is set to send data */ - if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE) - { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; - } - else - { - /* Timeout management */ - if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) - { - errorcode = HAL_TIMEOUT; - goto error; - } - } - } - } - /* Transmit data in 8 Bit mode */ - else - { - while (hspi->TxXferCount > 0) - { - /* Wait until TXE flag is set to send data */ - if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE) - { - if(hspi->TxXferCount > 1) - { - /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2; - } - else - { - *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++); - hspi->TxXferCount--; - } - } - else - { - /* Timeout management */ - if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) - { - errorcode = HAL_TIMEOUT; - goto error; - } - } - } - } - -#if (USE_SPI_CRC != 0U) - /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - hspi->Instance->CR1|= SPI_CR1_CRCNEXT; - } -#endif - - /* Check the end of the transaction */ - if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_FLAG; - } - - /* Clear overrun flag in 2 Lines communication mode because received is not read */ - if(hspi->Init.Direction == SPI_DIRECTION_2LINES) - { - __HAL_SPI_CLEAR_OVRFLAG(hspi); - } - - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - errorcode = HAL_ERROR; - } - -error: - hspi->State = HAL_SPI_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; -} - -/** - * @brief Receive an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ -#if (USE_SPI_CRC != 0U) - __IO uint16_t tmpreg; -#endif - uint32_t tickstart = HAL_GetTick(); - HAL_StatusTypeDef errorcode = HAL_OK; - - if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) - { - /* the receive process is not supported in 2Lines direction master mode */ - /* in this case we call the TransmitReceive process */ - /* Process Locked */ - return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout); - } - - /* Process Locked */ - __HAL_LOCK(hspi); - - if(hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - - if((pData == NULL ) || (Size == 0)) - { - errorcode = HAL_ERROR; - goto error; - } - - hspi->State = HAL_SPI_STATE_BUSY_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = pData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - hspi->pTxBuffPtr = (uint8_t *)NULL; - hspi->TxXferSize = 0; - hspi->TxXferCount = 0; - -#if (USE_SPI_CRC != 0U) - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - /* this is done to handle the CRCNEXT before the latest data */ - hspi->RxXferCount--; - } -#endif - - /* Set the Rx Fido threshold */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - /* set fiforxthreshold according the reception data length: 16bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - else - { - /* set fiforxthreshold according the reception data length: 8bit */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - - /* Configure communication direction 1Line and enabled SPI if needed */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_RX(hspi); - } - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - /* Receive data in 8 Bit mode */ - if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT) - { - /* Transfer loop */ - while(hspi->RxXferCount > 0) - { - /* Check the RXNE flag */ - if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE) - { - /* read the received data */ - (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR; - hspi->RxXferCount--; - } - else - { - /* Timeout management */ - if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) - { - errorcode = HAL_TIMEOUT; - goto error; - } - } - } - } - else - { - /* Transfer loop */ - while(hspi->RxXferCount > 0) - { - /* Check the RXNE flag */ - if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE) - { - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - } - else - { - /* Timeout management */ - if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) - { - errorcode = HAL_TIMEOUT; - goto error; - } - } - } - } - -#if (USE_SPI_CRC != 0U) - /* Handle the CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* freeze the CRC before the latest data */ - hspi->Instance->CR1|= SPI_CR1_CRCNEXT; - - /* Read the latest data */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) - { - /* the latest data has not been received */ - errorcode = HAL_TIMEOUT; - goto error; - } - - /* Receive last data in 16 Bit mode */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - } - /* Receive last data in 8 Bit mode */ - else - { - *hspi->pRxBuffPtr = *(__IO uint8_t *)&hspi->Instance->DR; - } - - /* Wait until TXE flag */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) - { - /* Flag Error*/ - hspi->ErrorCode = HAL_SPI_ERROR_CRC; - errorcode = HAL_TIMEOUT; - goto error; - } - - if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) - { - tmpreg = hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ - } - else - { - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ - - if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) - { - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) - { - /* Error on the CRC reception */ - hspi->ErrorCode = HAL_SPI_ERROR_CRC; - errorcode = HAL_TIMEOUT; - goto error; - } - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ - } - } - } -#endif - - /* Check the end of the transaction */ - if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_FLAG; - } - -#if (USE_SPI_CRC != 0U) - /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) - { - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - } -#endif - - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - errorcode = HAL_ERROR; - } - -error : - hspi->State = HAL_SPI_STATE_READY; - __HAL_UNLOCK(hspi); - return errorcode; -} - -/** - * @brief Transmit and Receive an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @param Size: amount of data to be sent and received - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) -{ -#if (USE_SPI_CRC != 0U) - __IO uint16_t tmpreg; -#endif - uint32_t tickstart = HAL_GetTick(); - /* Variable used to alternate Rx and Tx during transfer */ - uint32_t txallowed = 1U; - - HAL_StatusTypeDef errorcode = HAL_OK; - - assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - - /* Process Locked */ - __HAL_LOCK(hspi); - - if(hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) - { - errorcode = HAL_ERROR; - goto error; - } - - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = pRxData; - hspi->RxXferCount = Size; - hspi->RxXferSize = Size; - hspi->pTxBuffPtr = pTxData; - hspi->TxXferCount = Size; - hspi->TxXferSize = Size; - -#if (USE_SPI_CRC != 0U) - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } -#endif - - /* Set the Rx Fifo threshold */ - if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1)) - { - /* set fiforxthreshold according the reception data length: 16bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - else - { - /* set fiforxthreshold according the reception data length: 8bit */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - /* Transmit and Receive data in 16 Bit mode */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0)) - { - /* Check TXE flag */ - if(txallowed && ((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))) - { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; - /* Next Data is a reception (Rx). Tx not allowed */ - txallowed = 0U; - -#if (USE_SPI_CRC != 0U) - /* Enable CRC Transmission */ - if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) - { - /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ - if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP)) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); - } - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } -#endif - } - /* Check RXNE flag */ - if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)) - { - *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - /* Next Data is a reception (Rx). Tx not allowed */ - txallowed = 1U; - } - if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)) - { - errorcode = HAL_TIMEOUT; - goto error; - } - } - } - /* Transmit and Receive data in 8 Bit mode */ - else - { - while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0)) - { - /* check TXE flag */ - if(txallowed && ((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))) - { - if(hspi->TxXferCount > 1) - { - hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2; - } - else - { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); - hspi->TxXferCount--; - /* Next Data is a reception (Rx). Tx not allowed */ - txallowed = 0U; - } - -#if (USE_SPI_CRC != 0U) - /* Enable CRC Transmission */ - if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) - { - /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ - if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP)) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); - } - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } -#endif - } - - /* Wait until RXNE flag is reset */ - if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)) - { - if(hspi->RxXferCount > 1) - { - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount -= 2; - if(hspi->RxXferCount <= 1) - { - /* set fiforxthreshold before to switch on 8 bit data size */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - } - else - { - (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR; - hspi->RxXferCount--; - /* Next Data is a Transmission (Tx). Tx is allowed */ - txallowed = 1U; - } - } - if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)) - { - errorcode = HAL_TIMEOUT; - goto error; - } - } - } - -#if (USE_SPI_CRC != 0U) - /* Read CRC from DR to close CRC calculation process */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* Wait until TXE flag */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) - { - /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; - errorcode = HAL_TIMEOUT; - goto error; - } - - if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) - { - tmpreg = hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ - } - else - { - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ - - if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) - { - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) - { - /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; - errorcode = HAL_TIMEOUT; - goto error; - } - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ - } - } - } - - /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) - { - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; - /* Clear CRC Flag */ - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - - errorcode = HAL_ERROR; - } -#endif - - /* Check the end of the transaction */ - if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_FLAG; - } - - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - errorcode = HAL_ERROR; - } - -error : - hspi->State = HAL_SPI_STATE_READY; - __HAL_UNLOCK(hspi); - return errorcode; -} - -/** - * @brief Transmit an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef errorcode = HAL_OK; - assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - - /* Process Locked */ - __HAL_LOCK(hspi); - - if((pData == NULL) || (Size == 0)) - { - errorcode = HAL_ERROR; - goto error; - } - - if(hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - - /* prepare the transfer */ - hspi->State = HAL_SPI_STATE_BUSY_TX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = pData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - hspi->pRxBuffPtr = (uint8_t *)NULL; - hspi->RxXferSize = 0; - hspi->RxXferCount = 0; - hspi->RxISR = NULL; - - /* Set the function for IT treatment */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) - { - hspi->TxISR = SPI_TxISR_16BIT; - } - else - { - hspi->TxISR = SPI_TxISR_8BIT; - } - - /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_TX(hspi); - } - -#if (USE_SPI_CRC != 0U) - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } -#endif - - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE)); - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - -error : - __HAL_UNLOCK(hspi); - return errorcode; -} - -/** - * @brief Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef errorcode = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(hspi); - - if(hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - if((pData == NULL) || (Size == 0)) - { - errorcode = HAL_ERROR; - goto error; - } - - /* Configure communication */ - hspi->State = HAL_SPI_STATE_BUSY_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = pData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - hspi->pTxBuffPtr = (uint8_t *)NULL; - hspi->TxXferSize = 0; - hspi->TxXferCount = 0; - - if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) - { - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - /* the receive process is not supported in 2Lines direction master mode */ - /* in this we call the TransmitReceive process */ - return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size); - } - - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - hspi->CRCSize = 1; - if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) - { - hspi->CRCSize = 2; - } - } - else - { - hspi->CRCSize = 0; - } - - hspi->TxISR = NULL; - /* check the data size to adapt Rx threshold and the set the function for IT treatment */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) - { - /* set fiforxthresold according the reception data length: 16 bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - hspi->RxISR = SPI_RxISR_16BIT; - } - else - { - /* set fiforxthresold according the reception data length: 8 bit */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - hspi->RxISR = SPI_RxISR_8BIT; - } - - /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_RX(hspi); - } - -#if (USE_SPI_CRC != 0U) - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } -#endif - - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; -} - -/** - * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @param Size: amount of data to be sent and received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) -{ - HAL_StatusTypeDef errorcode = HAL_OK; - assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - - /* Process locked */ - __HAL_LOCK(hspi); - - if(!((hspi->State == HAL_SPI_STATE_READY) || \ - ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))) - { - errorcode = HAL_BUSY; - goto error; - } - - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) - { - errorcode = HAL_ERROR; - goto error; - } - - hspi->CRCSize = 0; - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - hspi->CRCSize = 1; - if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) - { - hspi->CRCSize = 2; - } - } - - if(hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } - - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = pTxData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - hspi->pRxBuffPtr = pRxData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - - /* Set the function for IT treatment */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) - { - hspi->RxISR = SPI_2linesRxISR_16BIT; - hspi->TxISR = SPI_2linesTxISR_16BIT; - } - else - { - hspi->RxISR = SPI_2linesRxISR_8BIT; - hspi->TxISR = SPI_2linesTxISR_8BIT; - } - -#if (USE_SPI_CRC != 0U) - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } -#endif - - /* check if packing mode is enabled and if there is more than 2 data to receive */ - if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2)) - { - /* set fiforxthresold according the reception data length: 16 bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - else - { - /* set fiforxthresold according the reception data length: 8 bit */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - - /* Enable TXE, RXNE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; -} - -/** - * @brief Transmit an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef errorcode = HAL_OK; - assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - - /* Process Locked */ - __HAL_LOCK(hspi); - - if(hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - - if((pData == NULL) || (Size == 0)) - { - errorcode = HAL_ERROR; - goto error; - } - - hspi->State = HAL_SPI_STATE_BUSY_TX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = pData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - hspi->pRxBuffPtr = (uint8_t *)NULL; - hspi->RxXferSize = 0; - hspi->RxXferCount = 0; - - /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_TX(hspi); - } - -#if (USE_SPI_CRC != 0U) - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } -#endif - - /* Set the SPI TxDMA Half transfer complete callback */ - hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; - - /* Set the SPI TxDMA transfer complete callback */ - hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; - - /* Set the DMA error callback */ - hspi->hdmatx->XferErrorCallback = SPI_DMAError; - - /* Set the DMA abort callback */ - hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; - - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - /* packing mode is enabled only if the DMA setting is HALWORD */ - if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) - { - /* Check the even/odd of the data size + crc if enabled */ - if((hspi->TxXferCount & 0x1) == 0) - { - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - hspi->TxXferCount = (hspi->TxXferCount >> 1); - } - else - { - SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1; - } - } - - /* Enable SPI Error interrupts, EIE: MODF, OVR, FE, FRE, CEC(depends on family) */ - SET_BIT(hspi->Instance->CR2, (SPI_CR2_ERRIE)); - SET_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR)); - - /* Enable the Tx DMA channel */ - HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - /* Enable Tx DMA Request */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; -} - -/** - * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @note When the CRC feature is enabled the pData Length must be Size + 1. - * @param Size: amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef errorcode = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(hspi); - - if(hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - - if((pData == NULL) || (Size == 0)) - { - errorcode = HAL_ERROR; - goto error; - } - - hspi->State = HAL_SPI_STATE_BUSY_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = pData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - hspi->pTxBuffPtr = (uint8_t *)NULL; - hspi->TxXferSize = 0; - hspi->TxXferCount = 0; - - if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) - { - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - /* the receive process is not supported in 2Lines direction master mode */ - /* in this case we call the TransmitReceive process */ - return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size); - } - - /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_RX(hspi); - } - -#if (USE_SPI_CRC != 0U) - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } -#endif - - /* packing mode management is enabled by the DMA settings */ - if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) - { - /* Restriction the DMA data received is not allowed in this mode */ - errorcode = HAL_ERROR; - goto error; - } - - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); - if( hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - /* set fiforxthreshold according the reception data length: 16bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - else - { - /* set fiforxthreshold according the reception data length: 8bit */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - - /* Set the SPI RxDMA Half transfer complete callback */ - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; - - /* Set the SPI Rx DMA transfer complete callback */ - hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; - - /* Set the DMA error callback */ - hspi->hdmarx->XferErrorCallback = SPI_DMAError; - - /* Set the DMA abort callback */ - hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; - - /* Enable SPI Error interrupts, EIE: MODF, OVR, FE, FRE, CEC(depends on family) */ - SET_BIT(hspi->Instance->CR2, (SPI_CR2_ERRIE)); - SET_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR)); - - /* Enable Rx DMA Request */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - - /* Enable the Rx DMA channel */ - HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; -} - -/** - * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @note When the CRC feature is enabled the pRxData Length must be Size + 1 - * @param Size: amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) -{ - HAL_StatusTypeDef errorcode = HAL_OK; - assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - - /* Process locked */ - __HAL_LOCK(hspi); - - if(!((hspi->State == HAL_SPI_STATE_READY) || - ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))) - { - errorcode = HAL_BUSY; - goto error; - } - - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) - { - errorcode = HAL_ERROR; - goto error; - } - - /* check if the transmit Receive function is not called by a receive master */ - if(hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } - - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - hspi->pRxBuffPtr = (uint8_t *)pRxData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - -#if (USE_SPI_CRC != 0U) - /* Reset CRC Calculation + increase the rxsize */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } -#endif - - /* Reset the threshold bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX); - - /* the packing mode management is enabled by the DMA settings according the spi data size */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - /* set fiforxthreshold according the reception data length: 16bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - else - { - /* set fiforxthresold according the reception data length: 8bit */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - - if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) - { - if((hspi->TxXferSize & 0x1) == 0x0) - { - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - hspi->TxXferCount = hspi->TxXferCount >> 1; - } - else - { - SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1; - } - } - - if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) - { - /* set fiforxthresold according the reception data length: 16bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - - if((hspi->RxXferCount & 0x1) == 0x0 ) - { - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); - hspi->RxXferCount = hspi->RxXferCount >> 1; - } - else - { - SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); - hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1; - } - } - } - - /* Set the SPI Rx DMA transfer complete callback if the transfer request is a - reception request (RXNE) */ - if(hspi->State == HAL_SPI_STATE_BUSY_RX) - { - /* Set the SPI Rx DMA Half transfer complete callback */ - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; - hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; - } - else - { - /* Set the SPI Rx DMA Half transfer complete callback */ - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; - hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; - } - - /* Set the DMA error callback */ - hspi->hdmarx->XferErrorCallback = SPI_DMAError; - - /* Set the DMA abort callback */ - hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; - - /* Enable SPI Error interrupts, EIE: MODF, OVR, FE, FRE, CEC(depends on family) */ - SET_BIT(hspi->Instance->CR2, (SPI_CR2_ERRIE)); - SET_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR)); - - /* Enable Rx DMA Request */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - - /* Enable the Rx DMA channel */ - HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount); - - /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing - is performed in DMA reception complete callback */ - hspi->hdmatx->XferHalfCpltCallback = NULL; - hspi->hdmatx->XferCpltCallback = NULL; - - /* Set the DMA error callback */ - hspi->hdmatx->XferErrorCallback = SPI_DMAError; - - /* Set the DMA abort callback */ - hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; - - /* Enable the Tx DMA channel */ - HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - /* Enable Tx DMA Request */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; -} - -/** - * @brief Pause the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) -{ - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Disable the SPI DMA Tx & Rx requests */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_OK; -} - -/** - * @brief Resumes the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) -{ - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Enable the SPI DMA Tx & Rx requests */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_OK; -} - -/** - * @brief Stops the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) -{ - /* The Lock is not implemented on this API to allow the user application - to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): - when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() - */ - - /* Abort the SPI DMA tx Stream */ - if(hspi->hdmatx != NULL) - { - HAL_DMA_Abort(hspi->hdmatx); - } - /* Abort the SPI DMA rx Stream */ - if(hspi->hdmarx != NULL) - { - HAL_DMA_Abort(hspi->hdmarx); - } - - /* Disable the SPI DMA Tx & Rx requests */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); - hspi->State = HAL_SPI_STATE_READY; - return HAL_OK; -} - -/** - * @brief This function handles SPI interrupt request. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. - * @retval None - */ -void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) -{ - uint32_t itsource = hspi->Instance->CR2; - uint32_t itflag = hspi->Instance->SR; - - /* SPI in mode Receiver ----------------------------------------------------*/ - if(((itflag & SPI_FLAG_OVR) == RESET) && - ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET)) - { - hspi->RxISR(hspi); - return; - } - - /* SPI in mode Transmitter ---------------------------------------------------*/ - if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET)) - { - hspi->TxISR(hspi); - return; - } - - /* SPI in Error Treatment ---------------------------------------------------*/ - if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) - { - /* SPI Overrun error interrupt occurred -------------------------------------*/ - if((itflag & SPI_FLAG_OVR) != RESET) - { - if(hspi->State != HAL_SPI_STATE_BUSY_TX) - { - hspi->ErrorCode |= HAL_SPI_ERROR_OVR; - __HAL_SPI_CLEAR_OVRFLAG(hspi); - } - else - { - return; - } - } - - /* SPI Mode Fault error interrupt occurred -------------------------------------*/ - if((itflag & SPI_FLAG_MODF) != RESET) - { - hspi->ErrorCode |= HAL_SPI_ERROR_MODF; - __HAL_SPI_CLEAR_MODFFLAG(hspi); - } - - /* SPI Frame error interrupt occurred ----------------------------------------*/ - if((itflag & SPI_FLAG_FRE) != RESET) - { - hspi->ErrorCode |= HAL_SPI_ERROR_FRE; - __HAL_SPI_CLEAR_FREFLAG(hspi); - } - - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - /* All SPI errors are treated as Blocking errors : transfer is aborted. - Set the SPI state to ready so as to be able to restart the process, - Disable Rx/Tx Interrupts, and disable DMA Rx/Tx requests, if ongoing */ - - /* Disable TXE, RXNE, MODF, OVR, FRE, and CRCERR (Master mode fault, Overrun error, TI frame format error, CRC protocol error) interrupts */ - CLEAR_BIT(hspi->Instance->CR1, (SPI_CR2_RXNEIE | SPI_CR2_TXEIE | SPI_CR2_ERRIE)); - CLEAR_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR)); - - /* Restore SPI State to Ready */ - hspi->State = HAL_SPI_STATE_READY; - - /* Disable the SPI DMA requests if enabled */ - if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))||(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))) - { - CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); - - /* Abort the SPI DMA Rx channel */ - if(hspi->hdmarx != NULL) - { - /* Set the SPI DMA Abort callback : - will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ - hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; - - /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) - { - /* Call Directly hspi->hdmarx->XferAbortCallback function in case of error */ - hspi->hdmarx->XferAbortCallback(hspi->hdmarx); - } - } - /* Abort the SPI DMA Tx channel */ - if(hspi->hdmatx != NULL) - { - /* Set the SPI DMA Abort callback : - will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ - hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; - - /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) - { - /* Call Directly hspi->hdmatx->XferAbortCallback function in case of error */ - hspi->hdmatx->XferAbortCallback(hspi->hdmatx); - } - } - } - else - { - /* Call user error callback */ - HAL_SPI_ErrorCallback(hspi); - } - } - } -} - -/** - * @brief Tx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_TxCpltCallback should be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_RxCpltCallback should be implemented in the user file - */ -} - -/** - * @brief Tx and Rx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_TxRxCpltCallback should be implemented in the user file - */ -} - -/** - * @brief Tx Half Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_TxHalfCpltCallback should be implemented in the user file - */ -} - -/** - * @brief Rx Half Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file - */ -} - -/** - * @brief Tx and Rx Half Transfer callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file - */ -} - -/** - * @brief SPI error callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_ErrorCallback should be implemented in the user file - */ - /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes - and user can use HAL_SPI_GetError() API to check the latest error occurred - */ -} - -/** - * @} - */ - -/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief SPI control functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the SPI. - (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral - (+) HAL_SPI_GetError() check in run-time Errors occurring during communication -@endverbatim - * @{ - */ - -/** - * @brief Return the SPI handle state. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval SPI state - */ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) -{ - /* Return SPI handle state */ - return hspi->State; -} - -/** - * @brief Return the SPI error code. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval SPI error code in bitmap format - */ -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) -{ - return hspi->ErrorCode; -} - -/** - * @} - */ - - -/** - * @} - */ - -/** @addtogroup SPI_Private_Functions - * @brief Private functions - * @{ - */ - -/** - * @brief DMA SPI transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* DMA Normal Mode */ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) - { - /* Disable Tx DMA Request */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - - /* Check the end of the transaction */ - if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_FLAG; - } - - /* Clear overrun flag in 2 Lines communication mode because received data is not read */ - if(hspi->Init.Direction == SPI_DIRECTION_2LINES) - { - __HAL_SPI_CLEAR_OVRFLAG(hspi); - } - - hspi->TxXferCount = 0; - hspi->State = HAL_SPI_STATE_READY; - - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - HAL_SPI_ErrorCallback(hspi); - return; - } - } - HAL_SPI_TxCpltCallback(hspi); -} - -/** - * @brief DMA SPI receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* DMA Normal mode */ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) - { - -#if (USE_SPI_CRC != 0U) - __IO uint16_t tmpreg; - /* CRC handling */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* Wait until TXE flag */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK) - { - /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; - } - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - tmpreg = hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ - } - else - { - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ - - if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) - { - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK) - { - /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; - } - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ - } - } - } -#endif - - /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); - - /* Check the end of the transaction */ - if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK) - { - hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; - } - - hspi->RxXferCount = 0; - hspi->State = HAL_SPI_STATE_READY; - -#if (USE_SPI_CRC != 0U) - /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) - { - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - } -#endif - - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - HAL_SPI_ErrorCallback(hspi); - return; - } - } - HAL_SPI_RxCpltCallback(hspi); -} - -/** - * @brief DMA SPI transmit receive process complete callback. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; -#if (USE_SPI_CRC != 0U) - __IO uint16_t tmpreg; - /* CRC handling */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT)) - { - if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK) - { - /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; - } - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ - } - else - { - if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK) - { - /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; - } - tmpreg = hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ - } - } -#endif - - /* Check the end of the transaction */ - if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_FLAG; - } - - /* Disable Rx/Tx DMA Request */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); - - hspi->TxXferCount = 0; - hspi->RxXferCount = 0; - hspi->State = HAL_SPI_STATE_READY; - -#if (USE_SPI_CRC != 0U) - /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) - { - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - } -#endif - - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - HAL_SPI_ErrorCallback(hspi); - return; - } - HAL_SPI_TxRxCpltCallback(hspi); -} - -/** - * @brief DMA SPI half transmit process complete callback. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - HAL_SPI_TxHalfCpltCallback(hspi); -} - -/** - * @brief DMA SPI half receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - HAL_SPI_RxHalfCpltCallback(hspi); -} - -/** - * @brief DMA SPI half transmit receive process complete callback. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - HAL_SPI_TxRxHalfCpltCallback(hspi); -} - -/** - * @brief DMA SPI communication error callback. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMAError(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Stop the disable DMA transfer on SPI side */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); - - hspi->ErrorCode|= HAL_SPI_ERROR_DMA; - hspi->State = HAL_SPI_STATE_READY; - HAL_SPI_ErrorCallback(hspi); -} - -/** - * @brief DMA SPI communication abort callback - * (To be called at end of DMA Abort procedure). - * @param hdma: DMA handle. - * @retval None - */ -static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hspi->RxXferCount = 0U; - hspi->TxXferCount = 0U; - - HAL_SPI_ErrorCallback(hspi); -} - -/** - * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) -{ - /* Receive data in packing mode */ - if(hspi->RxXferCount > 1) - { - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount -= 2; - if(hspi->RxXferCount == 1) - { - /* set fiforxthreshold according the reception data length: 8bit */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - } - /* Receive data in 8 Bit mode */ - else - { - *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR); - hspi->RxXferCount--; - } - - /* check end of the reception */ - if(hspi->RxXferCount == 0) - { -#if (USE_SPI_CRC != 0U) - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - hspi->RxISR = SPI_2linesRxISR_8BITCRC; - return; - } -#endif - - /* Disable RXNE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); - - if(hspi->TxXferCount == 0) - { - SPI_CloseRxTx_ISR(hspi); - } - } -} - -#if (USE_SPI_CRC != 0U) -/** - * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) -{ - __IO uint8_t tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); - UNUSED(tmpreg); /* To avoid GCC warning */ - - hspi->CRCSize--; - - /* check end of the reception */ - if(hspi->CRCSize == 0) - { - /* Disable RXNE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); - - if(hspi->TxXferCount == 0) - { - SPI_CloseRxTx_ISR(hspi); - } - } -} -#endif - -/** - * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) -{ - /* Transmit data in packing Bit mode */ - if(hspi->TxXferCount >= 2) - { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2; - } - /* Transmit data in 8 Bit mode */ - else - { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); - hspi->TxXferCount--; - } - - /* check the end of the transmission */ - if(hspi->TxXferCount == 0) - { -#if (USE_SPI_CRC != 0U) - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; - } -#endif - - /* Disable TXE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); - - if(hspi->RxXferCount == 0) - { - SPI_CloseRxTx_ISR(hspi); - } - } -} - -/** - * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) -{ - /* Receive data in 16 Bit mode */ - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - - if(hspi->RxXferCount == 0) - { -#if (USE_SPI_CRC != 0U) - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - hspi->RxISR = SPI_2linesRxISR_16BITCRC; - return; - } -#endif - - /* Disable RXNE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); - - if(hspi->TxXferCount == 0) - { - SPI_CloseRxTx_ISR(hspi); - } - } -} - -#if (USE_SPI_CRC != 0U) -/** - * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) -{ - /* Receive data in 16 Bit mode */ - __IO uint16_t tmpreg = hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ - - /* Disable RXNE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); - - SPI_CloseRxTx_ISR(hspi); -} -#endif - -/** - * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) -{ - /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; - - /* Enable CRC Transmission */ - if(hspi->TxXferCount == 0) - { -#if (USE_SPI_CRC != 0U) - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; - } -#endif - - /* Disable TXE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); - - if(hspi->RxXferCount == 0) - { - SPI_CloseRxTx_ISR(hspi); - } - } -} - -#if (USE_SPI_CRC != 0U) -/** - * @brief Manage the CRC 8-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) -{ - __IO uint8_t tmpreg; - tmpreg = *((__IO uint8_t*)&hspi->Instance->DR); - - UNUSED(tmpreg); /* To avoid GCC warning */ - - hspi->CRCSize--; - - if(hspi->CRCSize == 0) - { - SPI_CloseRx_ISR(hspi); - } -} -#endif - -/** - * @brief Manage the receive 8-bit in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) -{ - *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR); - hspi->RxXferCount--; - -#if (USE_SPI_CRC != 0U) - /* Enable CRC Transmission */ - if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) - { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; - } -#endif - - if(hspi->RxXferCount == 0) - { -#if (USE_SPI_CRC != 0U) - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - hspi->RxISR = SPI_RxISR_8BITCRC; - return; - } -#endif - SPI_CloseRx_ISR(hspi); - } -} - -#if (USE_SPI_CRC != 0U) -/** - * @brief Manage the CRC 16-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) -{ - __IO uint16_t tmpreg; - - tmpreg = hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ - - /* Disable RXNE and ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - - SPI_CloseRx_ISR(hspi); -} -#endif - -/** - * @brief Manage the 16-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) -{ - *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; -#if (USE_SPI_CRC != 0U) - /* Enable CRC Transmission */ - if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) - { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; - } -#endif - if(hspi->RxXferCount == 0) - { -#if (USE_SPI_CRC != 0U) - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - hspi->RxISR = SPI_RxISR_16BITCRC; - return; - } -#endif - SPI_CloseRx_ISR(hspi); - } -} - -/** - * @brief Handle the data 8-bit transmit in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) -{ - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); - hspi->TxXferCount--; - - if(hspi->TxXferCount == 0) - { -#if (USE_SPI_CRC != 0U) - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* Enable CRC Transmission */ - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; - } -#endif - SPI_CloseTx_ISR(hspi); - } -} - -/** - * @brief Handle the data 16-bit transmit in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) -{ - /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; - - if(hspi->TxXferCount == 0) - { -#if (USE_SPI_CRC != 0U) - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* Enable CRC Transmission */ - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; - } -#endif - SPI_CloseTx_ISR(hspi); - } -} - -/** - * @brief Handle SPI Communication Timeout. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param Flag : SPI flag to check - * @param State : flag state to check - * @param Timeout : Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - while((hspi->Instance->SR & Flag) != State) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout)) - { - /* Disable the SPI and reset the CRC: the CRC value should be cleared - on both master and slave sides in order to resynchronize the master - and slave for their respective CRC calculation */ - - /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - - if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) - { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - } - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } - - hspi->State= HAL_SPI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief Handle SPI FIFO Communication Timeout. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param Fifo : Fifo to check - * @param State : Fifo state to check - * @param Timeout : Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout) -{ - __IO uint8_t tmpreg; - uint32_t tickstart = HAL_GetTick(); - - while((hspi->Instance->SR & Fifo) != State) - { - if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) - { - tmpreg = *((__IO uint8_t*)&hspi->Instance->DR); - UNUSED(tmpreg); /* To avoid GCC warning */ - } - - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout)) - { - /* Disable the SPI and reset the CRC: the CRC value should be cleared - on both master and slave sides in order to resynchronize the master - and slave for their respective CRC calculation */ - - /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - - if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) - { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - } - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } - - hspi->State = HAL_SPI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief Handle the check of the RX transaction complete. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param Timeout : Timeout duration - * @retval None - */ -static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout) -{ - if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) - { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - } - - /* Control the BSY flag */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK) - { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; - return HAL_TIMEOUT; - } - - if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) - { - /* Empty the FRLVL fifo */ - if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK) - { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief Handle the check of the RXTX or TX transaction complete. - * @param hspi: SPI handle - * @param Timeout : Timeout duration - */ -static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout) -{ - /* Procedure to check the transaction complete */ - if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK) - { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; - return HAL_TIMEOUT; - } - if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK) - { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; - return HAL_TIMEOUT; - } - /* Control the BSY flag */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK) - { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; - return HAL_TIMEOUT; - } - return HAL_OK; -} - -/** - * @brief Handle the end of the RXTX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) -{ - /* Disable ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); - - /* Check the end of the transaction */ - if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK) - { - hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; - } - -#if (USE_SPI_CRC != 0U) - /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) - { - hspi->State = HAL_SPI_STATE_READY; - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - HAL_SPI_ErrorCallback(hspi); - } - else - { -#endif - if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) - { - if(hspi->State == HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_READY; - HAL_SPI_RxCpltCallback(hspi); - } - else - { - hspi->State = HAL_SPI_STATE_READY; - HAL_SPI_TxRxCpltCallback(hspi); - } - } - else - { - hspi->State = HAL_SPI_STATE_READY; - HAL_SPI_ErrorCallback(hspi); - } -#if (USE_SPI_CRC != 0U) - } -#endif -} - -/** - * @brief Handle the end of the RX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) -{ - /* Disable RXNE and ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - - /* Check the end of the transaction */ - if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK) - { - hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; - } - hspi->State = HAL_SPI_STATE_READY; -#if (USE_SPI_CRC != 0U) - /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) - { - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - HAL_SPI_ErrorCallback(hspi); - } - else - { -#endif - if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) - { - HAL_SPI_RxCpltCallback(hspi); - } - else - { - HAL_SPI_ErrorCallback(hspi); - } -#if (USE_SPI_CRC != 0U) - } -#endif -} - -/** - * @brief Handle the end of the TX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) -{ - /* Disable TXE and ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); - - /* Check the end of the transaction */ - if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK) - { - hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; - } - - /* Clear overrun flag in 2 Lines communication mode because received is not read */ - if(hspi->Init.Direction == SPI_DIRECTION_2LINES) - { - __HAL_SPI_CLEAR_OVRFLAG(hspi); - } - - hspi->State = HAL_SPI_STATE_READY; - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - HAL_SPI_ErrorCallback(hspi); - } - else - { - HAL_SPI_TxCpltCallback(hspi); - } -} - -/** - * @} - */ - -#endif /* HAL_SPI_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sram.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sram.c deleted file mode 100644 index 1d26607..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sram.c +++ /dev/null @@ -1,690 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_sram.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief SRAM HAL module driver. - * This file provides a generic firmware to drive SRAM memories - * mounted as external device. - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - This driver is a generic layered driver which contains a set of APIs used to - control SRAM memories. It uses the FMC layer functions to interface - with SRAM devices. - The following sequence should be followed to configure the FMC to interface - with SRAM/PSRAM memories: - - (#) Declare a SRAM_HandleTypeDef handle structure, for example: - SRAM_HandleTypeDef hsram; and: - - (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed - values of the structure member. - - (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined - base register instance for NOR or SRAM device - - (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined - base register instance for NOR or SRAM extended mode - - (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended - mode timings; for example: - FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming; - and fill its fields with the allowed values of the structure member. - - (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function - performs the following sequence: - - (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit() - (##) Control register configuration using the FMC NORSRAM interface function - FMC_NORSRAM_Init() - (##) Timing register configuration using the FMC NORSRAM interface function - FMC_NORSRAM_Timing_Init() - (##) Extended mode Timing register configuration using the FMC NORSRAM interface function - FMC_NORSRAM_Extended_Timing_Init() - (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE() - - (#) At this stage you can perform read/write accesses from/to the memory connected - to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the - following APIs: - (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access - (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer - - (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/ - HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation - - (#) You can continuously monitor the SRAM device HAL state by calling the function - HAL_SRAM_GetState() - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup SRAM SRAM - * @brief SRAM driver modules - * @{ - */ -#ifdef HAL_SRAM_MODULE_ENABLED -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup SRAM_Exported_Functions SRAM Exported Functions - * @{ - */ - -/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. - * - @verbatim - ============================================================================== - ##### SRAM Initialization and de_initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to initialize/de-initialize - the SRAM memory - -@endverbatim - * @{ - */ - -/** - * @brief Performs the SRAM device initialization sequence - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param Timing: Pointer to SRAM control timing structure - * @param ExtTiming: Pointer to SRAM extended mode timing structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) -{ - /* Check the SRAM handle parameter */ - if(hsram == NULL) - { - return HAL_ERROR; - } - - if(hsram->State == HAL_SRAM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hsram->Lock = HAL_UNLOCKED; - /* Initialize the low level hardware (MSP) */ - HAL_SRAM_MspInit(hsram); - } - - /* Initialize SRAM control Interface */ - FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init)); - - /* Initialize SRAM timing Interface */ - FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); - - /* Initialize SRAM extended mode timing Interface */ - FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode); - - /* Enable the NORSRAM device */ - __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); - - return HAL_OK; -} - -/** - * @brief Performs the SRAM device De-initialization sequence. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) -{ - /* De-Initialize the low level hardware (MSP) */ - HAL_SRAM_MspDeInit(hsram); - - /* Configure the SRAM registers with their reset values */ - FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); - - hsram->State = HAL_SRAM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief SRAM MSP Init. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval None - */ -__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsram); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SRAM_MspInit could be implemented in the user file - */ -} - -/** - * @brief SRAM MSP DeInit. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval None - */ -__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsram); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SRAM_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief DMA transfer complete callback. - * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval None - */ -__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file - */ -} - -/** - * @brief DMA transfer complete error callback. - * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval None - */ -__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions - * @brief Input Output and memory control functions - * - @verbatim - ============================================================================== - ##### SRAM Input and Output functions ##### - ============================================================================== - [..] - This section provides functions allowing to use and control the SRAM memory - -@endverbatim - * @{ - */ - -/** - * @brief Reads 8-bit buffer from SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) -{ - __IO uint8_t * psramaddress = (uint8_t *)pAddress; - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Read data from memory */ - for(; BufferSize != 0; BufferSize--) - { - *pDstBuffer = *(__IO uint8_t *)psramaddress; - pDstBuffer++; - psramaddress++; - } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Writes 8-bit buffer to SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) -{ - __IO uint8_t * psramaddress = (uint8_t *)pAddress; - - /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Write data to memory */ - for(; BufferSize != 0; BufferSize--) - { - *(__IO uint8_t *)psramaddress = *pSrcBuffer; - pSrcBuffer++; - psramaddress++; - } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Reads 16-bit buffer from SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) -{ - __IO uint16_t * psramaddress = (uint16_t *)pAddress; - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Read data from memory */ - for(; BufferSize != 0; BufferSize--) - { - *pDstBuffer = *(__IO uint16_t *)psramaddress; - pDstBuffer++; - psramaddress++; - } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Writes 16-bit buffer to SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) -{ - __IO uint16_t * psramaddress = (uint16_t *)pAddress; - - /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Write data to memory */ - for(; BufferSize != 0; BufferSize--) - { - *(__IO uint16_t *)psramaddress = *pSrcBuffer; - pSrcBuffer++; - psramaddress++; - } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Reads 32-bit buffer from SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) -{ - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Read data from memory */ - for(; BufferSize != 0; BufferSize--) - { - *pDstBuffer = *(__IO uint32_t *)pAddress; - pDstBuffer++; - pAddress++; - } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Writes 32-bit buffer to SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) -{ - /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Write data to memory */ - for(; BufferSize != 0; BufferSize--) - { - *(__IO uint32_t *)pAddress = *pSrcBuffer; - pSrcBuffer++; - pAddress++; - } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Reads a Words data from the SRAM memory using DMA transfer. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) -{ - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Configure DMA user callbacks */ - hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; - hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Writes a Words data buffer to SRAM memory using DMA transfer. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) -{ - /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Configure DMA user callbacks */ - hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; - hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup SRAM_Exported_Functions_Group3 Control functions - * @brief Control functions - * -@verbatim - ============================================================================== - ##### SRAM Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the SRAM interface. - -@endverbatim - * @{ - */ - -/** - * @brief Enables dynamically SRAM write operation. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) -{ - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Enable write operation */ - FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Disables dynamically SRAM write operation. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) -{ - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Disable write operation */ - FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_PROTECTED; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### SRAM State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the SRAM controller - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the SRAM controller state - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval HAL state - */ -HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) -{ - return hsram->State; -} - -/** - * @} - */ - -/** - * @} - */ -#endif /* HAL_SRAM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c deleted file mode 100644 index 8272fcb..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c +++ /dev/null @@ -1,5521 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_tim.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer (TIM) peripheral: - * + Time Base Initialization - * + Time Base Start - * + Time Base Start Interruption - * + Time Base Start DMA - * + Time Output Compare/PWM Initialization - * + Time Output Compare/PWM Channel Configuration - * + Time Output Compare/PWM Start - * + Time Output Compare/PWM Start Interruption - * + Time Output Compare/PWM Start DMA - * + Time Input Capture Initialization - * + Time Input Capture Channel Configuration - * + Time Input Capture Start - * + Time Input Capture Start Interruption - * + Time Input Capture Start DMA - * + Time One Pulse Initialization - * + Time One Pulse Channel Configuration - * + Time One Pulse Start - * + Time Encoder Interface Initialization - * + Time Encoder Interface Start - * + Time Encoder Interface Start Interruption - * + Time Encoder Interface Start DMA - * + Commutation Event configuration with Interruption and DMA - * + Time OCRef clear configuration - * + Time External Clock configuration - @verbatim - ============================================================================== - ##### TIMER Generic features ##### - ============================================================================== - [..] The Timer features include: - (#) 16-bit up, down, up/down auto-reload counter. - (#) 16-bit programmable prescaler allowing dividing (also on the fly) the - counter clock frequency either by any factor between 1 and 65536. - (#) Up to 4 independent channels for: - (++) Input Capture - (++) Output Compare - (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the TIM low level resources by implementing the following functions - depending from feature used : - (++) Time Base : HAL_TIM_Base_MspInit() - (++) Input Capture : HAL_TIM_IC_MspInit() - (++) Output Compare : HAL_TIM_OC_MspInit() - (++) PWM generation : HAL_TIM_PWM_MspInit() - (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() - (++) Encoder mode output : HAL_TIM_Encoder_MspInit() - - (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); - (##) TIM pins configuration - (+++) Enable the clock for the TIM GPIOs using the following function: - __GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - - (#) The external Clock can be configured, if needed (the default clock is the - internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before - any start function. - - (#) Configure the TIM in the desired functioning mode using one of the - initialization function of this driver: - (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base - (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an - Output Compare signal. - (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a - PWM signal. - (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an - external signal. - (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer - in One Pulse Mode. - (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. - - (#) Activate the TIM peripheral using one of the start functions depending from the feature used: - (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() - (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() - (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() - (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() - (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() - (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). - - (#) The DMA Burst is managed with the two following functions: - HAL_TIM_DMABurst_WriteStart() - HAL_TIM_DMABurst_ReadStart() - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup TIM TIM - * @brief TIM HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @addtogroup TIM_Private_Functions - * @{ - */ -/* Private function prototypes -----------------------------------------------*/ -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); - -static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx); -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); -static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup TIM_Exported_Functions TIM Exported Functions - * @{ - */ - -/** @defgroup TIM_Exported_Functions_Group1 Time Base functions - * @brief Time Base functions - * -@verbatim - ============================================================================== - ##### Time Base functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM base. - (+) De-initialize the TIM base. - (+) Start the Time Base. - (+) Stop the Time Base. - (+) Start the Time Base and enable interrupt. - (+) Stop the Time Base and disable interrupt. - (+) Start the Time Base and enable DMA transfer. - (+) Stop the Time Base and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Time base Unit according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Set the Time Base configuration */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM Base peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Base MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_Base_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Base MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_Base_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Base generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Change the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Enable the TIM Update interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Disable the TIM Update interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length); - - /* Enable the TIM Update DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions - * @brief Time Output Compare functions - * -@verbatim - ============================================================================== - ##### Time Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Output Compare. - (+) De-initialize the TIM Output Compare. - (+) Start the Time Output Compare. - (+) Stop the Time Output Compare. - (+) Start the Time Output Compare and enable interrupt. - (+) Stop the Time Output Compare and disable interrupt. - (+) Start the Time Output Compare and enable DMA transfer. - (+) Stop the Time Output Compare and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Output Compare according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Init the base time for the Output Compare */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Output Compare MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_OC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Output Compare MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_OC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Output Compare signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions - * @brief Time PWM functions - * -@verbatim - ============================================================================== - ##### Time PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM OPWM. - (+) De-initialize the TIM PWM. - (+) Start the Time PWM. - (+) Stop the Time PWM. - (+) Start the Time PWM and enable interrupt. - (+) Stop the Time PWM and disable interrupt. - (+) Start the Time PWM and enable DMA transfer. - (+) Stop the Time PWM and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM PWM Time Base according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Init the base time for the PWM */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM PWM MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM PWM MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the PWM signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the PWM signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Output Capture/Compare 3 request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions - * @brief Time Input Capture functions - * -@verbatim - ============================================================================== - ##### Time Input Capture functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Input Capture. - (+) De-initialize the TIM Input Capture. - (+) Start the Time Input Capture. - (+) Stop the Time Input Capture. - (+) Start the Time Input Capture and enable interrupt. - (+) Stop the Time Input Capture and disable interrupt. - (+) Start the Time Input Capture and enable DMA transfer. - (+) Stop the Time Input Capture and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Input Capture Time base according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Init the base time for the input capture */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM INput Capture MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_IC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Input Capture MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_IC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Input Capture measurement. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Input Capture measurement on in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement on in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions - * @brief Time One Pulse functions - * -@verbatim - ============================================================================== - ##### Time One Pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM One Pulse. - (+) De-initialize the TIM One Pulse. - (+) Start the Time One Pulse. - (+) Stop the Time One Pulse. - (+) Start the Time One Pulse and enable interrupt. - (+) Stop the Time One Pulse and disable interrupt. - (+) Start the Time One Pulse and enable DMA transfer. - (+) Stop the Time One Pulse and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM One Pulse Time Base according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param OnePulseMode: Select the One pulse mode. - * This parameter can be one of the following values: - * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. - * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_OPM_MODE(OnePulseMode)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OnePulse_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Configure the Time base in the One Pulse Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Reset the OPM Bit */ - htim->Instance->CR1 &= ~TIM_CR1_OPM; - - /* Configure the OPM Mode */ - htim->Instance->CR1 |= OnePulseMode; - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM One Pulse - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_OnePulse_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM One Pulse MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM One Pulse MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM One Pulse signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param OutputChannel : TIM Channels to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param OutputChannel : TIM Channels to be disable. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param OutputChannel : TIM Channels to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param OutputChannel : TIM Channels to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions - * @brief Time Encoder functions - * -@verbatim - ============================================================================== - ##### Time Encoder functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Encoder. - (+) De-initialize the TIM Encoder. - (+) Start the Time Encoder. - (+) Stop the Time Encoder. - (+) Start the Time Encoder and enable interrupt. - (+) Stop the Time Encoder and disable interrupt. - (+) Start the Time Encoder and enable DMA transfer. - (+) Stop the Time Encoder and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Encoder Interface and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param sConfig: TIM Encoder Interface configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) -{ - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_Encoder_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Reset the SMS bits */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - - /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = htim->Instance->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = htim->Instance->CCER; - - /* Set the encoder Mode */ - tmpsmcr |= sConfig->EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); - tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8)); - - /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ - tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); - tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); - tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8); - tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12); - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); - tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); - tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4); - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Write to TIMx CCMR1 */ - htim->Instance->CCMR1 = tmpccmr1; - - /* Write to TIMx CCER */ - htim->Instance->CCER = tmpccer; - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM Encoder interface - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Encoder_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Encoder Interface MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Encoder Interface MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Encoder Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Enable the encoder interface channels */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - break; - } - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - break; - } - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - break; - } - } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - break; - } - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - break; - } - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - break; - } - } - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Enable the encoder interface channels */ - /* Enable the capture compare Interrupts 1 and/or 2 */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if(Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - else if(Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 and 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @param pData1: The destination Buffer address for IC1. - * @param pData2: The destination Buffer address for IC2. - * @param Length: The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError; - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - } - break; - - case TIM_CHANNEL_ALL: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length); - - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - default: - break; - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if(Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - else if(Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 and 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ -/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief IRQ handler management - * -@verbatim - ============================================================================== - ##### IRQ handler management ##### - ============================================================================== - [..] - This section provides Timer IRQ handler function. - -@endverbatim - * @{ - */ -/** - * @brief This function handles TIM interrupts requests. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) -{ - /* Capture compare 1 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET) - { - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - } - /* Capture compare 2 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 3 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 4 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* TIM Update event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); - HAL_TIM_PeriodElapsedCallback(htim); - } - } - /* TIM Break input event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); - HAL_TIMEx_BreakCallback(htim); - } - } - - /* TIM Break input event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); - HAL_TIMEx_BreakCallback(htim); - } - } - - /* TIM Trigger detection event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); - HAL_TIM_TriggerCallback(htim); - } - } - /* TIM commutation event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); - HAL_TIMEx_CommutationCallback(htim); - } - } -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. - (+) Configure External Clock source. - (+) Configure Complementary channels, break features and dead time. - (+) Configure Master and the Slave synchronization. - (+) Configure the DMA Burst Mode. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIM Output Compare Channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param sConfig: TIM Output Compare configuration structure - * @param Channel: TIM Channels to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - - /* Check input state */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (Channel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 1 in Output Compare */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 2 in Output Compare */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_3: - { - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 3 in Output Compare */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_4: - { - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 4 in Output Compare */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - } - break; - - default: - break; - } - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Input Capture Channels according to the specified - * parameters in the TIM_IC_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param sConfig: TIM Input Capture configuration structure - * @param Channel: TIM Channels to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); - assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - if (Channel == TIM_CHANNEL_1) - { - /* TI1 Configuration */ - TIM_TI1_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Set the IC1PSC value */ - htim->Instance->CCMR1 |= sConfig->ICPrescaler; - } - else if (Channel == TIM_CHANNEL_2) - { - /* TI2 Configuration */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Set the IC2PSC value */ - htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8); - } - else if (Channel == TIM_CHANNEL_3) - { - /* TI3 Configuration */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - TIM_TI3_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC3PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; - - /* Set the IC3PSC value */ - htim->Instance->CCMR2 |= sConfig->ICPrescaler; - } - else - { - /* TI4 Configuration */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - TIM_TI4_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC4PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; - - /* Set the IC4PSC value */ - htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8); - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM PWM channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param sConfig: TIM PWM configuration structure - * @param Channel: TIM Channels to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) -{ - __HAL_LOCK(htim); - - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (Channel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - /* Configure the Channel 1 in PWM mode */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode; - } - break; - - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - /* Configure the Channel 2 in PWM mode */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode << 8; - } - break; - - case TIM_CHANNEL_3: - { - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - /* Configure the Channel 3 in PWM mode */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode; - } - break; - - case TIM_CHANNEL_4: - { - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - /* Configure the Channel 4 in PWM mode */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; - } - break; - - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM One Pulse Channels according to the specified - * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param sConfig: TIM One Pulse configuration structure - * @param OutputChannel: TIM Channels to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel: TIM Channels to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel) -{ - TIM_OC_InitTypeDef temp1; - - /* Check the parameters */ - assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); - assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); - - if(OutputChannel != InputChannel) - { - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Extract the Output compare configuration from sConfig structure */ - temp1.OCMode = sConfig->OCMode; - temp1.Pulse = sConfig->Pulse; - temp1.OCPolarity = sConfig->OCPolarity; - temp1.OCNPolarity = sConfig->OCNPolarity; - temp1.OCIdleState = sConfig->OCIdleState; - temp1.OCNIdleState = sConfig->OCNIdleState; - - switch (OutputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_OC1_SetConfig(htim->Instance, &temp1); - } - break; - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_OC2_SetConfig(htim->Instance, &temp1); - } - break; - default: - break; - } - switch (InputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1FP1; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - } - break; - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI2FP2; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - } - break; - - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write. - * This parameters can be on of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc: TIM DMA Request sources. - * This parameters can be on of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer: The Buffer address. - * @param BurstLength: DMA Burst length. This parameter can be one value - * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t* BurstBuffer, uint32_t BurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((BurstBuffer == 0 ) && (BurstLength > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_COM: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_TRIGGER: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - default: - break; - } - /* configure the DMA Burst Mode */ - htim->Instance->DCR = BurstBaseAddress | BurstLength; - - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM DMA Burst mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param BurstRequestSrc: TIM DMA Request sources to disable - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA channel) */ - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); - } - break; - case TIM_DMA_CC1: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); - } - break; - case TIM_DMA_CC2: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); - } - break; - case TIM_DMA_CC3: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); - } - break; - case TIM_DMA_CC4: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); - } - break; - case TIM_DMA_COM: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); - } - break; - case TIM_DMA_TRIGGER: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); - } - break; - default: - break; - } - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read. - * This parameters can be on of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc: TIM DMA Request sources. - * This parameters can be on of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer: The Buffer address. - * @param BurstLength: DMA Burst length. This parameter can be one value - * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t *BurstBuffer, uint32_t BurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((BurstBuffer == 0 ) && (BurstLength > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_COM: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_TRIGGER: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - default: - break; - } - - /* configure the DMA Burst Mode */ - htim->Instance->DCR = BurstBaseAddress | BurstLength; - - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop the DMA burst reading - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param BurstRequestSrc: TIM DMA Request sources to disable. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA channel) */ - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); - } - break; - case TIM_DMA_CC1: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); - } - break; - case TIM_DMA_CC2: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); - } - break; - case TIM_DMA_CC3: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); - } - break; - case TIM_DMA_CC4: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); - } - break; - case TIM_DMA_COM: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); - } - break; - case TIM_DMA_TRIGGER: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); - } - break; - default: - break; - } - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Generate a software event - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param EventSource: specifies the event source. - * This parameter can be one of the following values: - * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source - * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EVENTSOURCE_COM: Timer COM event source - * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source - * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source - * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source - * @note TIM6 and TIM7 can only generate an update event. - * @note TIM_EVENTSOURCE_COM, TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are used only with TIM1 and TIM8. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_EVENT_SOURCE(EventSource)); - - /* Process Locked */ - __HAL_LOCK(htim); - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Set the event sources */ - htim->Instance->EGR = EventSource; - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configures the OCRef clear feature - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that - * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel: specifies the TIM Channel. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR) - { - assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); - assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); - assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); - - TIM_ETR_SetConfig(htim->Instance, - sClearInputConfig->ClearInputPrescaler, - sClearInputConfig->ClearInputPolarity, - sClearInputConfig->ClearInputFilter); - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; - } - else - { - /* Disable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; - } - } - break; - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; - } - else - { - /* Disable the Ocref clear feature for Channel 2 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; - } - } - break; - case TIM_CHANNEL_3: - { - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; - } - else - { - /* Disable the Ocref clear feature for Channel 3 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; - } - } - break; - case TIM_CHANNEL_4: - { - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; - } - else - { - /* Disable the Ocref clear feature for Channel 4 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; - } - } - break; - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the clock source to be used - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that - * contains the clock source information for the TIM peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) -{ - uint32_t tmpsmcr = 0; - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); - - /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ - tmpsmcr = htim->Instance->SMCR; - tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - htim->Instance->SMCR = tmpsmcr; - - switch (sClockSourceConfig->ClockSource) - { - case TIM_CLOCKSOURCE_INTERNAL: - { - assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Disable slave mode to clock the prescaler directly with the internal clock */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - } - break; - - case TIM_CLOCKSOURCE_ETRMODE1: - { - assert_param(IS_TIM_ETR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - /* Reset the SMS and TS Bits */ - tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); - /* Select the External clock mode1 and the ETRF trigger */ - tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - } - break; - - case TIM_CLOCKSOURCE_ETRMODE2: - { - assert_param(IS_TIM_ETR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - /* Enable the External clock mode2 */ - htim->Instance->SMCR |= TIM_SMCR_ECE; - } - break; - - case TIM_CLOCKSOURCE_TI1: - { - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI1 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); - } - break; - case TIM_CLOCKSOURCE_TI2: - { - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI1 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI2_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); - } - break; - case TIM_CLOCKSOURCE_TI1ED: - { - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - /* Check TI1 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); - } - break; - case TIM_CLOCKSOURCE_ITR0: - { - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); - } - break; - case TIM_CLOCKSOURCE_ITR1: - { - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); - } - break; - case TIM_CLOCKSOURCE_ITR2: - { - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); - } - break; - case TIM_CLOCKSOURCE_ITR3: - { - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3); - } - break; - - default: - break; - } - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Selects the signal connected to the TI1 input: direct from CH1_input - * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param TI1_Selection: Indicate whether or not channel 1 is connected to the - * output of a XOR gate. - * This parameter can be one of the following values: - * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input - * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 - * pins are connected to the TI1 input (XOR combination) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) -{ - uint32_t tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); - - /* Get the TIMx CR2 register value */ - tmpcr2 = htim->Instance->CR2; - - /* Reset the TI1 selection */ - tmpcr2 &= ~TIM_CR2_TI1S; - - /* Set the TI1 selection */ - tmpcr2 |= TI1_Selection; - - /* Write to TIMxCR2 */ - htim->Instance->CR2 = tmpcr2; - - return HAL_OK; -} - -/** - * @brief Configures the TIM in Slave mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) -{ - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Reset the Trigger Selection Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source */ - tmpsmcr |= sSlaveConfig->InputTrigger; - - /* Reset the slave mode Bits */ - tmpsmcr &= ~TIM_SMCR_SMS; - /* Set the slave mode */ - tmpsmcr |= sSlaveConfig->SlaveMode; - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Configure the trigger prescaler, filter, and polarity */ - switch (sSlaveConfig->InputTrigger) - { - case TIM_TS_ETRF: - { - /* Check the parameters */ - assert_param(IS_TIM_ETR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - /* Configure the ETR Trigger source */ - TIM_ETR_SetConfig(htim->Instance, - sSlaveConfig->TriggerPrescaler, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_TI1F_ED: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = htim->Instance->CCER; - htim->Instance->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = htim->Instance->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); - - /* Write to TIMx CCMR1 and CCER registers */ - htim->Instance->CCMR1 = tmpccmr1; - htim->Instance->CCER = tmpccer; - - } - break; - - case TIM_TS_TI1FP1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI1 Filter and Polarity */ - TIM_TI1_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_TI2FP2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI2 Filter and Polarity */ - TIM_TI2_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_ITR0: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR1: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR2: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR3: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIM in Slave mode in interrupt mode - * @param htim: TIM handle. - * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig) -{ - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); - - /* Enable Trigger Interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); - - /* Disable Trigger DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Read the captured value from Capture Compare unit - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval Captured value - */ -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpreg = 0; - - __HAL_LOCK(htim); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Return the capture 1 value */ - tmpreg = htim->Instance->CCR1; - - break; - } - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Return the capture 2 value */ - tmpreg = htim->Instance->CCR2; - - break; - } - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Return the capture 3 value */ - tmpreg = htim->Instance->CCR3; - - break; - } - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Return the capture 4 value */ - tmpreg = htim->Instance->CCR4; - - break; - } - - default: - break; - } - - __HAL_UNLOCK(htim); - return tmpreg; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions - * -@verbatim - ============================================================================== - ##### TIM Callbacks functions ##### - ============================================================================== - [..] - This section provides TIM callback functions: - (+) Timer Period elapsed callback - (+) Timer Output Compare callback - (+) Timer Input capture callback - (+) Timer Trigger callback - (+) Timer Error callback - -@endverbatim - * @{ - */ - -/** - * @brief Period elapsed callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file - */ - -} -/** - * @brief Output Compare callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file - */ -} -/** - * @brief Input Capture callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the __HAL_TIM_IC_CaptureCallback could be implemented in the user file - */ -} - -/** - * @brief PWM Pulse finished callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Trigger detection callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_TriggerCallback could be implemented in the user file - */ -} - -/** - * @brief Timer error callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Base state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM OC state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM PWM state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Input Capture state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM One Pulse Mode state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Encoder Mode state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @} - */ - -/** - * @brief TIM DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIM_ErrorCallback(htim); -} - -/** - * @brief TIM DMA Delay Pulse complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - - HAL_TIM_PWM_PulseFinishedCallback(htim); - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} -/** - * @brief TIM DMA Capture complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - - HAL_TIM_IC_CaptureCallback(htim); - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - -} - -/** - * @brief TIM DMA Period Elapse complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIM_PeriodElapsedCallback(htim); -} - -/** - * @brief TIM DMA Trigger callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIM_TriggerCallback(htim); -} - -/** - * @brief Time Base configuration - * @param TIMx: TIM peripheral - * @param Structure: pointer on TIM Time Base required parameters - * @retval None - */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) -{ - uint32_t tmpcr1 = 0; - tmpcr1 = TIMx->CR1; - - /* Set TIM Time Base Unit parameters ---------------------------------------*/ - if(IS_TIM_CC3_INSTANCE(TIMx) != RESET) - { - /* Select the Counter Mode */ - tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); - tmpcr1 |= Structure->CounterMode; - } - - if(IS_TIM_CC1_INSTANCE(TIMx) != RESET) - { - /* Set the clock division */ - tmpcr1 &= ~TIM_CR1_CKD; - tmpcr1 |= (uint32_t)Structure->ClockDivision; - } - - TIMx->CR1 = tmpcr1; - - /* Set the Auto-reload value */ - TIMx->ARR = (uint32_t)Structure->Period ; - - /* Set the Prescaler value */ - TIMx->PSC = (uint32_t)Structure->Prescaler; - - if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) - { - /* Set the Repetition Counter value */ - TIMx->RCR = Structure->RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler - and the repetition counter(only for TIM1 and TIM8) value immediately */ - TIMx->EGR = TIM_EGR_UG; -} - -/** - * @brief Time Output Compare 1 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure - * @retval None - */ -void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= ~TIM_CCER_CC1E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= ~TIM_CCMR1_OC1M; - tmpccmrx &= ~TIM_CCMR1_CC1S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC1P; - /* Set the Output Compare Polarity */ - tmpccer |= OC_Config->OCPolarity; - - - if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) - { - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC1NP; - /* Set the Output N Polarity */ - tmpccer |= OC_Config->OCNPolarity; - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC1NE; - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS1; - tmpcr2 &= ~TIM_CR2_OIS1N; - /* Set the Output Idle state */ - tmpcr2 |= OC_Config->OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= OC_Config->OCNIdleState; - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Time Output Compare 2 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure - * @retval None - */ -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR1_OC2M; - tmpccmrx &= ~TIM_CCMR1_CC2S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC2P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 4); - - if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) - { - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC2NP; - /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 4); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC2NE; - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS2; - tmpcr2 &= ~TIM_CR2_OIS2N; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 2); - /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 2); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Time Output Compare 3 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure - * @retval None - */ -void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the Channel 3: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC3E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC3M; - tmpccmrx &= ~TIM_CCMR2_CC3S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC3P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 8); - - if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) - { - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC3NP; - /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 8); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC3NE; - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS3; - tmpcr2 &= ~TIM_CR2_OIS3N; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 4); - /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 4); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Time Output Compare 4 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure - * @retval None - */ -void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= ~TIM_CCER_CC4E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC4M; - tmpccmrx &= ~TIM_CCMR2_CC4S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC4P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 12); - - /*if((TIMx == TIM1) || (TIMx == TIM8))*/ - if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) - { - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - /* Reset the Output Compare IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS4; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 6); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Time Output Compare 4 configuration - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param sSlaveConfig: The slave configuration structure - * @retval None - */ -static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig) -{ - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Reset the Trigger Selection Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source */ - tmpsmcr |= sSlaveConfig->InputTrigger; - - /* Reset the slave mode Bits */ - tmpsmcr &= ~TIM_SMCR_SMS; - /* Set the slave mode */ - tmpsmcr |= sSlaveConfig->SlaveMode; - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Configure the trigger prescaler, filter, and polarity */ - switch (sSlaveConfig->InputTrigger) - { - case TIM_TS_ETRF: - { - /* Check the parameters */ - assert_param(IS_TIM_ETR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - /* Configure the ETR Trigger source */ - TIM_ETR_SetConfig(htim->Instance, - sSlaveConfig->TriggerPrescaler, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_TI1F_ED: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = htim->Instance->CCER; - htim->Instance->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = htim->Instance->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); - - /* Write to TIMx CCMR1 and CCER registers */ - htim->Instance->CCMR1 = tmpccmr1; - htim->Instance->CCER = tmpccer; - - } - break; - - case TIM_TS_TI1FP1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI1 Filter and Polarity */ - TIM_TI1_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_TI2FP2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI2 Filter and Polarity */ - TIM_TI2_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_ITR0: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR1: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR2: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR3: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - default: - break; - } -} - -/** - * @brief Configure the TI1 as Input. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 - * (on channel2 path) is used as the input signal. Therefore CCMR1 must be - * protected against un-initialized filter and polarity values. - */ -void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input */ - if(IS_TIM_CC2_INSTANCE(TIMx) != RESET) - { - tmpccmr1 &= ~TIM_CCMR1_CC1S; - tmpccmr1 |= TIM_ICSelection; - } - else - { - tmpccmr1 |= TIM_CCMR1_CC1S_0; - } - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI1. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = TIMx->CCER; - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= (TIM_ICFilter << 4); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= TIM_ICPolarity; - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 - * (on channel1 path) is used as the input signal. Therefore CCMR1 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr1 &= ~TIM_CCMR1_CC2S; - tmpccmr1 |= (TIM_ICSelection << 8); - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI2. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ -uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= (TIM_ICFilter << 12); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (TIM_ICPolarity << 4); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= ~TIM_CCER_CC3E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC3S; - tmpccmr2 |= TIM_ICSelection; - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC3F; - tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F); - - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= ~TIM_CCER_CC4E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC4S; - tmpccmr2 |= (TIM_ICSelection << 8); - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC4F; - tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F); - - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer ; -} - -/** - * @brief Selects the Input Trigger source - * @param TIMx to select the TIM peripheral - * @param TIM_ITRx: The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx) -{ - uint32_t tmpsmcr = 0; - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source and the slave mode*/ - tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx to select the TIM peripheral - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) -{ - uint32_t tmpsmcr = 0; - - tmpsmcr = TIMx->SMCR; - - /* Reset the ETR Bits */ - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8))); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx to select the TIM peripheral - * @param Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param ChannelState: specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. - * @retval None - */ -void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(TIMx)); - assert_param(IS_TIM_CHANNELS(Channel)); - - tmp = TIM_CCER_CC1E << Channel; - - /* Reset the CCxE Bit */ - TIMx->CCER &= ~tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint32_t)(ChannelState << Channel); -} - - -/** - * @} - */ - -#endif /* HAL_TIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c deleted file mode 100644 index c6195fc..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c +++ /dev/null @@ -1,2574 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_tim_ex.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer extension peripheral: - * + Time Hall Sensor Interface Initialization - * + Time Hall Sensor Interface Start - * + Time Complementary signal bread and dead time configuration - * + Time Master and Slave synchronization configuration - * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) - * + Time OCRef clear configuration - * + Timer remapping capabilities configuration - @verbatim - ============================================================================== - ##### TIMER Extended features ##### - ============================================================================== - [..] - The Timer Extension features include: - (#) Complementary outputs with programmable dead-time for : - (++) Input Capture - (++) Output Compare - (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output - (#) Synchronization circuit to control the timer with external signals and to - interconnect several timers together. - (#) Break input to put the timer output signals in reset state or in a known state. - (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for - positioning purposes - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the TIM low level resources by implementing the following functions - depending from feature used : - (++) Complementary Output Compare : HAL_TIM_OC_MspInit() - (++) Complementary PWM generation : HAL_TIM_PWM_MspInit() - (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit() - (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit() - - (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); - (##) TIM pins configuration - (+++) Enable the clock for the TIM GPIOs using the following function: - __GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - - (#) The external Clock can be configured, if needed (the default clock is the - internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before - any start function. - - (#) Configure the TIM in the desired functioning mode using one of the - initialization function of this driver: - (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the - Timer Hall Sensor Interface and the commutation event with the corresponding - Interrupt and DMA request if needed (Note that One Timer is used to interface - with the Hall sensor Interface and another Timer should be used to use - the commutation event). - - (#) Activate the TIM peripheral using one of the start functions: - (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT() - (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() - (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() - (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). - - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup TIMEx TIMEx - * @brief TIM Extended HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define BDTR_BKF_SHIFT (16) -#define BDTR_BK2F_SHIFT (20) -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup TIMEx_Private_Functions - * @{ - */ -static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState); -static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -/** - * @} - */ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions - * @{ - */ - -/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions - * @brief Timer Hall Sensor functions - * -@verbatim - ============================================================================== - ##### Timer Hall Sensor functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure TIM HAL Sensor. - (+) De-initialize TIM HAL Sensor. - (+) Start the Hall Sensor Interface. - (+) Stop the Hall Sensor Interface. - (+) Start the Hall Sensor Interface and enable interrupts. - (+) Stop the Hall Sensor Interface and disable interrupts. - (+) Start the Hall Sensor Interface and enable DMA transfers. - (+) Stop the Hall Sensor Interface and disable DMA transfers. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Hall Sensor Interface and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param sConfig: TIM Hall Sensor configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) -{ - TIM_OC_InitTypeDef OC_Config; - - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIMEx_HallSensor_MspInit(htim); - - /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ - TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - /* Set the IC1PSC value */ - htim->Instance->CCMR1 |= sConfig->IC1Prescaler; - - /* Enable the Hall sensor interface (XOR function of the three inputs) */ - htim->Instance->CR2 |= TIM_CR2_TI1S; - - /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1F_ED; - - /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; - - /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ - OC_Config.OCFastMode = TIM_OCFAST_DISABLE; - OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; - OC_Config.OCMode = TIM_OCMODE_PWM2; - OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; - OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; - OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; - OC_Config.Pulse = sConfig->Commutation_Delay; - - TIM_OC2_SetConfig(htim->Instance, &OC_Config); - - /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 - register to 101 */ - htim->Instance->CR2 &= ~TIM_CR2_MMS; - htim->Instance->CR2 |= TIM_TRGO_OC2REF; - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM Hall Sensor interface - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIMEx_HallSensor_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Hall Sensor MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Hall Sensor MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Hall Sensor Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - - /* Enable the Input Capture channels 1 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall sensor Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1, 2 and 3 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Hall Sensor Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - - /* Enable the capture compare Interrupts 1 event */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the Input Capture channels 1 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall Sensor Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts event */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Hall Sensor Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - /* Enable the Input Capture channels 1 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Set the DMA Input Capture 1 Callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream for Capture 1*/ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); - - /* Enable the capture compare 1 Interrupt */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall Sensor Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - - /* Disable the capture compare Interrupts 1 event */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions - * @brief Timer Complementary Output Compare functions - * -@verbatim - ============================================================================== - ##### Timer Complementary Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary Output Compare/PWM. - (+) Stop the Complementary Output Compare/PWM. - (+) Start the Complementary Output Compare/PWM and enable interrupts. - (+) Stop the Complementary Output Compare/PWM and disable interrupts. - (+) Start the Complementary Output Compare/PWM and enable DMA transfers. - (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the TIM Output Compare signal generation on the complementary - * output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation on the complementary - * output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in interrupt mode - * on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in interrupt mode - * on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) - { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in DMA mode - * on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: -{ - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in DMA mode - * on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions - * @brief Timer Complementary PWM functions - * -@verbatim - ============================================================================== - ##### Timer Complementary PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary PWM. - (+) Stop the Complementary PWM. - (+) Start the Complementary PWM and enable interrupts. - (+) Stop the Complementary PWM and disable interrupts. - (+) Start the Complementary PWM and enable DMA transfers. - (+) Stop the Complementary PWM and disable DMA transfers. - (+) Start the Complementary Input Capture measurement. - (+) Stop the Complementary Input Capture. - (+) Start the Complementary Input Capture and enable interrupts. - (+) Stop the Complementary Input Capture and disable interrupts. - (+) Start the Complementary Input Capture and enable DMA transfers. - (+) Stop the Complementary Input Capture and disable DMA transfers. - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the PWM signal generation on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the PWM signal generation in interrupt mode on the - * complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation in interrupt mode on the - * complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) - { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM PWM signal generation in DMA mode on the - * complementary output - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM PWM signal generation in DMA mode on the complementary - * output - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions - * @brief Timer Complementary One Pulse functions - * -@verbatim - ============================================================================== - ##### Timer Complementary One Pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the TIM One Pulse signal generation on the complemetary - * output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param OutputChannel: TIM Channel to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) - { - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Enable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation on the complementary - * output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param OutputChannel: TIM Channel to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Disable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM One Pulse signal generation in interrupt mode on the - * complementary channel. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param OutputChannel: TIM Channel to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - /* Enable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Return function status */ - return HAL_OK; - } - -/** - * @brief Stops the TIM One Pulse signal generation in interrupt mode on the - * complementary channel. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param OutputChannel: TIM Channel to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - - /* Disable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. - (+) Configure External Clock source. - (+) Configure Complementary channels, break features and dead time. - (+) Configure Master and the Slave synchronization. - (+) Configure the commutation event in case of use of the Hall sensor interface. - (+) Configure the DMA Burst Mode. - -@endverbatim - * @{ - */ -/** - * @brief Configure the TIM commutation event sequence. - * @note This function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource: the Commutation Event source. - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configure the TIM commutation event sequence with interrupt. - * @note This function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource: the Commutation Event source. - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Enable the Commutation Interrupt Request */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configure the TIM commutation event sequence with DMA. - * @note This function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource: the Commutation Event source. - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Enable the Commutation DMA Request */ - /* Set the DMA Commutation Callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt; - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError; - - /* Enable the Commutation DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Output Compare Channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim: TIM Output Compare handle - * @param sConfig: TIM Output Compare configuration structure - * @param Channel : TIM Channels to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - - /* Check input state */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 1 in Output Compare */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 2 in Output Compare */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 3 in Output Compare */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 4 in Output Compare */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_5: - { - /* Check the parameters */ - assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 5 in Output Compare */ - TIM_OC5_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_6: - { - /* Check the parameters */ - assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 6 in Output Compare */ - TIM_OC6_SetConfig(htim->Instance, sConfig); - } - break; - - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM PWM channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim: TIM PWM handle - * @param sConfig: TIM PWM configuration structure - * @param Channel : TIM Channels to be configured - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef* sConfig, - uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); - - /* Check input state */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Configure the Channel 1 in PWM mode */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode; - } - break; - - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Configure the Channel 2 in PWM mode */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode << 8; - } - break; - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Configure the Channel 3 in PWM mode */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode; - } - break; - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Configure the Channel 4 in PWM mode */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; - } - break; - - case TIM_CHANNEL_5: - { - /* Check the parameters */ - assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); - - /* Configure the Channel 5 in PWM mode */ - TIM_OC5_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel5*/ - htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; - htim->Instance->CCMR3 |= sConfig->OCFastMode; - } - break; - - case TIM_CHANNEL_6: - { - /* Check the parameters */ - assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); - - /* Configure the Channel 5 in PWM mode */ - TIM_OC6_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel6 */ - htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; - htim->Instance->CCMR3 |= sConfig->OCFastMode << 8; - } - break; - - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the OCRef clear feature - * @param htim: TIM handle - * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that - * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @arg TIM_Channel_5: TIM Channel 5 - * @arg TIM_Channel_6: TIM Channel 6 - * @retval None - */ -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, - TIM_ClearInputConfigTypeDef *sClearInputConfig, - uint32_t Channel) -{ - uint32_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); - - /* Check input state */ - __HAL_LOCK(htim); - - switch (sClearInputConfig->ClearInputSource) - { - case TIM_CLEARINPUTSOURCE_NONE: - { - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Clear the OCREF clear selection bit */ - tmpsmcr &= ~TIM_SMCR_OCCS; - - /* Clear the ETR Bits */ - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - - /* Set TIMx_SMCR */ - htim->Instance->SMCR = tmpsmcr; - } - break; - - case TIM_CLEARINPUTSOURCE_OCREFCLR: - { - /* Clear the OCREF clear selection bit */ - htim->Instance->SMCR &= ~TIM_SMCR_OCCS; - } - break; - - case TIM_CLEARINPUTSOURCE_ETR: - { - /* Check the parameters */ - assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); - assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); - assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); - - TIM_ETR_SetConfig(htim->Instance, - sClearInputConfig->ClearInputPrescaler, - sClearInputConfig->ClearInputPolarity, - sClearInputConfig->ClearInputFilter); - - /* Set the OCREF clear selection bit */ - htim->Instance->SMCR |= TIM_SMCR_OCCS; - } - break; - default: - break; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; - } - else - { - /* Disable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; - } - } - break; - case TIM_CHANNEL_2: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; - } - else - { - /* Disable the Ocref clear feature for Channel 2 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; - } - } - break; - case TIM_CHANNEL_3: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; - } - else - { - /* Disable the Ocref clear feature for Channel 3 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; - } - } - break; - case TIM_CHANNEL_4: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; - } - else - { - /* Disable the Ocref clear feature for Channel 4 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; - } - } - break; - case TIM_CHANNEL_5: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE; - } - else - { - /* Disable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE; - } - } - break; - case TIM_CHANNEL_6: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE; - } - else - { - /* Disable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE; - } - } - break; - default: - break; - } - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIM in master mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that - * contains the selected trigger output (TRGO) and the Master/Slave - * mode. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig) -{ - uint32_t tmpcr2; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); - assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); - - /* Check input state */ - __HAL_LOCK(htim); - - /* Get the TIMx CR2 register value */ - tmpcr2 = htim->Instance->CR2; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ - if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); - - /* Clear the MMS2 bits */ - tmpcr2 &= ~TIM_CR2_MMS2; - /* Select the TRGO2 source*/ - tmpcr2 |= sMasterConfig->MasterOutputTrigger2; - } - - /* Reset the MMS Bits */ - tmpcr2 &= ~TIM_CR2_MMS; - /* Select the TRGO source */ - tmpcr2 |= sMasterConfig->MasterOutputTrigger; - - /* Reset the MSM Bit */ - tmpsmcr &= ~TIM_SMCR_MSM; - /* Set master mode */ - tmpsmcr |= sMasterConfig->MasterSlaveMode; - - /* Update TIMx CR2 */ - htim->Instance->CR2 = tmpcr2; - - /* Update TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State - * and the AOE(automatic output enable). - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig) -{ - uint32_t tmpbdtr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); - assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); - assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); - assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); - assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); - assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); - assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); - assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); - assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); - assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); - - /* Check input state */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - - /* Clear the BDTR bits */ - tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI | - TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP | - TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF | - TIM_BDTR_BK2F | TIM_BDTR_BK2E | TIM_BDTR_BK2P); - - /* Set the BDTR bits */ - tmpbdtr |= sBreakDeadTimeConfig->DeadTime; - tmpbdtr |= sBreakDeadTimeConfig->LockLevel; - tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode; - tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode; - tmpbdtr |= sBreakDeadTimeConfig->BreakState; - tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity; - tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput; - tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT); - tmpbdtr |= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT); - tmpbdtr |= sBreakDeadTimeConfig->Break2State; - tmpbdtr |= sBreakDeadTimeConfig->Break2Polarity; - - /* Set TIMx_BDTR */ - htim->Instance->BDTR = tmpbdtr; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -/** - * @brief Configures the break input source. - * @param htim: TIM handle. - * @param BreakInput: Break input to configure - * This parameter can be one of the following values: - * @arg TIM_BREAKINPUT_BRK: Timer break input - * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input - * @param sBreakInputConfig: Break input source configuration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, - uint32_t BreakInput, - TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) - -{ - uint32_t tmporx = 0; - uint32_t bkin_enable_mask = 0; - uint32_t bkin_enable_bitpos = 0; - - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - assert_param(IS_TIM_BREAKINPUT(BreakInput)); - assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); - assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); - - /* Check input state */ - __HAL_LOCK(htim); - - switch(sBreakInputConfig->Source) - { - case TIM_BREAKINPUTSOURCE_BKIN: - { - bkin_enable_mask = TIM1_AF1_BKINE; - bkin_enable_bitpos = 0; - } - break; - - case TIM_BREAKINPUTSOURCE_DFSDM1: - { - bkin_enable_mask = TIM1_AF1_BKDF1BKE; - bkin_enable_bitpos = 8; - } - break; - - default: - break; - } - - switch(BreakInput) - { - case TIM_BREAKINPUT_BRK: - { - /* Get the TIMx_AF1 register value */ - tmporx = htim->Instance->AF1; - - /* Enable the break input */ - tmporx &= ~bkin_enable_mask; - tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - - /* Set TIMx_AF1 */ - htim->Instance->AF1 = tmporx; - } - break; - case TIM_BREAKINPUT_BRK2: - { - /* Get the TIMx_AF2 register value */ - tmporx = htim->Instance->AF2; - - /* Enable the break input */ - tmporx &= ~bkin_enable_mask; - tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - - /* Set TIMx_AF2 */ - htim->Instance->AF2 = tmporx; - } - break; - default: - break; - } - - __HAL_UNLOCK(htim); - - return HAL_OK; -} -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Remap: specifies the TIM input remapping source. - * This parameter can be one of the following values: - * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) - * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output. - * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. - * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. - * @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default) - * @arg TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock. - * @arg TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock. - * @arg TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event. - * @arg TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) - * @arg TIM_TIM11_SPDIF: SPDIF Frame synchronous - * @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock - * (HSE divided by a programmable prescaler) - * @arg TIM_TIM11_MCO1: TIM11 CH1 input is connected to MCO1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) -{ - __HAL_LOCK(htim); - - /* Check parameters */ - assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); - assert_param(IS_TIM_REMAP(Remap)); - - /* Set the Timer remapping configuration */ - htim->Instance->OR = Remap; - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Group channel 5 and channel 1, 2 or 3 - * @param htim: TIM handle. - * @param OCRef: specifies the reference signal(s) the OC5REF is combined with. - * This parameter can be any combination of the following values: - * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC - * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF - * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF - * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef) -{ - /* Check parameters */ - assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_GROUPCH5(OCRef)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Clear GC5Cx bit fields */ - htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1); - - /* Set GC5Cx bit fields */ - htim->Instance->CCR5 |= OCRef; - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions - * @brief Extended Callbacks functions - * -@verbatim - ============================================================================== - ##### Extension Callbacks functions ##### - ============================================================================== - [..] - This section provides Extension TIM callback functions: - (+) Timer Commutation callback - (+) Timer Break callback - -@endverbatim - * @{ - */ - -/** - * @brief Hall commutation changed callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIMEx_CommutationCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Break detection callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIMEx_BreakCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions - * @brief Extended Peripheral State functions - * -@verbatim - ============================================================================== - ##### Extension Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Hall Sensor interface state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @} - */ - -/** - * @brief TIM DMA Commutation callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIMEx_CommutationCallback(htim); -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx to select the TIM peripheral - * @param Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @param ChannelNState: specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. - * @retval None - */ -static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ADVANCED_INSTANCE(TIMx)); - assert_param(IS_TIM_COMPLEMENTARY_CHANNELS(Channel)); - - tmp = TIM_CCER_CC1NE << Channel; - - /* Reset the CCxNE Bit */ - TIMx->CCER &= ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint32_t)(ChannelNState << Channel); -} - -/** - * @brief Timer Output Compare 5 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure - * @retval None - */ -static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the output: Reset the CCxE Bit */ - TIMx->CCER &= ~TIM_CCER_CC5E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR3; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= ~(TIM_CCMR3_OC5M); - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC5P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 16); - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Reset the Output Compare IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS5; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 8); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR3 */ - TIMx->CCMR3 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR5 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Output Compare 6 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure - * @retval None - */ -static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the output: Reset the CCxE Bit */ - TIMx->CCER &= ~TIM_CCER_CC6E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR3; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= ~(TIM_CCMR3_OC6M); - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint32_t)~TIM_CCER_CC6P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 20); - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Reset the Output Compare IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS6; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 10); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR3 */ - TIMx->CCMR3 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR6 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @} - */ - -#endif /* HAL_TIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c deleted file mode 100644 index 42999b5..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c +++ /dev/null @@ -1,2185 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_uart.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief UART HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The UART HAL driver can be used as follows: - - (#) Declare a UART_HandleTypeDef handle structure. - - (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: - (##) Enable the USARTx interface clock. - (##) UART pins configuration: - (+++) Enable the clock for the UART GPIOs. - (+++) Configure these UART pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() - and HAL_UART_Receive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. - (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() - and HAL_UART_Receive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx stream. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required - Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx Stream. - (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the DMA Tx/Rx Stream. - - (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware - flow control and Mode(Receiver/Transmitter) in the Init structure. - - (#) For the UART asynchronous mode, initialize the UART registers by calling - the HAL_UART_Init() API. - - (#) For the UART Half duplex mode, initialize the UART registers by calling - the HAL_HalfDuplex_Init() API. - - (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API. - - (#) For the Multi-Processor mode, initialize the UART registers by calling - the HAL_MultiProcessor_Init() API. - - [..] - (@) The specific UART interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit - and receive process. - - [..] - (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the - low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized - HAL_UART_MspInit() API. - - [..] - Three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_UART_Transmit() - (+) Receive an amount of data in blocking mode using HAL_UART_Receive() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT() - (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT() - (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_RxCpltCallback - (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_UART_ErrorCallback - - *** DMA mode IO operation *** - ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA() - (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback - (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_TxCpltCallback - (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA() - (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback - (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_RxCpltCallback - (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_UART_ErrorCallback - (+) Pause the DMA Transfer using HAL_UART_DMAPause() - (+) Resume the DMA Transfer using HAL_UART_DMAResume() - (+) Stop the DMA Transfer using HAL_UART_DMAStop() - - *** UART HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in UART HAL driver. - - (+) __HAL_UART_ENABLE: Enable the UART peripheral - (+) __HAL_UART_DISABLE: Disable the UART peripheral - (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not - (+) __HAL_UART_CLEAR_IT : Clears the specified UART ISR flag - (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt - (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt - (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not - - [..] - (@) You can refer to the UART HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup UART UART - * @brief HAL UART module driver - * @{ - */ - -#ifdef HAL_UART_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup UART_Private_Constants UART Private Constants - * @{ - */ -#define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup UART_Private_Functions - * @{ - */ -static void UART_EndTxTransfer(UART_HandleTypeDef *huart); -static void UART_EndRxTransfer(UART_HandleTypeDef *huart); -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); -static void UART_DMAError(DMA_HandleTypeDef *hdma); -static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); -static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); -static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup UART_Exported_Functions UART Exported Functions - * @{ - */ - -/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USARTx or the UARTy - in asynchronous mode. - (+) For the asynchronous mode only these parameters can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - please refer to Reference manual for possible UART frame formats. - (++) Hardware flow control - (++) Receiver/transmitter modes - (++) Over Sampling Method - [..] - The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs - follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor - configuration procedures (details for the procedures are available in reference manual (RM0329)). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the UART mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle . - * @param huart: uart handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) - { - /* Check the parameters */ - assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); - } - else - { - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); - } - - if(huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* In asynchronous mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - -/** - * @brief Initializes the half-duplex mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle . - * @param huart: UART handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - if(huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* In half-duplex mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); - - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @brief Initialize the LIN mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle . - * @param huart: UART handle. - * @param BreakDetectLength: specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection - * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); - assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); - assert_param(IS_LIN_WORD_LENGTH(huart->Init.WordLength)); - - if(huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* In LIN mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); - - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); - - /* Set the USART LIN Break detection length. */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @brief Initialize the multiprocessor mode according to the specified - * parameters in the UART_InitTypeDef and initialize the associated handle. - * @param huart: UART handle. - * @param Address: UART node address (4-, 6-, 7- or 8-bit long). - * @param WakeUpMethod: specifies the UART wakeup method. - * This parameter can be one of the following values: - * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection - * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark - * @note If the user resorts to idle line detection wake up, the Address parameter - * is useless and ignored by the initialization function. - * @note If the user resorts to address mark wake up, the address length detection - * is configured by default to 4 bits only. For the UART to be able to - * manage 6-, 7- or 8-bit long addresses detection - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - /* Check the wake up method parameter */ - assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); - - if(huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* In multiprocessor mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) - { - /* If address mark wake up method is chosen, set the USART address node */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); - } - - /* Set the wake up method by setting the WAKE bit in the CR1 register */ - MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @brief Initialize the RS485 Driver enable feature according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart: UART handle. - * @param Polarity: select the driver enable polarity. - * This parameter can be one of the following values: - * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high - * @arg @ref UART_DE_POLARITY_LOW DE signal is active low - * @param AssertionTime: Driver Enable assertion time: - * 5-bit value defining the time between the activation of the DE (Driver Enable) - * signal and the beginning of the start bit. It is expressed in sample time - * units (1/8 or 1/16 bit time, depending on the oversampling rate) - * @param DeassertionTime: Driver Enable deassertion time: - * 5-bit value defining the time between the end of the last stop bit, in a - * transmitted message, and the de-activation of the DE (Driver Enable) signal. - * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the - * oversampling rate). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) -{ - uint32_t temp = 0x0; - - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - /* Check the Driver Enable UART instance */ - assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); - - /* Check the Driver Enable polarity */ - assert_param(IS_UART_DE_POLARITY(Polarity)); - - /* Check the Driver Enable assertion time */ - assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); - - /* Check the Driver Enable deassertion time */ - assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); - - if(huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, CORTEX */ - HAL_UART_MspInit(huart); - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DEM); - - /* Set the Driver Enable polarity */ - MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); - - /* Set the Driver Enable assertion and deassertion times */ - temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); - temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); - MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - -/** - * @brief DeInitializes the UART peripheral - * @param huart: uart handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - huart->Instance->CR1 = 0x0U; - huart->Instance->CR2 = 0x0U; - huart->Instance->CR3 = 0x0U; - - /* DeInit the low level hardware */ - HAL_UART_MspDeInit(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_RESET; - huart->RxState = HAL_UART_STATE_RESET; - - /* Process Unlock */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief UART MSP Init - * @param huart: uart handle - * @retval None - */ -__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_MspInit can be implemented in the user file - */ -} - -/** - * @brief UART MSP DeInit - * @param huart: uart handle - * @retval None - */ -__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_MspDeInit can be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group2 IO operation functions - * @brief UART Transmit/Receive functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of functions allowing to manage the UART asynchronous - and Half duplex data transfers. - - (#) There are two mode of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) Non-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected - - (#) Blocking mode API's are : - (+) HAL_UART_Transmit() - (+) HAL_UART_Receive() - - (#) Non-Blocking mode API's with Interrupt are : - (+) HAL_UART_Transmit_IT() - (+) HAL_UART_Receive_IT() - (+) HAL_UART_IRQHandler() - (+) UART_Transmit_IT() - (+) UART_Receive_IT() - - (#) Non-Blocking mode API's with DMA are : - (+) HAL_UART_Transmit_DMA() - (+) HAL_UART_Receive_DMA() - (+) HAL_UART_DMAPause() - (+) HAL_UART_DMAResume() - (+) HAL_UART_DMAStop() - - (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: - (+) HAL_UART_TxHalfCpltCallback() - (+) HAL_UART_TxCpltCallback() - (+) HAL_UART_RxHalfCpltCallback() - (+) HAL_UART_RxCpltCallback() - (+) HAL_UART_ErrorCallback() - - - -@- In the Half duplex communication, it is forbidden to run the transmit - and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. - -@endverbatim - * @{ - */ - -/** - * @brief Send an amount of data in blocking mode. - * @param huart: UART handle. - * @param pData: Pointer to data buffer. - * @param Size: Amount of data to be sent. - * @param Timeout: Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint16_t* tmp; - uint32_t tickstart = 0U; - - /* Check that a Tx process is not already ongoing */ - if(huart->gState == HAL_UART_STATE_READY) - { - if((pData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Init tickstart for timeout managment*/ - tickstart = HAL_GetTick(); - - huart->TxXferSize = Size; - huart->TxXferCount = Size; - while(huart->TxXferCount > 0U) - { - huart->TxXferCount--; - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - tmp = (uint16_t*) pData; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); - pData += 2; - } - else - { - huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU); - } - } - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* At end of Tx process, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in blocking mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. - * @param Timeout: Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint16_t* tmp; - uint16_t uhMask; - uint32_t tickstart = 0U; - - /* Check that a Rx process is not already ongoing */ - if(huart->RxState == HAL_UART_STATE_READY) - { - if((pData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Init tickstart for timeout managment*/ - tickstart = HAL_GetTick(); - - huart->RxXferSize = Size; - huart->RxXferCount = Size; - - /* Computation of UART mask to apply to RDR register */ - UART_MASK_COMPUTATION(huart); - uhMask = huart->Mask; - - /* as long as data have to be received */ - while(huart->RxXferCount > 0U) - { - huart->RxXferCount--; - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - tmp = (uint16_t*) pData ; - *tmp = (uint16_t)(huart->Instance->RDR & uhMask); - pData +=2U; - } - else - { - *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); - } - } - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in interrupt mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be sent. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Tx process is not already ongoing */ - if(huart->gState == HAL_UART_STATE_READY) - { - if((pData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; - huart->TxXferCount = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the UART Transmit Data Register Empty Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in interrupt mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Rx process is not already ongoing */ - if(huart->RxState == HAL_UART_STATE_READY) - { - if((pData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - huart->RxXferCount = Size; - - /* Computation of UART mask to apply to RDR register */ - UART_MASK_COMPUTATION(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the UART Data Register not empty Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in DMA mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be sent. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - uint32_t *tmp; - - /* Check that a Tx process is not already ongoing */ - if(huart->gState == HAL_UART_STATE_READY) - { - if((pData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; - huart->TxXferCount = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Set the UART DMA transfer complete callback */ - huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmatx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmatx->XferAbortCallback = NULL; - - /* Enable the UART transmit DMA channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->TDR, Size); - - /* Clear the TC flag in the SR register by writing 0 to it */ - __HAL_UART_CLEAR_IT(huart, UART_FLAG_TC); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in DMA mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. - * @note When the UART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - uint32_t *tmp; - - /* Check that a Rx process is not already ongoing */ - if(huart->RxState == HAL_UART_STATE_READY) - { - if((pData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Set the UART DMA transfer complete callback */ - huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmarx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, *(uint32_t*)tmp, Size); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Pause the DMA Transfer. - * @param huart: UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - if ((huart->gState == HAL_UART_STATE_BUSY_TX) && - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) - { - /* Disable the UART DMA Tx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - } - if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) - { - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the UART DMA Rx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Resume the DMA Transfer. - * @param huart: UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - if(huart->gState == HAL_UART_STATE_BUSY_TX) - { - /* Enable the UART DMA Tx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); - } - if(huart->RxState == HAL_UART_STATE_BUSY_RX) - { - /* Clear the Overrun flag before resuming the Rx transfer*/ - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); - - /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the UART DMA Rx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - } - - /* If the UART peripheral is still not enabled, enable it */ - if ((huart->Instance->CR1 & USART_CR1_UE) == 0U) - { - /* Enable UART peripheral */ - __HAL_UART_ENABLE(huart); - } - - return HAL_OK; -} - -/** - * @brief Stop the DMA Transfer. - * @param huart: UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) -{ - /* The Lock is not implemented on this API to allow the user application - to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / - HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete - interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of - the stream and the corresponding call back is executed. */ - - /* Stop UART DMA Tx request if ongoing */ - if ((huart->gState == HAL_UART_STATE_BUSY_TX) && - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel */ - if(huart->hdmatx != NULL) - { - HAL_DMA_Abort(huart->hdmatx); - } - - UART_EndTxTransfer(huart); - } - - /* Stop UART DMA Rx request if ongoing */ - if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel */ - if(huart->hdmarx != NULL) - { - HAL_DMA_Abort(huart->hdmarx); - } - - UART_EndRxTransfer(huart); - } - - return HAL_OK; -} - -/** - * @brief This function handles UART interrupt request. - * @param huart: uart handle - * @retval None - */ -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) -{ - uint32_t isrflags = READ_REG(huart->Instance->ISR); - uint32_t cr1its = READ_REG(huart->Instance->CR1); - uint32_t cr3its = READ_REG(huart->Instance->CR3); - uint32_t errorflags; - - /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); - if (errorflags == RESET) - { - /* UART in mode Receiver ---------------------------------------------------*/ - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) - { - UART_Receive_IT(huart); - return; - } - } - - /* If some errors occur */ - if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET)) - { - - /* UART parity error interrupt occurred -------------------------------------*/ - if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) - { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF); - - huart->ErrorCode |= HAL_UART_ERROR_PE; - } - - /* UART frame error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) - { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF); - - huart->ErrorCode |= HAL_UART_ERROR_FE; - } - - /* UART noise error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) - { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF); - - huart->ErrorCode |= HAL_UART_ERROR_NE; - } - - /* UART Over-Run interrupt occurred -----------------------------------------*/ - if(((isrflags & USART_ISR_ORE) != RESET) && - (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) - { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); - - huart->ErrorCode |= HAL_UART_ERROR_ORE; - } - - /* Call UART Error Call back function if need be --------------------------*/ - if(huart->ErrorCode != HAL_UART_ERROR_NONE) - { - /* UART in mode Receiver ---------------------------------------------------*/ - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) - { - UART_Receive_IT(huart); - } - - /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ - if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) - { - /* Blocking error : transfer is aborted - Set the UART state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ - UART_EndRxTransfer(huart); - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel */ - if(huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; - - /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ - huart->hdmarx->XferAbortCallback(huart->hdmarx); - } - } - else - { - /* Call user error callback */ - HAL_UART_ErrorCallback(huart); - } - } - else - { - /* Call user error callback */ - HAL_UART_ErrorCallback(huart); - } - } - else - { - /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ - HAL_UART_ErrorCallback(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; - } - } - return; - - } /* End if some error occurs */ - - /* UART in mode Transmitter ------------------------------------------------*/ - if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) - { - UART_Transmit_IT(huart); - return; - } - - /* UART in mode Transmitter (transmission end) -----------------------------*/ - if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) - { - UART_EndTransmit_IT(huart); - return; - } - -} - -/** - * @brief This function handles UART Communication Timeout. - * @param huart UART handle - * @param Flag specifies the UART flag to check. - * @param Status The new Flag status (SET or RESET). - * @param Tickstart Tick start value - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) -{ - /* Wait until flag is set */ - while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U)||((HAL_GetTick()-Tickstart) >= Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief DMA UART transmit process complete callback - * @param hdma: DMA handle - * @retval None - */ -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* DMA Normal mode*/ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) - { - huart->TxXferCount = 0U; - - /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - } - /* DMA Circular mode */ - else - { - HAL_UART_TxCpltCallback(huart); - } -} - -/** - * @brief DMA UART transmit process half complete callback - * @param hdma : DMA handle - * @retval None - */ -static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - HAL_UART_TxHalfCpltCallback(huart); -} - -/** - * @brief DMA UART receive process complete callback - * @param hdma: DMA handle - * @retval None - */ -static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* DMA Normal mode */ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) - { - huart->RxXferCount = 0U; - - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - } - HAL_UART_RxCpltCallback(huart); -} - -/** - * @brief DMA UART receive process half complete callback - * @param hdma : DMA handle - * @retval None - */ -static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - HAL_UART_RxHalfCpltCallback(huart); -} - -/** - * @brief DMA UART communication error callback - * @param hdma: DMA handle - * @retval None - */ -static void UART_DMAError(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - huart->RxXferCount = 0U; - huart->TxXferCount = 0U; - /* Stop UART DMA Tx request if ongoing */ - if ( (huart->gState == HAL_UART_STATE_BUSY_TX) - &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) ) - { - UART_EndTxTransfer(huart); - } - - /* Stop UART DMA Rx request if ongoing */ - if ( (huart->RxState == HAL_UART_STATE_BUSY_RX) - &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ) - { - UART_EndRxTransfer(huart); - } - SET_BIT(huart->ErrorCode, HAL_UART_ERROR_DMA); - HAL_UART_ErrorCallback(huart); -} - -/** - * @brief DMA UART communication abort callback, when call by HAL services on Error - * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma: DMA handle. - * @retval None - */ -static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - huart->RxXferCount = 0U; - huart->TxXferCount = 0U; - - HAL_UART_ErrorCallback(huart); -} - -/** - * @brief Tx Transfer completed callbacks - * @param huart: uart handle - * @retval None - */ - __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_TxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Tx Half Transfer completed callbacks. - * @param huart: UART handle - * @retval None - */ - __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_TxHalfCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callbacks - * @param huart: uart handle - * @retval None - */ -__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_RxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Rx Half Transfer completed callbacks. - * @param huart: UART handle - * @retval None - */ -__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_RxHalfCpltCallback can be implemented in the user file - */ -} - -/** - * @brief UART error callbacks - * @param huart: uart handle - * @retval None - */ - __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_ErrorCallback can be implemented in the user file - */ -} - -/** - * @brief Send an amount of data in interrupt mode - * Function called under interruption only, once - * interruptions have been enabled by HAL_UART_Transmit_IT() - * @param huart: UART handle - * @retval HAL status - */ -static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) -{ - uint16_t* tmp; - - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - - if(huart->TxXferCount == 0U) - { - /* Disable the UART Transmit Data Register Empty Interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); - - /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - - return HAL_OK; - } - else - { - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - tmp = (uint16_t*) huart->pTxBuffPtr; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); - huart->pTxBuffPtr += 2U; - } - else - { - huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU); - } - - huart->TxXferCount--; - - return HAL_OK; - } - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Wrap up transmission in non-blocking mode. - * @param huart: pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) -{ - /* Disable the UART Transmit Complete Interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); - - /* Tx process is ended, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - HAL_UART_TxCpltCallback(huart); - - return HAL_OK; -} - -/** - * @brief Receive an amount of data in interrupt mode - * Function called under interruption only, once - * interruptions have been enabled by HAL_UART_Receive_IT() - * @param huart: UART handle - * @retval HAL status - */ -static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) -{ - uint16_t* tmp; - uint16_t uhMask = huart->Mask; - - /* Check that a Rx process is ongoing */ - if(huart->RxState == HAL_UART_STATE_BUSY_RX) - { - - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - tmp = (uint16_t*) huart->pRxBuffPtr ; - *tmp = (uint16_t)(huart->Instance->RDR & uhMask); - huart->pRxBuffPtr +=2; - } - else - { - *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); - } - - if(--huart->RxXferCount == 0) - { - /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - HAL_UART_RxCpltCallback(huart); - - return HAL_OK; - } - - return HAL_OK; - } - else - { - /* Clear RXNE interrupt flag */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - return HAL_BUSY; - } -} - -/** - * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). - * @param huart: UART handle. - * @retval None - */ -static void UART_EndTxTransfer(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - - /* At end of Tx process, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; -} - - -/** - * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). - * @param huart: UART handle. - * @retval None - */ -static void UART_EndRxTransfer(UART_HandleTypeDef *huart) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; -} - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions - * @brief UART control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the UART. - (+) HAL_UART_GetState() API is helpful to check in run-time the state of the UART peripheral. - (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode - (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode - (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode - (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode - (+) UART_SetConfig() API configures the UART peripheral - (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features - (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization - (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter - (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver - (+) HAL_LIN_SendBreak() API transmits the break characters - (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address - detection length to more than 4 bits for multiprocessor address mark wake up. -@endverbatim - * @{ - */ - -/** - * @brief Enable UART in mute mode (doesn't mean UART enters mute mode; - * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called) - * @param huart: UART handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Enable USART mute mode by setting the MME bit in the CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_MME); - - huart->gState = HAL_UART_STATE_READY; - - return (UART_CheckIdleState(huart)); -} - -/** - * @brief Disable UART mute mode (doesn't mean it actually wakes up the software, - * as it may not have been in mute mode at this very moment). - * @param huart: uart handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable USART mute mode by clearing the MME bit in the CR1 register */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); - - huart->gState = HAL_UART_STATE_READY; - - return (UART_CheckIdleState(huart)); -} - -/** - * @brief Enter UART mute mode (means UART actually enters mute mode). - * To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. - * @param huart: uart handle - * @retval HAL status - */ -void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) -{ - __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); -} - - - -/** - * @brief return the UART state - * @param huart: uart handle - * @retval HAL state - */ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) -{ - uint32_t temp1= 0x00U, temp2 = 0x00U; - temp1 = huart->gState; - temp2 = huart->RxState; - - return (HAL_UART_StateTypeDef)(temp1 | temp2); -} - -/** -* @brief Return the UART error code -* @param huart : pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. -* @retval UART Error Code -*/ -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) -{ - return huart->ErrorCode; -} - -/** - * @brief Configure the UART peripheral - * @param huart: uart handle - * @retval None - */ -HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) -{ - uint32_t tmpreg = 0x00000000U; - UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED; - uint16_t brrtemp = 0x0000U; - uint16_t usartdiv = 0x0000U; - HAL_StatusTypeDef ret = HAL_OK; - - /* Check the parameters */ - assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); - assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); - assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); - assert_param(IS_UART_PARITY(huart->Init.Parity)); - assert_param(IS_UART_MODE(huart->Init.Mode)); - assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); - assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); - - - /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure - * the UART Word Length, Parity, Mode and oversampling: - * set the M bits according to huart->Init.WordLength value - * set PCE and PS bits according to huart->Init.Parity value - * set TE and RE bits according to huart->Init.Mode value - * set OVER8 bit according to huart->Init.OverSampling value */ - tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg); - - /*-------------------------- USART CR2 Configuration -----------------------*/ - /* Configure the UART Stop Bits: Set STOP[13:12] bits according - * to huart->Init.StopBits value */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - - /*-------------------------- USART CR3 Configuration -----------------------*/ - /* Configure - * - UART HardWare Flow Control: set CTSE and RTSE bits according - * to huart->Init.HwFlowCtl value - * - one-bit sampling method versus three samples' majority rule according - * to huart->Init.OneBitSampling */ - tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ; - MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg); - - /*-------------------------- USART BRR Configuration -----------------------*/ - UART_GETCLOCKSOURCE(huart, clocksource); - - /* Check UART Over Sampling to set Baud Rate Register */ - if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - { - switch (clocksource) - { - case UART_CLOCKSOURCE_PCLK1: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); - break; - case UART_CLOCKSOURCE_PCLK2: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); - break; - case UART_CLOCKSOURCE_HSI: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); - break; - case UART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); - break; - case UART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); - break; - case UART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; - } - - brrtemp = usartdiv & 0xFFF0U; - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - huart->Instance->BRR = brrtemp; - } - else - { - switch (clocksource) - { - case UART_CLOCKSOURCE_PCLK1: - huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); - break; - case UART_CLOCKSOURCE_PCLK2: - huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); - break; - case UART_CLOCKSOURCE_HSI: - huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); - break; - case UART_CLOCKSOURCE_SYSCLK: - huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); - break; - case UART_CLOCKSOURCE_LSE: - huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); - break; - case UART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; - } - } - - return ret; - -} - - -/** - * @brief Configure the UART peripheral advanced features - * @param huart: uart handle - * @retval None - */ -void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) -{ - /* Check whether the set of advanced features to configure is properly set */ - assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); - - /* if required, configure TX pin active level inversion */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) - { - assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); - } - - /* if required, configure RX pin active level inversion */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) - { - assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); - } - - /* if required, configure data inversion */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) - { - assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); - } - - /* if required, configure RX/TX pins swap */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - { - assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - } - - /* if required, configure RX overrun detection disabling */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) - { - assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); - MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); - } - - /* if required, configure DMA disabling on reception error */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) - { - assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); - MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); - } - - /* if required, configure auto Baud rate detection scheme */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) - { - assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); - /* set auto Baudrate detection parameters if detection is enabled */ - if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) - { - assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); - } - } - - /* if required, configure MSB first on communication line */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) - { - assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); - } -} - - - -/** - * @brief Check the UART Idle State - * @param huart: uart handle - * @retval HAL status - */ -HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) -{ - uint32_t tickstart = 0U; - - /* Initialize the UART ErrorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Init tickstart for timeout managment*/ - tickstart = HAL_GetTick(); - - /* Check if the Transmitter is enabled */ - if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - { - /* Wait until TEACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - /* Timeout Occurred */ - return HAL_TIMEOUT; - } - } - /* Check if the Receiver is enabled */ - if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - /* Wait until REACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - /* Timeout Occurred */ - return HAL_TIMEOUT; - } - } - - /* Initialize the UART State */ - huart->gState= HAL_UART_STATE_READY; - huart->RxState= HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Enables the UART transmitter and disables the UART receiver. - * @param huart: UART handle - * @retval HAL status - * @retval None - */ -HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - huart->gState = HAL_UART_STATE_BUSY; - - /* Clear TE and RE bits */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); - /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_TE); - - huart->gState= HAL_UART_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Enables the UART receiver and disables the UART transmitter. - * @param huart: UART handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - huart->gState = HAL_UART_STATE_BUSY; - - /* Clear TE and RE bits */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); - /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_RE); - - huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - - -/** - * @brief Transmits break characters. - * @param huart: UART handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) -{ - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Send break characters */ - SET_BIT(huart->Instance->RQR, UART_SENDBREAK_REQUEST); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief By default in multiprocessor mode, when the wake up method is set - * to address mark, the UART handles only 4-bit long addresses detection; - * this API allows to enable longer addresses detection (6-, 7- or 8-bit - * long). - * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, - * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. - * @param huart: UART handle. - * @param AddressLength: this parameter can be one of the following values: - * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address - * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - /* Check the address length parameter */ - assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the address length */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState to Ready */ - return (UART_CheckIdleState(huart)); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_UART_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_usart.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_usart.c deleted file mode 100644 index db7d0e5..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_usart.c +++ /dev/null @@ -1,1997 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_usart.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief USART HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter - * Peripheral (USART). - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The USART HAL driver can be used as follows: - - (#) Declare a USART_HandleTypeDef handle structure. - (#) Initialize the USART low level resources by implement the HAL_USART_MspInit ()API: - (##) Enable the USARTx interface clock. - (##) USART pins configuration: - (+++) Enable the clock for the USART GPIOs. - (+++) Configure these USART pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(), - HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. - (+++) The specific USART interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process. - (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA() - HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx stream. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx Stream. - (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream. - - (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware - flow control and Mode(Receiver/Transmitter) in the husart Init structure. - - (#) Initialize the USART registers by calling the HAL_USART_Init() API: - (++) These API's configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_USART_MspInit(&husart) API. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup USART USART - * @brief HAL USART Synchronous module driver - * @{ - */ - -#ifdef HAL_USART_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup USART_Private_Constants - * @{ - */ -#define DUMMY_DATA ((uint16_t) 0xFFFFU) -#define TEACK_REACK_TIMEOUT ((uint32_t) 1000U) -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) -#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \ - USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup USART_Private_Functions - * @{ - */ -static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); -static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void USART_DMAError(DMA_HandleTypeDef *hdma); -static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma); -static void USART_EndTxTransfer(USART_HandleTypeDef *husart); -static void USART_EndRxTransfer(USART_HandleTypeDef *husart); -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); -static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart); -static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart); -static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart); -static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart); -static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart); -static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart); - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup USART_Exported_Functions USART Exported Functions - * @{ - */ - -/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - (++) USART polarity - (++) USART phase - (++) USART LastBit - (++) Receiver/transmitter modes - - [..] - The HAL_USART_Init() function follows the USART synchronous configuration - procedure (details for the procedure are available in reference manual). - -@endverbatim - - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible USART frame formats are as listed in the - following table: - - +---------------------------------------------------------------+ - | M1M0 bits | PCE bit | USART frame | - |-----------------------|---------------------------------------| - | 10 | 0 | | SB | 7-bit data | STB | | - |-----------|-----------|---------------------------------------| - | 10 | 1 | | SB | 6-bit data | PB | STB | | - +---------------------------------------------------------------+ - - * @{ - */ - -/** - * @brief Initializes the USART mode according to the specified - * parameters in the USART_InitTypeDef and create the associated handle. - * @param husart: USART handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) -{ - /* Check the USART handle allocation */ - if(husart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_USART_INSTANCE(husart->Instance)); - - if(husart->State == HAL_USART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - husart->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK */ - HAL_USART_MspInit(husart); - } - - husart->State = HAL_USART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_USART_DISABLE(husart); - - /* Set the Usart Communication parameters */ - if (USART_SetConfig(husart) == HAL_ERROR) - { - return HAL_ERROR; - } - - /* In Synchronous mode, the following bits must be kept cleared: - - LINEN bit in the USART_CR2 register - - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - /* Enable the Peripheral */ - __HAL_USART_ENABLE(husart); - - /* TEACK and/or REACK to check before moving husart->State to Ready */ - return (USART_CheckIdleState(husart)); -} - -/** - * @brief DeInitializes the USART peripheral - * @param husart: USART handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) -{ - /* Check the USART handle allocation */ - if(husart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_USART_INSTANCE(husart->Instance)); - - husart->State = HAL_USART_STATE_BUSY; - - husart->Instance->CR1 = 0x0U; - husart->Instance->CR2 = 0x0U; - husart->Instance->CR3 = 0x0U; - - /* DeInit the low level hardware */ - HAL_USART_MspDeInit(husart); - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_RESET; - - /* Process Unlock */ - __HAL_UNLOCK(husart); - - return HAL_OK; -} - -/** - * @brief USART MSP Init - * @param husart: USART handle - * @retval None - */ - __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(husart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_USART_MspInit can be implemented in the user file - */ -} - -/** - * @brief USART MSP DeInit - * @param husart: USART handle - * @retval None - */ - __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(husart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_USART_MspDeInit can be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup USART_Exported_Functions_Group2 IO operation functions - * @brief USART Transmit and Receive functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of functions allowing to manage the USART synchronous - data transfers. - - [..] The USART supports master mode only: it cannot receive or send data related to an input - clock (SCLK is always an output). - - (#) There are two mode of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated USART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected - - (#) Blocking mode API's are : - (++) HAL_USART_Transmit()in simplex mode - (++) HAL_USART_Receive() in full duplex receive only - (++) HAL_USART_TransmitReceive() in full duplex mode - - (#) Non-Blocking mode API's with Interrupt are : - (++) HAL_USART_Transmit_IT()in simplex mode - (++) HAL_USART_Receive_IT() in full duplex receive only - (++) HAL_USART_TransmitReceive_IT()in full duplex mode - (++) HAL_USART_IRQHandler() - - (#) No-Blocking mode functions with DMA are : - (++) HAL_USART_Transmit_DMA()in simplex mode - (++) HAL_USART_Receive_DMA() in full duplex receive only - (++) HAL_USART_TransmitReceive_DMA() in full duplex mode - (++) HAL_USART_DMAPause() - (++) HAL_USART_DMAResume() - (++) HAL_USART_DMAStop() - - (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: - (++) HAL_USART_TxCpltCallback() - (++) HAL_USART_RxCpltCallback() - (++) HAL_USART_TxHalfCpltCallback() - (++) HAL_USART_RxHalfCpltCallback() - (++) HAL_USART_ErrorCallback() - (++) HAL_USART_TxRxCpltCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Simplex Send an amount of data in blocking mode - * @param husart: USART handle - * @param pTxData: pointer to data buffer - * @param Size: amount of data to be sent - * @param Timeout : Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout) -{ - uint16_t* tmp; - uint32_t tickstart = 0U; - - if(husart->State == HAL_USART_STATE_READY) - { - if((pTxData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(husart); - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_TX; - - /* Init tickstart for timeout managment*/ - tickstart = HAL_GetTick(); - - husart->TxXferSize = Size; - husart->TxXferCount = Size; - - /* Check the remaining data to be sent */ - while(husart->TxXferCount > 0U) - { - husart->TxXferCount--; - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) - { - tmp = (uint16_t*) pTxData; - husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); - pTxData += 2; - } - else - { - husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFFU); - } - } - - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - husart->State = HAL_USART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in blocking mode - * @note To receive synchronous data, dummy data are simultaneously transmitted - * @param husart: USART handle - * @param pRxData: pointer to data buffer - * @param Size: amount of data to be received - * @param Timeout : Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) -{ - uint16_t* tmp; - uint16_t uhMask; - uint32_t tickstart = 0U; - - if(husart->State == HAL_USART_STATE_READY) - { - if((pRxData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(husart); - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_RX; - - /* Init tickstart for timeout managment*/ - tickstart = HAL_GetTick(); - - husart->RxXferSize = Size; - husart->RxXferCount = Size; - - /* Computation of USART mask to apply to RDR register */ - __HAL_USART_MASK_COMPUTATION(husart); - uhMask = husart->Mask; - - /* as long as data have to be received */ - while(husart->RxXferCount > 0U) - { - husart->RxXferCount--; - - /* Wait until TC flag is set to send dummy byte in order to generate the - * clock for the slave to send data. - * Whatever the frame length (7, 8 or 9-bit long), the same dummy value - * can be written for all the cases. */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x0FFU); - - /* Wait for RXNE Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) - { - tmp = (uint16_t*) pRxData ; - *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - pRxData +=2; - } - else - { - *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); - } - } - - husart->State = HAL_USART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Full-Duplex Send and Receive an amount of data in blocking mode - * @param husart: USART handle - * @param pTxData: pointer to TX data buffer - * @param pRxData: pointer to RX data buffer - * @param Size: amount of data to be sent (same amount to be received) - * @param Timeout : Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) -{ - uint16_t* tmp; - uint16_t uhMask; - uint32_t tickstart = 0U; - - if(husart->State == HAL_USART_STATE_READY) - { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(husart); - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_RX; - - /* Init tickstart for timeout managment*/ - tickstart = HAL_GetTick(); - - husart->RxXferSize = Size; - husart->TxXferSize = Size; - husart->TxXferCount = Size; - husart->RxXferCount = Size; - - /* Computation of USART mask to apply to RDR register */ - __HAL_USART_MASK_COMPUTATION(husart); - uhMask = husart->Mask; - - /* Check the remain data to be sent */ - while(husart->TxXferCount > 0) - { - husart->TxXferCount--; - husart->RxXferCount--; - - /* Wait until TC flag is set to send data */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) - { - tmp = (uint16_t*) pTxData; - husart->Instance->TDR = (*tmp & uhMask); - pTxData += 2; - } - else - { - husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask); - } - - /* Wait for RXNE Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) - { - tmp = (uint16_t*) pRxData ; - *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - pRxData +=2U; - } - else - { - *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); - } - } - - husart->State = HAL_USART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in interrupt mode - * @param husart: USART handle - * @param pTxData: pointer to data buffer - * @param Size: amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) -{ - if(husart->State == HAL_USART_STATE_READY) - { - if((pTxData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(husart); - - husart->pTxBuffPtr = pTxData; - husart->TxXferSize = Size; - husart->TxXferCount = Size; - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_TX; - - /* The USART Error Interrupts: (Frame error, noise error, overrun error) - are not managed by the USART Transmit Process to avoid the overrun interrupt - when the usart mode is configured for transmit and receive "USART_MODE_TX_RX" - to benefit for the frame error and noise interrupts the usart mode should be - configured only for transmit "USART_MODE_TX" */ - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - /* Enable the USART Transmit Data Register Empty Interrupt */ - SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in blocking mode - * To receive synchronous data, dummy data are simultaneously transmitted - * @param husart: USART handle - * @param pRxData: pointer to data buffer - * @param Size: amount of data to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) -{ - if(husart->State == HAL_USART_STATE_READY) - { - if((pRxData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(husart); - - husart->pRxBuffPtr = pRxData; - husart->RxXferSize = Size; - husart->RxXferCount = Size; - - __HAL_USART_MASK_COMPUTATION(husart); - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_RX; - - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); - - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - - /* Enable the USART Data Register not empty Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE); - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - - /* Send dummy byte in order to generate the clock for the Slave to send the next data */ - if(husart->Init.WordLength == USART_WORDLENGTH_9B) - { - husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x01FFU); - } - else - { - husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FFU); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Full-Duplex Send and Receive an amount of data in interrupt mode - * @param husart: USART handle - * @param pTxData: pointer to TX data buffer - * @param pRxData: pointer to RX data buffer - * @param Size: amount of data to be sent (same amount to be received) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) -{ - - if(husart->State == HAL_USART_STATE_READY) - { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(husart); - - husart->pRxBuffPtr = pRxData; - husart->RxXferSize = Size; - husart->RxXferCount = Size; - husart->pTxBuffPtr = pTxData; - husart->TxXferSize = Size; - husart->TxXferCount = Size; - - /* Computation of USART mask to apply to RDR register */ - __HAL_USART_MASK_COMPUTATION(husart); - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_TX_RX; - - /* Enable the USART Data Register not empty Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE); - - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); - - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - /* Enable the USART Transmit Data Register Empty Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in DMA mode - * @param husart: USART handle - * @param pTxData: pointer to data buffer - * @param Size: amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) -{ - uint32_t *tmp; - - if(husart->State == HAL_USART_STATE_READY) - { - if((pTxData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(husart); - - husart->pTxBuffPtr = pTxData; - husart->TxXferSize = Size; - husart->TxXferCount = Size; - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_TX; - - /* Set the USART DMA transfer complete callback */ - husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; - - /* Set the USART DMA Half transfer complete callback */ - husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; - - /* Set the DMA error callback */ - husart->hdmatx->XferErrorCallback = USART_DMAError; - - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - SET_BIT(husart->Instance->ISR, (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE | USART_ISR_ORE)); - - /* Enable the USART transmit DMA channel */ - tmp = (uint32_t*)&pTxData; - HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); - - /* Clear the TC flag in the SR register by writing 0 to it */ - __HAL_USART_CLEAR_IT(husart, USART_FLAG_TC); - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in DMA mode - * @param husart: USART handle - * @param pRxData: pointer to data buffer - * @param Size: amount of data to be received - * @note When the USART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position) - * @retval HAL status - * @note The USART DMA transmit stream must be configured in order to generate the clock for the slave. - */ -HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) -{ - uint32_t *tmp; - - if(husart->State == HAL_USART_STATE_READY) - { - if((pRxData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(husart); - - husart->pRxBuffPtr = pRxData; - husart->RxXferSize = Size; - husart->pTxBuffPtr = pRxData; - husart->TxXferSize = Size; - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_RX; - - /* Set the USART DMA Rx transfer complete callback */ - husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; - - /* Set the USART DMA Half transfer complete callback */ - husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; - - /* Set the USART DMA Rx transfer error callback */ - husart->hdmarx->XferErrorCallback = USART_DMAError; - - /* Set the DMA abort callback */ - husart->hdmatx->XferAbortCallback = NULL; - - /* Set the USART Tx DMA transfer complete callback as NULL because the communication closing - is performed in DMA reception complete callback */ - husart->hdmatx->XferHalfCpltCallback = NULL; - husart->hdmatx->XferCpltCallback = NULL; - - /* Set the DMA error callback */ - husart->hdmatx->XferErrorCallback = USART_DMAError; - - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - SET_BIT(husart->Instance->ISR, (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE | USART_ISR_ORE)); - - /* Enable the USART receive DMA channel */ - tmp = (uint32_t*)&pRxData; - HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size); - - /* Enable the USART transmit DMA channel: the transmit stream is used in order - to generate in the non-blocking mode the clock to the slave device, - this mode isn't a simplex receive mode but a full-duplex receive mode */ - HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); - - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Full-Duplex Transmit Receive an amount of data in non blocking mode - * @param husart: USART handle - * @param pTxData: pointer to TX data buffer - * @param pRxData: pointer to RX data buffer - * @param Size: amount of data to be received/sent - * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) -{ - uint32_t *tmp; - - if(husart->State == HAL_USART_STATE_READY) - { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(husart); - - husart->pRxBuffPtr = pRxData; - husart->RxXferSize = Size; - husart->pTxBuffPtr = pTxData; - husart->TxXferSize = Size; - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_TX_RX; - - /* Set the USART DMA Rx transfer complete callback */ - husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; - - /* Set the USART DMA Half transfer complete callback */ - husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; - - /* Set the USART DMA Tx transfer complete callback */ - husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; - - /* Set the USART DMA Half transfer complete callback */ - husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; - - /* Set the USART DMA Tx transfer error callback */ - husart->hdmatx->XferErrorCallback = USART_DMAError; - - /* Set the USART DMA Rx transfer error callback */ - husart->hdmarx->XferErrorCallback = USART_DMAError; - - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - SET_BIT(husart->Instance->ISR, (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE | USART_ISR_ORE)); - - /* Enable the USART receive DMA channel */ - tmp = (uint32_t*)&pRxData; - HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size); - - /* Enable the USART transmit DMA channel */ - tmp = (uint32_t*)&pTxData; - HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); - - /* Clear the TC flag in the SR register by writing 0 to it */ - __HAL_USART_CLEAR_IT(husart, USART_FLAG_TC); - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); - - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Pauses the DMA Transfer. - * @param husart: USART handle - * @retval None - */ -HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) -{ - /* Process Locked */ - __HAL_LOCK(husart); - - if(husart->State == HAL_USART_STATE_BUSY_TX) - { - /* Disable the USART DMA Tx request */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - } - else if(husart->State == HAL_USART_STATE_BUSY_RX) - { - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* Disable the USART DMA Rx request */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); - } - else if(husart->State == HAL_USART_STATE_BUSY_TX_RX) - { - /* Disable the USART DMA Tx request */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); - /* Disable the USART DMA Rx request */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - } - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_OK; -} - -/** - * @brief Resumes the DMA Transfer. - * @param husart: USART handle - * @retval None - */ -HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) -{ - /* Process Locked */ - __HAL_LOCK(husart); - - if(husart->State == HAL_USART_STATE_BUSY_TX) - { - /* Enable the USART DMA Tx request */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - } - else if(husart->State == HAL_USART_STATE_BUSY_RX) - { - /* Clear the Overrun flag before resuming the Rx transfer*/ - __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); - - /* Reenable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - - /* Enable the USART DMA Rx request */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); - } - else if(husart->State == HAL_USART_STATE_BUSY_TX_RX) - { - /* Clear the Overrun flag before resuming the Rx transfer*/ - __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); - - /* Enable the USART DMA Rx request before the DMA Tx request */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); - - /* Enable the USART DMA Tx request */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - } - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_OK; -} - -/** - * @brief Stops the DMA Transfer. - * @param husart: USART handle - * @retval None - */ -HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) -{ - /* The Lock is not implemented on this API to allow the user application - to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() / - HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback: - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete - interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of - the stream and the corresponding call back is executed. */ - - /* Stop USART DMA Tx request if ongoing */ - if ((husart->State == HAL_USART_STATE_BUSY_TX) && - (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))) - { - USART_EndTxTransfer(husart); - - /* Abort the USART DMA Tx channel */ - if(husart->hdmatx != NULL) - { - HAL_DMA_Abort(husart->hdmatx); - } - - /* Disable the USART Tx DMA request */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - } - - /* Stop USART DMA Rx request if ongoing */ - if ((husart->State == HAL_USART_STATE_BUSY_RX) && - (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))) - { - USART_EndRxTransfer(husart); - - /* Abort the USART DMA Rx channel */ - if(husart->hdmarx != NULL) - { - HAL_DMA_Abort(husart->hdmarx); - } - - /* Disable the USART Rx DMA request */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); - } - - return HAL_OK; -} - -/** - * @brief This function handles USART interrupt request. - * @param husart: USART handle - * @retval None - */ -void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) -{ - uint32_t isrflags = READ_REG(husart->Instance->ISR); - uint32_t cr1its = READ_REG(husart->Instance->CR1); - uint32_t cr3its = READ_REG(husart->Instance->CR3); - uint32_t errorflags; - - /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); - if (errorflags == RESET) - { - /* USART in mode Receiver --------------------------------------------------*/ - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) - { - if(husart->State == HAL_USART_STATE_BUSY_RX) - { - USART_Receive_IT(husart); - } - else - { - USART_TransmitReceive_IT(husart); - } - } - } - - /* If some errors occur */ - if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET)) - { - - /* USART parity error interrupt occurred ------------------------------------*/ - if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) - { - __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF); - husart->ErrorCode |= HAL_USART_ERROR_PE; - } - - /* USART frame error interrupt occurred -------------------------------------*/ - if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) - { - __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF); - husart->ErrorCode |= HAL_USART_ERROR_FE; - } - - /* USART noise error interrupt occurred -------------------------------------*/ - if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) - { - __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF); - husart->ErrorCode |= HAL_USART_ERROR_NE; - } - - /* USART Over-Run interrupt occurred ----------------------------------------*/ - if(((isrflags & USART_ISR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) - { - __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); - husart->ErrorCode |= HAL_USART_ERROR_ORE; - } - - /* Call USART Error Call back function if need be --------------------------*/ - if(husart->ErrorCode != HAL_USART_ERROR_NONE) - { - /* USART in mode Receiver ---------------------------------------------------*/ - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) - { - USART_Receive_IT(husart); - } - - /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ - if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) || - (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))) - { - /* Blocking error : transfer is aborted - Set the USART state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ - USART_EndRxTransfer(husart); - - /* Disable the USART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the USART DMA Rx channel */ - if(husart->hdmarx != NULL) - { - /* Set the USART DMA Abort callback : - will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */ - husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError; - - /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) - { - /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */ - husart->hdmarx->XferAbortCallback(husart->hdmarx); - } - } - else - { - /* Call user error callback */ - HAL_USART_ErrorCallback(husart); - } - } - else - { - /* Call user error callback */ - HAL_USART_ErrorCallback(husart); - } - } - else - { - /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ - HAL_USART_ErrorCallback(husart); - husart->ErrorCode = HAL_USART_ERROR_NONE; - } - } - return; - - } /* End if some error occurs */ - - /* USART in mode Transmitter -----------------------------------------------*/ - if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) - { - if(husart->State == HAL_USART_STATE_BUSY_TX) - { - USART_Transmit_IT(husart); - } - else - { - USART_TransmitReceive_IT(husart); - } - return; - } - - /* USART in mode Transmitter (transmission end) -----------------------------*/ - if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) - { - USART_EndTransmit_IT(husart); - return; - } -} - -/** - * @brief Tx Transfer completed callbacks - * @param husart: USART handle - * @retval None - */ -__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(husart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_USART_TxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Tx Half Transfer completed callbacks. - * @param husart: USART handle - * @retval None - */ - __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(husart); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_USART_TxHalfCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callbacks. - * @param husart: USART handle - * @retval None - */ -__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(husart); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_USART_RxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Rx Half Transfer completed callbacks - * @param husart: usart handle - * @retval None - */ -__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(husart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_USART_RxHalfCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Tx/Rx Transfers completed callback for the non-blocking process - * @param husart: USART handle - * @retval None - */ -__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(husart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_USART_TxRxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief USART error callbacks - * @param husart: USART handle - * @retval None - */ -__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(husart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_USART_ErrorCallback can be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief USART State and Errors functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Errors functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to return the State of - USART communication - process, return Peripheral Errors occurred during communication process - (+) HAL_USART_GetState() API can be helpful to check in run-time the state - of the USART peripheral. - (+) HAL_USART_GetError() check in run-time errors that could be occurred during - communication. -@endverbatim - * @{ - */ - -/** - * @brief return the USART state - * @param husart: USART handle - * @retval HAL state - */ -HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) -{ - return husart->State; -} - -/** - * @brief Return the USART error code - * @param husart : pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART. - * @retval USART Error Code - */ -uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) -{ - return husart->ErrorCode; -} - -/** - * @} - */ - - -/** - * @brief Simplex Send an amount of data in non-blocking mode. - * @note Function called under interruption only, once - * interruptions have been enabled by HAL_USART_Transmit_IT(). - * @param husart: USART handle - * @retval HAL status - * @note The USART errors are not managed to avoid the overrun error. - */ -static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) -{ - uint16_t* tmp; - - if(husart->State == HAL_USART_STATE_BUSY_TX) - { - - if(husart->TxXferCount == 0U) - { - /* Disable the USART Transmit data register empty interrupt */ - __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - - /* Enable the USART Transmit Complete Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_TC); - - return HAL_OK; - } - else - { - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) - { - tmp = (uint16_t*) husart->pTxBuffPtr; - husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); - husart->pTxBuffPtr += 2U; - } - else - { - husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF); - } - - husart->TxXferCount--; - - return HAL_OK; - } - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Wraps up transmission in non-blocking mode. - * @param husart: pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval HAL status - */ -static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart) -{ - /* Disable the USART Transmit Complete Interrupt */ - CLEAR_BIT(husart->Instance->CR1, USART_CR1_TCIE); - - /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - - husart->State = HAL_USART_STATE_READY; - - HAL_USART_TxCpltCallback(husart); - - return HAL_OK; -} - -/** - * @brief Simplex Receive an amount of data in non-blocking mode. - * Function called under interruption only, once - * interruptions have been enabled by HAL_USART_Receive_IT() - * @param husart: USART handle - * @retval HAL status - */ -static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) -{ - uint16_t* tmp; - uint16_t uhMask = husart->Mask; - - if(husart->State == HAL_USART_STATE_BUSY_RX) - { - - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) - { - tmp = (uint16_t*) husart->pRxBuffPtr; - *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - husart->pRxBuffPtr += 2U; - } - else - { - *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); - } - /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ - husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FFU); - - if(--husart->RxXferCount == 0U) - { - CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE); - - /* Disable the USART Parity Error Interrupt */ - CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); - - /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - - husart->State = HAL_USART_STATE_READY; - - HAL_USART_RxCpltCallback(husart); - - return HAL_OK; - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). - * Function called under interruption only, once - * interruptions have been enabled by HAL_USART_TransmitReceive_IT() - * @param husart: USART handle - * @retval HAL status - */ -static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) -{ - uint16_t* tmp; - uint16_t uhMask = husart->Mask; - - if(husart->State == HAL_USART_STATE_BUSY_TX_RX) - { - if(husart->TxXferCount != 0x00U) - { - if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET) - { - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) - { - tmp = (uint16_t*) husart->pTxBuffPtr; - husart->Instance->TDR = (uint16_t)(*tmp & uhMask); - husart->pTxBuffPtr += 2U; - } - else - { - husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask); - } - husart->TxXferCount--; - - /* Check the latest data transmitted */ - if(husart->TxXferCount == 0U) - { - CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE); - } - } - } - - if(husart->RxXferCount != 0x00U) - { - if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET) - { - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) - { - tmp = (uint16_t*) husart->pRxBuffPtr; - *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - husart->pRxBuffPtr += 2U; - } - else - { - *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); - } - husart->RxXferCount--; - } - } - - /* Check the latest data received */ - if(husart->RxXferCount == 0U) - { - CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE); - - /* Disable the USART Parity Error Interrupt */ - CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); - - /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - - husart->State = HAL_USART_STATE_READY; - - HAL_USART_TxRxCpltCallback(husart); - - return HAL_OK; - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief This function handles USART Communication Timeout. - * @param husart USART handle - * @param Flag specifies the USART flag to check. - * @param Status The new Flag status (SET or RESET). - * @param Tickstart Tick start value - * @param Timeout Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) -{ - /* Wait until flag is set */ - while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U)||((HAL_GetTick()-Tickstart) >= Timeout)) - { - /* Disable the USART Transmit Complete Interrupt */ - CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE); - - /* Disable the USART RXNE Interrupt */ - CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE); - - /* Disable the USART Parity Error Interrupt */ - CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); - - /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - - husart->State= HAL_USART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - - -/** - * @brief DMA USART transmit process complete callback - * @param hdma: DMA handle - * @retval None - */ -static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* DMA Normal mode */ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) - { - husart->TxXferCount = 0U; - - if(husart->State == HAL_USART_STATE_BUSY_TX) - { - /* Disable the DMA transfer for transmit request by resetting the DMAT bit - in the USART CR3 register */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - - /* Enable the USART Transmit Complete Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_TCIE); - } - } - /* DMA Circular mode */ - else - { - if(husart->State == HAL_USART_STATE_BUSY_TX) - { - HAL_USART_TxCpltCallback(husart); - } - } -} - - -/** - * @brief DMA USART transmit process half complete callback - * @param hdma : DMA handle - * @retval None - */ -static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) -{ - USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - HAL_USART_TxHalfCpltCallback(husart); -} - -/** - * @brief DMA USART receive process complete callback - * @param hdma: DMA handle - * @retval None - */ -static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* DMA Normal mode */ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) - { - husart->RxXferCount = 0U; - - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - - /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit - in USART CR3 register */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); - /* similarly, disable the DMA TX transfer that was started to provide the - clock to the slave device */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - - if(husart->State == HAL_USART_STATE_BUSY_RX) - { - HAL_USART_RxCpltCallback(husart); - } - /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ - else - { - HAL_USART_TxRxCpltCallback(husart); - } - husart->State= HAL_USART_STATE_READY; - } - /* DMA circular mode */ - else - { - if(husart->State == HAL_USART_STATE_BUSY_RX) - { - HAL_USART_RxCpltCallback(husart); - } - /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ - else - { - HAL_USART_TxRxCpltCallback(husart); - } - } -} - -/** - * @brief DMA USART receive process half complete callback - * @param hdma : DMA handle - * @retval None - */ -static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - HAL_USART_RxHalfCpltCallback(husart); -} - -/** - * @brief DMA USART communication error callback - * @param hdma: DMA handle - * @retval None - */ -static void USART_DMAError(DMA_HandleTypeDef *hdma) -{ - USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - husart->RxXferCount = 0U; - husart->TxXferCount = 0U; - - /* Stop USART DMA Tx request if ongoing */ - if((husart->State == HAL_USART_STATE_BUSY_TX) - &&(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))) - { - USART_EndTxTransfer(husart); - } - - /* Stop USART DMA Rx request if ongoing */ - if((husart->State == HAL_USART_STATE_BUSY_RX) - &&(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))) - { - USART_EndRxTransfer(husart); - } - - husart->ErrorCode |= HAL_USART_ERROR_DMA; - husart->State= HAL_USART_STATE_READY; - - HAL_USART_ErrorCallback(husart); -} - -/** - * @brief DMA USART communication abort callback - * (To be called at end of DMA Abort procedure). - * @param hdma: DMA handle. - * @retval None - */ -static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma) -{ - USART_HandleTypeDef* husart = (USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - husart->RxXferCount = 0U; - husart->TxXferCount = 0U; - - HAL_USART_ErrorCallback(husart); -} - -/** - * @brief End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion). - * @param husart: USART handle. - * @retval None - */ -static void USART_EndTxTransfer(USART_HandleTypeDef *husart) -{ - /* At end of Tx process, restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; - - /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); -} - -/** - * @brief End ongoing Rx transfer on USART peripheral (following error detection or Reception completion). - * @param husart: USART handle. - * @retval None - */ -static void USART_EndRxTransfer(USART_HandleTypeDef *husart) -{ - /* At end of Rx process, restore husart->RxState to Ready */ - husart->State = HAL_USART_STATE_READY; - - /* Disable RXNE, PE and ERR interrupts */ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); -} - -/** - * @brief Configure the USART peripheral - * @param husart: USART handle - * @retval None - */ -static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) -{ - uint32_t tmpreg = 0x0U; - USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED; - HAL_StatusTypeDef ret = HAL_OK; - uint16_t brrtemp = 0x0000U; - uint16_t usartdiv = 0x0000U; - - /* Check the parameters */ - assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); - assert_param(IS_USART_PHASE(husart->Init.CLKPhase)); - assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit)); - assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate)); - assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength)); - assert_param(IS_USART_STOPBITS(husart->Init.StopBits)); - assert_param(IS_USART_PARITY(husart->Init.Parity)); - assert_param(IS_USART_MODE(husart->Init.Mode)); - assert_param(IS_USART_OVERSAMPLING(husart->Init.OverSampling)); - - - /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Clear M, PCE, PS, TE and RE bits and configure - * the USART Word Length, Parity, Mode and OverSampling: - * set the M bits according to husart->Init.WordLength value - * set PCE and PS bits according to husart->Init.Parity value - * set TE and RE bits according to husart->Init.Mode value - * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */ - tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8; - MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg); - - /*---------------------------- USART CR2 Configuration ---------------------*/ - /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits: - * set CPOL bit according to husart->Init.CLKPolarity value - * set CPHA bit according to husart->Init.CLKPhase value - * set LBCL bit according to husart->Init.CLKLastBit value - * set STOP[13:12] bits according to husart->Init.StopBits value */ - tmpreg = (uint32_t)(USART_CLOCK_ENABLE); - tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase); - tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits); - MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg); - - /*-------------------------- USART CR3 Configuration -----------------------*/ - /* no CR3 register configuration */ - - /*-------------------------- USART BRR Configuration -----------------------*/ - /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */ - USART_GETCLOCKSOURCE(husart, clocksource); - switch (clocksource) - { - case USART_CLOCKSOURCE_PCLK1: - usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_PCLK2: - usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK2Freq()) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_HSI: - usartdiv = (uint16_t)(((2*HSI_VALUE) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint16_t)(((2*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)(((2*LSE_VALUE) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; - } - - brrtemp = usartdiv & 0xFFF0U; - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - husart->Instance->BRR = brrtemp; - - return ret; -} - -/** - * @brief Check the USART Idle State - * @param husart: USART handle - * @retval HAL status - */ -static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) -{ - uint32_t tickstart = 0U; - - /* Initialize the USART ErrorCode */ - husart->ErrorCode = HAL_USART_ERROR_NONE; - - /* Init tickstart for timeout managment*/ - tickstart = HAL_GetTick(); - - /* Check if the Transmitter is enabled */ - if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - { - /* Wait until TEACK flag is set */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK) - { - husart->State= HAL_USART_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - /* Check if the Receiver is enabled */ - if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - /* Wait until REACK flag is set */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK) - { - husart->State= HAL_USART_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - - /* Initialize the USART state*/ - husart->State= HAL_USART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_OK; -} - -/** - * @} - */ - -#endif /* HAL_USART_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_wwdg.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_wwdg.c deleted file mode 100644 index 1830ab9..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_wwdg.c +++ /dev/null @@ -1,322 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_wwdg.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief WWDG HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Window Watchdog (WWDG) peripheral: - * + Initialization and Configuration function - * + IO operation functions - @verbatim - ============================================================================== - ##### WWDG specific features ##### - ============================================================================== - [..] - Once enabled the WWDG generates a system reset on expiry of a programmed - time period, unless the program refreshes the counter (T[6;0] downcounter) - before reaching 0x3F value (i.e. a reset is generated when the counter - value rolls over from 0x40 to 0x3F). - - (+) An MCU reset is also generated if the counter value is refreshed - before the counter has reached the refresh window value. This - implies that the counter must be refreshed in a limited window. - - (+) Once enabled the WWDG cannot be disabled except by a system reset. - - (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has - occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)). - - (+) The WWDG downcounter input clock is derived from the APB clock divided - by a programmable prescaler. - - (+) WWDG downcounter clock (Hz) = PCLK1 / (4096 * Prescaler) - - (+) WWDG timeout (ms) = (1000 * (T[5;0] + 1)) / (WWDG downcounter clock) - where T[5;0] are the lowest 6 bits of downcounter. - - (+) WWDG Counter refresh is allowed between the following limits : - (++) min time (ms) = (1000 * (T[5;0] - Window)) / (WWDG downcounter clock) - (++) max time (ms) = (1000 * (T[5;0] - 0x40)) / (WWDG downcounter clock) - - (+) Min-max timeout value @80 MHz(PCLK1): ~51.2 us / ~26.22 ms - - (+) The Early Wakeup Interrupt (EWI) can be used if specific safety - operations or data logging must be performed before the actual reset is - generated. When the downcounter reaches the value 0x40, an EWI interrupt - is generated and the corresponding interrupt service routine (ISR) can - be used to trigger specific actions (such as communications or data - logging), before resetting the device. - In some applications, the EWI interrupt can be used to manage a software - system check and/or system recovery/graceful degradation, without - generating a WWDG reset. In this case, the corresponding interrupt - service routine (ISR) should reload the WWDG counter to avoid the WWDG - reset, then trigger the required actions. - Note:When the EWI interrupt cannot be served, e.g. due to a system lock - in a higher priority task, the WWDG reset will eventually be generated. - - (+) Debug mode : When the microcontroller enters debug mode (core halted), - the WWDG counter either continues to work normally or stops, depending - on DBG_WWDG_STOP configuration bit in DBG module, accessible through - __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros - - ##### How to use this driver ##### - ============================================================================== - [..] - (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). - - (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup - Interrupt mode using using HAL_WWDG_Init() function. - This enables WWDG peripheral and the downcounter starts downcounting - from given counter value. - Init function can be called again to modify all watchdog parameters, - however if EWI mode has been set once, it can't be clear until next - reset. - - (+) The application program must refresh the WWDG counter at regular - intervals during normal operation to prevent an MCU reset using - HAL_WWDG_Refresh() function. This operation must occur only when - the counter is lower than the window value already programmed. - - (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when - the counter reaches 0x40. User can add his own code in weak function - HAL_WWDG_EarlyWakeupCallback(). - - *** WWDG HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in WWDG HAL driver. - - (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source. - (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status. - (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#ifdef HAL_WWDG_MODULE_ENABLED -/** @defgroup WWDG WWDG - * @brief WWDG HAL module driver. - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup WWDG_Exported_Functions WWDG Exported Functions - * @{ - */ - -/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions. - * -@verbatim - ============================================================================== - ##### Initialization and Configuration functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and start the WWDG according to the specified parameters - in the WWDG_InitTypeDef of associated handle. - (+) Initialize the WWDG MSP. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the WWDG according to the specified. - * parameters in the WWDG_InitTypeDef of associated handle. - * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) -{ - /* Check the WWDG handle allocation */ - if(hwwdg == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance)); - assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler)); - assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window)); - assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter)); - assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode)); - - /* Init the low level hardware */ - HAL_WWDG_MspInit(hwwdg); - - /* Set WWDG Counter */ - WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter)); - - /* Set WWDG Prescaler and Window */ - WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window)); - - /* Return function status */ - return HAL_OK; -} - - -/** - * @brief Initialize the WWDG MSP. - * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @note When rewriting this function in user file, mechanism may be added - * to avoid multiple initialize when HAL_WWDG_Init function is called - * again to change parameters. - * @retval None - */ -__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hwwdg); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_WWDG_MspInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Refresh the WWDG. - (+) Handle WWDG interrupt request and associated function callback. - -@endverbatim - * @{ - */ - -/** - * @brief Refresh the WWDG. - * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg) -{ - /* Write to WWDG CR the WWDG Counter value to refresh with */ - WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter)); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Handle WWDG interrupt request. - * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations - * or data logging must be performed before the actual reset is generated. - * The EWI interrupt is enabled by calling HAL_WWDG_Init function with - * EWIMode set to WWDG_EWI_ENABLE. - * When the downcounter reaches the value 0x40, and EWI interrupt is - * generated and the corresponding Interrupt Service Routine (ISR) can - * be used to trigger specific actions (such as communications or data - * logging), before resetting the device. - * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval None - */ -void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) -{ - /* Check if Early Wakeup Interrupt is enable */ - if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET) - { - /* Check if WWDG Early Wakeup Interrupt occurred */ - if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET) - { - /* Clear the WWDG Early Wakeup flag */ - __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF); - - /* Early Wakeup callback */ - HAL_WWDG_EarlyWakeupCallback(hwwdg); - } - } -} - - -/** - * @brief WWDG Early Wakeup callback. - * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval None - */ -__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hwwdg); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_WWDG_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c deleted file mode 100644 index 374082e..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c +++ /dev/null @@ -1,1117 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_fmc.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief FMC Low Layer HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Flexible Memory Controller (FMC) peripheral memories: - * + Initialization/de-initialization functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### FMC peripheral features ##### - ============================================================================== - [..] The Flexible memory controller (FMC) includes three memory controllers: - (+) The NOR/PSRAM memory controller - (+) The NAND memory controller - (+) The Synchronous DRAM (SDRAM) controller - - [..] The FMC functional block makes the interface with synchronous and asynchronous static - memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are: - (+) to translate AHB transactions into the appropriate external device protocol - (+) to meet the access time requirements of the external memory devices - - [..] All external memories share the addresses, data and control signals with the controller. - Each external device is accessed by means of a unique Chip Select. The FMC performs - only one access at a time to an external device. - The main features of the FMC controller are the following: - (+) Interface with static-memory mapped devices including: - (++) Static random access memory (SRAM) - (++) Read-only memory (ROM) - (++) NOR Flash memory/OneNAND Flash memory - (++) PSRAM (4 memory banks) - (++) 16-bit PC Card compatible devices - (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of - data - (+) Interface with synchronous DRAM (SDRAM) memories - (+) Independent Chip Select control for each memory bank - (+) Independent configuration for each memory bank - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup FMC_LL FMC Low Layer - * @brief FMC driver modules - * @{ - */ - -#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions - * @{ - */ - -/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions - * @brief NORSRAM Controller functions - * - @verbatim - ============================================================================== - ##### How to use NORSRAM device driver ##### - ============================================================================== - - [..] - This driver contains a set of APIs to interface with the FMC NORSRAM banks in order - to run the NORSRAM external devices. - - (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() - (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init() - (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init() - (+) FMC NORSRAM bank extended timing configuration using the function - FMC_NORSRAM_Extended_Timing_Init() - (+) FMC NORSRAM bank enable/disable write operation using the functions - FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() - - -@endverbatim - * @{ - */ - -/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - ============================================================================== - ##### Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the FMC NORSRAM interface - (+) De-initialize the FMC NORSRAM interface - (+) Configure the FMC clock and associated GPIOs - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the FMC_NORSRAM device according to the specified - * control parameters in the FMC_NORSRAM_InitTypeDef - * @param Device: Pointer to NORSRAM device instance - * @param Init: Pointer to NORSRAM Initialization structure - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init) -{ - uint32_t tmpr = 0; - - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); - assert_param(IS_FMC_MUX(Init->DataAddressMux)); - assert_param(IS_FMC_MEMORY(Init->MemoryType)); - assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); - assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); - assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); - assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); - assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); - assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); - assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); - assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); - assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); - assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); - assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); - assert_param(IS_FMC_PAGESIZE(Init->PageSize)); - - /* Get the BTCR register value */ - tmpr = Device->BTCR[Init->NSBank]; - - /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN, - WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */ - tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \ - FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \ - FMC_BCR1_WAITPOL | FMC_BCR1_CPSIZE | FMC_BCR1_WAITCFG | \ - FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \ - FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS)); - - /* Set NORSRAM device control parameters */ - tmpr |= (uint32_t)(Init->DataAddressMux |\ - Init->MemoryType |\ - Init->MemoryDataWidth |\ - Init->BurstAccessMode |\ - Init->WaitSignalPolarity |\ - Init->WaitSignalActive |\ - Init->WriteOperation |\ - Init->WaitSignal |\ - Init->ExtendedMode |\ - Init->AsynchronousWait |\ - Init->WriteBurst |\ - Init->ContinuousClock |\ - Init->PageSize |\ - Init->WriteFifo); - - if(Init->MemoryType == FMC_MEMORY_TYPE_NOR) - { - tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE; - } - - Device->BTCR[Init->NSBank] = tmpr; - - /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ - if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) - { - Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock); - } - if(Init->NSBank != FMC_NORSRAM_BANK1) - { - Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo); - } - - return HAL_OK; -} - - -/** - * @brief DeInitialize the FMC_NORSRAM peripheral - * @param Device: Pointer to NORSRAM device instance - * @param ExDevice: Pointer to NORSRAM extended mode device instance - * @param Bank: NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); - assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Disable the FMC_NORSRAM device */ - __FMC_NORSRAM_DISABLE(Device, Bank); - - /* De-initialize the FMC_NORSRAM device */ - /* FMC_NORSRAM_BANK1 */ - if(Bank == FMC_NORSRAM_BANK1) - { - Device->BTCR[Bank] = 0x000030DB; - } - /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ - else - { - Device->BTCR[Bank] = 0x000030D2; - } - - Device->BTCR[Bank + 1] = 0x0FFFFFFF; - ExDevice->BWTR[Bank] = 0x0FFFFFFF; - - return HAL_OK; -} - - -/** - * @brief Initialize the FMC_NORSRAM Timing according to the specified - * parameters in the FMC_NORSRAM_TimingTypeDef - * @param Device: Pointer to NORSRAM device instance - * @param Timing: Pointer to NORSRAM Timing structure - * @param Bank: NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) -{ - uint32_t tmpr = 0; - - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); - assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); - assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); - assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); - assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); - assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); - assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); - assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Get the BTCR register value */ - tmpr = Device->BTCR[Bank + 1]; - - /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ - tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \ - FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \ - FMC_BTR1_ACCMOD)); - - /* Set FMC_NORSRAM device timing parameters */ - tmpr |= (uint32_t)(Timing->AddressSetupTime |\ - ((Timing->AddressHoldTime) << 4) |\ - ((Timing->DataSetupTime) << 8) |\ - ((Timing->BusTurnAroundDuration) << 16) |\ - (((Timing->CLKDivision)-1) << 20) |\ - (((Timing->DataLatency)-2) << 24) |\ - (Timing->AccessMode) - ); - - Device->BTCR[Bank + 1] = tmpr; - - /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ - if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) - { - tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20)); - tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20); - Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr; - } - - return HAL_OK; -} - -/** - * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified - * parameters in the FMC_NORSRAM_TimingTypeDef - * @param Device: Pointer to NORSRAM device instance - * @param Timing: Pointer to NORSRAM Timing structure - * @param Bank: NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) -{ - uint32_t tmpr = 0; - - /* Check the parameters */ - assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); - - /* Set NORSRAM device timing register for write configuration, if extended mode is used */ - if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE) - { - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); - assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); - assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); - assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); - assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); - assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); - assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); - assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); - assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Get the BWTR register value */ - tmpr = Device->BWTR[Bank]; - - /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ - tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \ - FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD)); - - tmpr |= (uint32_t)(Timing->AddressSetupTime |\ - ((Timing->AddressHoldTime) << 4) |\ - ((Timing->DataSetupTime) << 8) |\ - ((Timing->BusTurnAroundDuration) << 16) |\ - (Timing->AccessMode)); - - Device->BWTR[Bank] = tmpr; - } - else - { - Device->BWTR[Bank] = 0x0FFFFFFF; - } - - return HAL_OK; -} -/** - * @} - */ - -/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 - * @brief management functions - * -@verbatim - ============================================================================== - ##### FMC_NORSRAM Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the FMC NORSRAM interface. - -@endverbatim - * @{ - */ - -/** - * @brief Enables dynamically FMC_NORSRAM write operation. - * @param Device: Pointer to NORSRAM device instance - * @param Bank: NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Enable write operation */ - Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE; - - return HAL_OK; -} - -/** - * @brief Disables dynamically FMC_NORSRAM write operation. - * @param Device: Pointer to NORSRAM device instance - * @param Bank: NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Disable write operation */ - Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE; - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions - * @brief NAND Controller functions - * - @verbatim - ============================================================================== - ##### How to use NAND device driver ##### - ============================================================================== - [..] - This driver contains a set of APIs to interface with the FMC NAND banks in order - to run the NAND external devices. - - (+) FMC NAND bank reset using the function FMC_NAND_DeInit() - (+) FMC NAND bank control configuration using the function FMC_NAND_Init() - (+) FMC NAND bank common space timing configuration using the function - FMC_NAND_CommonSpace_Timing_Init() - (+) FMC NAND bank attribute space timing configuration using the function - FMC_NAND_AttributeSpace_Timing_Init() - (+) FMC NAND bank enable/disable ECC correction feature using the functions - FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable() - (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() - -@endverbatim - * @{ - */ - -/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the FMC NAND interface - (+) De-initialize the FMC NAND interface - (+) Configure the FMC clock and associated GPIOs - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the FMC_NAND device according to the specified - * control parameters in the FMC_NAND_HandleTypeDef - * @param Device: Pointer to NAND device instance - * @param Init: Pointer to NAND Initialization structure - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) -{ - uint32_t tmpr = 0; - - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Init->NandBank)); - assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); - assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); - assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); - assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); - assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); - assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); - - /* Get the NAND bank 3 register value */ - tmpr = Device->PCR; - - /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ - tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \ - FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \ - FMC_PCR_TAR | FMC_PCR_ECCPS)); - /* Set NAND device control parameters */ - tmpr |= (uint32_t)(Init->Waitfeature |\ - FMC_PCR_MEMORY_TYPE_NAND |\ - Init->MemoryDataWidth |\ - Init->EccComputation |\ - Init->ECCPageSize |\ - ((Init->TCLRSetupTime) << 9) |\ - ((Init->TARSetupTime) << 13)); - - /* NAND bank 3 registers configuration */ - Device->PCR = tmpr; - - return HAL_OK; - -} - -/** - * @brief Initializes the FMC_NAND Common space Timing according to the specified - * parameters in the FMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to NAND device instance - * @param Timing: Pointer to NAND timing structure - * @param Bank: NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) -{ - uint32_t tmpr = 0; - - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); - assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Get the NAND bank 3 register value */ - tmpr = Device->PMEM; - - /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ - tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET3 | FMC_PMEM_MEMWAIT3 | FMC_PMEM_MEMHOLD3 | \ - FMC_PMEM_MEMHIZ3)); - /* Set FMC_NAND device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8) |\ - ((Timing->HoldSetupTime) << 16) |\ - ((Timing->HiZSetupTime) << 24) - ); - - /* NAND bank 3 registers configuration */ - Device->PMEM = tmpr; - - return HAL_OK; -} - -/** - * @brief Initializes the FMC_NAND Attribute space Timing according to the specified - * parameters in the FMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to NAND device instance - * @param Timing: Pointer to NAND timing structure - * @param Bank: NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) -{ - uint32_t tmpr = 0; - - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); - assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Get the NAND bank 3 register value */ - tmpr = Device->PATT; - - /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ - tmpr &= ((uint32_t)~(FMC_PATT_ATTSET3 | FMC_PATT_ATTWAIT3 | FMC_PATT_ATTHOLD3 | \ - FMC_PATT_ATTHIZ3)); - /* Set FMC_NAND device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8) |\ - ((Timing->HoldSetupTime) << 16) |\ - ((Timing->HiZSetupTime) << 24)); - - /* NAND bank 3 registers configuration */ - Device->PATT = tmpr; - - return HAL_OK; -} - -/** - * @brief DeInitializes the FMC_NAND device - * @param Device: Pointer to NAND device instance - * @param Bank: NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Disable the NAND Bank */ - __FMC_NAND_DISABLE(Device); - - /* Set the FMC_NAND_BANK3 registers to their reset values */ - Device->PCR = 0x00000018U; - Device->SR = 0x00000040U; - Device->PMEM = 0xFCFCFCFCU; - Device->PATT = 0xFCFCFCFCU; - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup HAL_FMC_NAND_Group3 Control functions - * @brief management functions - * -@verbatim - ============================================================================== - ##### FMC_NAND Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the FMC NAND interface. - -@endverbatim - * @{ - */ - - -/** - * @brief Enables dynamically FMC_NAND ECC feature. - * @param Device: Pointer to NAND device instance - * @param Bank: NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Enable ECC feature */ - Device->PCR |= FMC_PCR_ECCEN; - - return HAL_OK; -} - - -/** - * @brief Disables dynamically FMC_NAND ECC feature. - * @param Device: Pointer to NAND device instance - * @param Bank: NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Disable ECC feature */ - Device->PCR &= ~FMC_PCR_ECCEN; - - return HAL_OK; -} - -/** - * @brief Disables dynamically FMC_NAND ECC feature. - * @param Device: Pointer to NAND device instance - * @param ECCval: Pointer to ECC value - * @param Bank: NAND bank number - * @param Timeout: Timeout wait value - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until FIFO is empty */ - while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - return HAL_TIMEOUT; - } - } - } - - /* Get the ECCR register value */ - *ECCval = (uint32_t)Device->ECCR; - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FMC_LL_SDRAM - * @brief SDRAM Controller functions - * - @verbatim - ============================================================================== - ##### How to use SDRAM device driver ##### - ============================================================================== - [..] - This driver contains a set of APIs to interface with the FMC SDRAM banks in order - to run the SDRAM external devices. - - (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() - (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init() - (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init() - (+) FMC SDRAM bank enable/disable write operation using the functions - FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable() - (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand() - -@endverbatim - * @{ - */ - -/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1 - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the FMC SDRAM interface - (+) De-initialize the FMC SDRAM interface - (+) Configure the FMC clock and associated GPIOs - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the FMC_SDRAM device according to the specified - * control parameters in the FMC_SDRAM_InitTypeDef - * @param Device: Pointer to SDRAM device instance - * @param Init: Pointer to SDRAM Initialization structure - * @retval HAL status - */ -HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) -{ - uint32_t tmpr1 = 0; - uint32_t tmpr2 = 0; - - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); - assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber)); - assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber)); - assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth)); - assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber)); - assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency)); - assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection)); - assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); - assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); - assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); - - /* Set SDRAM bank configuration parameters */ - if (Init->SDBank != FMC_SDRAM_BANK2) - { - tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; - - /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ - tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ - FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ - FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); - - tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\ - Init->RowBitsNumber |\ - Init->MemoryDataWidth |\ - Init->InternalBankNumber |\ - Init->CASLatency |\ - Init->WriteProtection |\ - Init->SDClockPeriod |\ - Init->ReadBurst |\ - Init->ReadPipeDelay - ); - Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; - } - else /* FMC_Bank2_SDRAM */ - { - tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; - - /* Clear SDCLK, RBURST, and RPIPE bits */ - tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); - - tmpr1 |= (uint32_t)(Init->SDClockPeriod |\ - Init->ReadBurst |\ - Init->ReadPipeDelay); - - tmpr2 = Device->SDCR[FMC_SDRAM_BANK2]; - - /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ - tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ - FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ - FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); - - tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\ - Init->RowBitsNumber |\ - Init->MemoryDataWidth |\ - Init->InternalBankNumber |\ - Init->CASLatency |\ - Init->WriteProtection); - - Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; - Device->SDCR[FMC_SDRAM_BANK2] = tmpr2; - } - - return HAL_OK; -} - - -/** - * @brief Initializes the FMC_SDRAM device timing according to the specified - * parameters in the FMC_SDRAM_TimingTypeDef - * @param Device: Pointer to SDRAM device instance - * @param Timing: Pointer to SDRAM Timing structure - * @param Bank: SDRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) -{ - uint32_t tmpr1 = 0; - uint32_t tmpr2 = 0; - - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); - assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay)); - assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime)); - assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay)); - assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime)); - assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); - assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); - assert_param(IS_FMC_SDRAM_BANK(Bank)); - - /* Set SDRAM device timing parameters */ - if (Bank != FMC_SDRAM_BANK2) - { - tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; - - /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ - tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ - FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ - FMC_SDTR1_TRCD)); - - tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ - (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ - (((Timing->SelfRefreshTime)-1) << 8) |\ - (((Timing->RowCycleDelay)-1) << 12) |\ - (((Timing->WriteRecoveryTime)-1) <<16) |\ - (((Timing->RPDelay)-1) << 20) |\ - (((Timing->RCDDelay)-1) << 24)); - Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; - } - else /* FMC_Bank2_SDRAM */ - { - tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; - - /* Clear TRC and TRP bits */ - tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP)); - - tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\ - (((Timing->RPDelay)-1) << 20)); - - tmpr2 = Device->SDTR[FMC_SDRAM_BANK2]; - - /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ - tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ - FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ - FMC_SDTR1_TRCD)); - - tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ - (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ - (((Timing->SelfRefreshTime)-1) << 8) |\ - (((Timing->WriteRecoveryTime)-1) <<16) |\ - (((Timing->RCDDelay)-1) << 24)); - - Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; - Device->SDTR[FMC_SDRAM_BANK2] = tmpr2; - } - - return HAL_OK; -} - -/** - * @brief DeInitializes the FMC_SDRAM peripheral - * @param Device: Pointer to SDRAM device instance - * @retval HAL status - */ -HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_SDRAM_BANK(Bank)); - - /* De-initialize the SDRAM device */ - Device->SDCR[Bank] = 0x000002D0; - Device->SDTR[Bank] = 0x0FFFFFFF; - Device->SDCMR = 0x00000000; - Device->SDRTR = 0x00000000; - Device->SDSR = 0x00000000; - - return HAL_OK; -} - -/** - * @} - */ - -/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2 - * @brief management functions - * -@verbatim - ============================================================================== - ##### FMC_SDRAM Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the FMC SDRAM interface. - -@endverbatim - * @{ - */ - -/** - * @brief Enables dynamically FMC_SDRAM write protection. - * @param Device: Pointer to SDRAM device instance - * @param Bank: SDRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_SDRAM_BANK(Bank)); - - /* Enable write protection */ - Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE; - - return HAL_OK; -} - -/** - * @brief Disables dynamically FMC_SDRAM write protection. - * @param hsdram: FMC_SDRAM handle - * @retval HAL status - */ -HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_SDRAM_BANK(Bank)); - - /* Disable write protection */ - Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE; - - return HAL_OK; -} - -/** - * @brief Send Command to the FMC SDRAM bank - * @param Device: Pointer to SDRAM device instance - * @param Command: Pointer to SDRAM command structure - * @param Timing: Pointer to SDRAM Timing structure - * @param Timeout: Timeout wait value - * @retval HAL state - */ -HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) -{ - __IO uint32_t tmpr = 0; - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode)); - assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget)); - assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber)); - assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); - - /* Set command register */ - tmpr = (uint32_t)((Command->CommandMode) |\ - (Command->CommandTarget) |\ - (((Command->AutoRefreshNumber)-1) << 5) |\ - ((Command->ModeRegisterDefinition) << 9) - ); - - Device->SDCMR = tmpr; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* wait until command is send */ - while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - return HAL_TIMEOUT; - } - } - } - - return HAL_OK; -} - -/** - * @brief Program the SDRAM Memory Refresh rate. - * @param Device: Pointer to SDRAM device instance - * @param RefreshRate: The SDRAM refresh rate value. - * @retval HAL state - */ -HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) -{ - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_REFRESH_RATE(RefreshRate)); - - /* Set the refresh rate in command register */ - Device->SDRTR |= (RefreshRate<<1); - - return HAL_OK; -} - -/** - * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands. - * @param Device: Pointer to SDRAM device instance - * @param AutoRefreshNumber: Specifies the auto Refresh number. - * @retval None - */ -HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber) -{ - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber)); - - /* Set the Auto-refresh number in command register */ - Device->SDCMR |= (AutoRefreshNumber << 5); - - return HAL_OK; -} - -/** - * @brief Returns the indicated FMC SDRAM bank mode status. - * @param Device: Pointer to SDRAM device instance - * @param Bank: Defines the FMC SDRAM bank. This parameter can be - * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. - * @retval The FMC SDRAM bank mode status, could be on of the following values: - * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or - * FMC_SDRAM_POWER_DOWN_MODE. - */ -uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_SDRAM_BANK(Bank)); - - /* Get the corresponding bank mode */ - if(Bank == FMC_SDRAM_BANK1) - { - tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); - } - else - { - tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2); - } - - /* Return the mode status */ - return tmpreg; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c deleted file mode 100644 index e88059c..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c +++ /dev/null @@ -1,509 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_sdmmc.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief SDMMC Low Layer HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the SDMMC peripheral: - * + Initialization/de-initialization functions - * + I/O operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### SDMMC peripheral features ##### - ============================================================================== - [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2 - peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA - devices. - - [..] The SDMMC features include the following: - (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support - for three different databus modes: 1-bit (default), 4-bit and 8-bit - (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility) - (+) Full compliance with SD Memory Card Specifications Version 2.0 - (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two - different data bus modes: 1-bit (default) and 4-bit - (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol - Rev1.1) - (+) Data transfer up to 48 MHz for the 8 bit mode - (+) Data and command output enable signals to control external bidirectional drivers. - - - ##### How to use this driver ##### - ============================================================================== - [..] - This driver is a considered as a driver of service for external devices drivers - that interfaces with the SDMMC peripheral. - According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs - is used in the device's driver to perform SDMMC operations and functionalities. - - This driver is almost transparent for the final user, it is only used to implement other - functionalities of the external device. - - [..] - (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output of PLL - (PLL48CLK). Before start working with SDMMC peripheral make sure that the - PLL is well configured. - The SDMMC peripheral uses two clock signals: - (++) SDMMC adapter clock (SDMMCCLK = 48 MHz) - (++) APB2 bus clock (PCLK2) - - -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition: - Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK)) - - (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC - peripheral. - - (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx) - function and disable it using the function SDMMC_PowerState_OFF(SDMMCx). - - (+) Enable/Disable the clock using the __SDMMC_ENABLE()/__SDMMC_DISABLE() macros. - - (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT) - and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode. - - (+) When using the DMA mode - (++) Configure the DMA in the MSP layer of the external device - (++) Active the needed channel Request - (++) Enable the DMA using __SDMMC_DMA_ENABLE() macro or Disable it using the macro - __SDMMC_DMA_DISABLE(). - - (+) To control the CPSM (Command Path State Machine) and send - commands to the card use the SDMMC_SendCommand(SDMMCx), - SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has - to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according - to the selected command to be sent. - The parameters that should be filled are: - (++) Command Argument - (++) Command Index - (++) Command Response type - (++) Command Wait - (++) CPSM Status (Enable or Disable). - - -@@- To check if the command is well received, read the SDMMC_CMDRESP - register using the SDMMC_GetCommandResponse(). - The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the - SDMMC_GetResponse() function. - - (+) To control the DPSM (Data Path State Machine) and send/receive - data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(), - SDMMC_ReadFIFO(), DIO_WriteFIFO() and SDMMC_GetFIFOCount() functions. - - *** Read Operations *** - ======================= - [..] - (#) First, user has to fill the data structure (pointer to - SDMMC_DataInitTypeDef) according to the selected data type to be received. - The parameters that should be filled are: - (++) Data TimeOut - (++) Data Length - (++) Data Block size - (++) Data Transfer direction: should be from card (To SDMMC) - (++) Data Transfer mode - (++) DPSM Status (Enable or Disable) - - (#) Configure the SDMMC resources to receive the data from the card - according to selected transfer mode (Refer to Step 8, 9 and 10). - - (#) Send the selected Read command (refer to step 11). - - (#) Use the SDMMC flags/interrupts to check the transfer status. - - *** Write Operations *** - ======================== - [..] - (#) First, user has to fill the data structure (pointer to - SDMMC_DataInitTypeDef) according to the selected data type to be received. - The parameters that should be filled are: - (++) Data TimeOut - (++) Data Length - (++) Data Block size - (++) Data Transfer direction: should be to card (To CARD) - (++) Data Transfer mode - (++) DPSM Status (Enable or Disable) - - (#) Configure the SDMMC resources to send the data to the card according to - selected transfer mode. - - (#) Send the selected Write command. - - (#) Use the SDMMC flags/interrupts to check the transfer status. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup SDMMC_LL SDMMC Low Layer - * @brief Low layer module for SD - * @{ - */ - -#if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions - * @{ - */ - -/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization/de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the SDMMC according to the specified - * parameters in the SDMMC_InitTypeDef and create the associated handle. - * @param SDMMCx: Pointer to SDMMC register base - * @param Init: SDMMC initialization structure - * @retval HAL status - */ -HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx)); - assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge)); - assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass)); - assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave)); - assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide)); - assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); - assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv)); - - /* Set SDMMC configuration parameters */ - tmpreg |= (Init.ClockEdge |\ - Init.ClockBypass |\ - Init.ClockPowerSave |\ - Init.BusWide |\ - Init.HardwareFlowControl |\ - Init.ClockDiv - ); - - /* Write to SDMMC CLKCR */ - MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); - - return HAL_OK; -} - - -/** - * @} - */ - -/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### I/O operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the SDMMC data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Read data (word) from Rx FIFO in blocking mode (polling) - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx) -{ - /* Read data from Rx FIFO */ - return (SDMMCx->FIFO); -} - -/** - * @brief Write data (word) to Tx FIFO in blocking mode (polling) - * @param SDMMCx: Pointer to SDMMC register base - * @param pWriteData: pointer to data to write - * @retval HAL status - */ -HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData) -{ - /* Write data to FIFO */ - SDMMCx->FIFO = *pWriteData; - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions - * @brief management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the SDMMC data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Set SDMMC Power state to ON. - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx) -{ - /* Set power state to ON */ - SDMMCx->POWER = SDMMC_POWER_PWRCTRL; - - return HAL_OK; -} - -/** - * @brief Set SDMMC Power state to OFF. - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx) -{ - /* Set power state to OFF */ - SDMMCx->POWER = (uint32_t)0x00000000; - - return HAL_OK; -} - -/** - * @brief Get SDMMC Power state. - * @param SDMMCx: Pointer to SDMMC register base - * @retval Power status of the controller. The returned value can be one of the - * following values: - * - 0x00: Power OFF - * - 0x02: Power UP - * - 0x03: Power ON - */ -uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx) -{ - return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL); -} - -/** - * @brief Configure the SDMMC command path according to the specified parameters in - * SDMMC_CmdInitTypeDef structure and send the command - * @param SDMMCx: Pointer to SDMMC register base - * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains - * the configuration information for the SDMMC command - * @retval HAL status - */ -HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex)); - assert_param(IS_SDMMC_RESPONSE(Command->Response)); - assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt)); - assert_param(IS_SDMMC_CPSM(Command->CPSM)); - - /* Set the SDMMC Argument value */ - SDMMCx->ARG = Command->Argument; - - /* Set SDMMC command parameters */ - tmpreg |= (uint32_t)(Command->CmdIndex |\ - Command->Response |\ - Command->WaitForInterrupt |\ - Command->CPSM); - - /* Write to SDMMC CMD register */ - MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg); - - return HAL_OK; -} - -/** - * @brief Return the command index of last command for which response received - * @param SDMMCx: Pointer to SDMMC register base - * @retval Command index of the last command response received - */ -uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx) -{ - return (uint8_t)(SDMMCx->RESPCMD); -} - - -/** - * @brief Return the response received from the card for the last command - * @param SDMMCx: Pointer to SDMMC register base - * @param Response: Specifies the SDMMC response register. - * This parameter can be one of the following values: - * @arg SDMMC_RESP1: Response Register 1 - * @arg SDMMC_RESP2: Response Register 2 - * @arg SDMMC_RESP3: Response Register 3 - * @arg SDMMC_RESP4: Response Register 4 - * @retval The Corresponding response register value - */ -uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_SDMMC_RESP(Response)); - - /* Get the response */ - tmp = (uint32_t)&(SDMMCx->RESP1) + Response; - - return (*(__IO uint32_t *) tmp); -} - -/** - * @brief Configure the SDMMC data path according to the specified - * parameters in the SDMMC_DataInitTypeDef. - * @param SDMMCx: Pointer to SDMMC register base - * @param Data : pointer to a SDMMC_DataInitTypeDef structure - * that contains the configuration information for the SDMMC data. - * @retval HAL status - */ -HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength)); - assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize)); - assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir)); - assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode)); - assert_param(IS_SDMMC_DPSM(Data->DPSM)); - - /* Set the SDMMC Data TimeOut value */ - SDMMCx->DTIMER = Data->DataTimeOut; - - /* Set the SDMMC DataLength value */ - SDMMCx->DLEN = Data->DataLength; - - /* Set the SDMMC data configuration parameters */ - tmpreg |= (uint32_t)(Data->DataBlockSize |\ - Data->TransferDir |\ - Data->TransferMode |\ - Data->DPSM); - - /* Write to SDMMC DCTRL */ - MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg); - - return HAL_OK; - -} - -/** - * @brief Returns number of remaining data bytes to be transferred. - * @param SDMMCx: Pointer to SDMMC register base - * @retval Number of remaining data bytes to be transferred - */ -uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx) -{ - return (SDMMCx->DCOUNT); -} - -/** - * @brief Get the FIFO data - * @param SDMMCx: Pointer to SDMMC register base - * @retval Data received - */ -uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx) -{ - return (SDMMCx->FIFO); -} - - -/** - * @brief Sets one of the two options of inserting read wait interval. - * @param SDMMCx: Pointer to SDMMC register base - * @param SDMMC_ReadWaitMode: SDMMC Read Wait operation mode. - * This parameter can be: - * @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK - * @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2 - * @retval None - */ -HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode) -{ - /* Check the parameters */ - assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode)); - - /* Set SDMMC read wait mode */ - MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode); - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c b/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c deleted file mode 100644 index 4c7f92a..0000000 --- a/int/com/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c +++ /dev/null @@ -1,1689 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_usb.c - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief USB Low Layer HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Initialization/de-initialization functions - * + I/O operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure. - - (#) Call USB_CoreInit() API to initialize the USB Core peripheral. - - (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_LL_USB_DRIVER - * @{ - */ - -#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions - * @{ - */ - -/** @defgroup LL_USB_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization/de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the USB Core - * @param USBx: USB Instance - * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) -{ - if (cfg.phy_itface == USB_OTG_ULPI_PHY) - { - - USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); - - /* Init The ULPI Interface */ - USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); - - /* Select vbus source */ - USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); - if(cfg.use_external_vbus == 1) - { - USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; - } - /* Reset after a PHY select */ - USB_CoreReset(USBx); - } - else /* FS interface (embedded Phy) */ - { - /* Select FS Embedded PHY */ - USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; - - /* Reset after a PHY select and set Host mode */ - USB_CoreReset(USBx); - - /* Deactivate the power down*/ - USBx->GCCFG = USB_OTG_GCCFG_PWRDWN; - } - - if(cfg.dma_enable == ENABLE) - { - USBx->GAHBCFG |= (USB_OTG_GAHBCFG_HBSTLEN_1 | USB_OTG_GAHBCFG_HBSTLEN_2); - USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; - } - - return HAL_OK; -} - -/** - * @brief USB_EnableGlobalInt - * Enables the controller's Global Int in the AHB Config reg - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) -{ - USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; - return HAL_OK; -} - - -/** - * @brief USB_DisableGlobalInt - * Disable the controller's Global Int in the AHB Config reg - * @param USBx : Selected device - * @retval HAL status -*/ -HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) -{ - USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; - return HAL_OK; -} - -/** - * @brief USB_SetCurrentMode : Set functional mode - * @param USBx : Selected device - * @param mode : current core mode - * This parameter can be one of these values: - * @arg USB_OTG_DEVICE_MODE: Peripheral mode - * @arg USB_OTG_HOST_MODE: Host mode - * @arg USB_OTG_DRD_MODE: Dual Role Device mode - * @retval HAL status - */ -HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode) -{ - USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); - - if ( mode == USB_OTG_HOST_MODE) - { - USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; - } - else if ( mode == USB_OTG_DEVICE_MODE) - { - USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; - } - HAL_Delay(50); - - return HAL_OK; -} - -/** - * @brief USB_DevInit : Initializes the USB_OTG controller registers - * for device mode - * @param USBx : Selected device - * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) -{ - uint32_t i = 0; - - /*Activate VBUS Sensing B */ - USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; - - if (cfg.vbus_sensing_enable == 0) - { - /* Deactivate VBUS Sensing B */ - USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN; - - /* B-peripheral session valid override enable*/ - USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; - USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; - } - - /* Restart the Phy Clock */ - USBx_PCGCCTL = 0; - - /* Device mode configuration */ - USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; - - if(cfg.phy_itface == USB_OTG_ULPI_PHY) - { - if(cfg.speed == USB_OTG_SPEED_HIGH) - { - /* Set High speed phy */ - USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH); - } - else - { - /* set High speed phy in Full speed mode */ - USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL); - } - } - else - { - /* Set Full speed phy */ - USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL); - } - - /* Flush the FIFOs */ - USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */ - USB_FlushRxFifo(USBx); - - /* Clear all pending Device Interrupts */ - USBx_DEVICE->DIEPMSK = 0; - USBx_DEVICE->DOEPMSK = 0; - USBx_DEVICE->DAINT = 0xFFFFFFFF; - USBx_DEVICE->DAINTMSK = 0; - - for (i = 0; i < cfg.dev_endpoints; i++) - { - if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) - { - USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK); - } - else - { - USBx_INEP(i)->DIEPCTL = 0; - } - - USBx_INEP(i)->DIEPTSIZ = 0; - USBx_INEP(i)->DIEPINT = 0xFF; - } - - for (i = 0; i < cfg.dev_endpoints; i++) - { - if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) - { - USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK); - } - else - { - USBx_OUTEP(i)->DOEPCTL = 0; - } - - USBx_OUTEP(i)->DOEPTSIZ = 0; - USBx_OUTEP(i)->DOEPINT = 0xFF; - } - - USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); - - if (cfg.dma_enable == 1) - { - /*Set threshold parameters */ - USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6); - USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN); - - i= USBx_DEVICE->DTHRCTL; - } - - /* Disable all interrupts. */ - USBx->GINTMSK = 0; - - /* Clear any pending interrupts */ - USBx->GINTSTS = 0xBFFFFFFF; - - /* Enable the common interrupts */ - if (cfg.dma_enable == DISABLE) - { - USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; - } - - /* Enable interrupts matching to the Device mode ONLY */ - USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\ - USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\ - USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\ - USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); - - if(cfg.Sof_enable) - { - USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; - } - - if (cfg.vbus_sensing_enable == ENABLE) - { - USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); - } - - return HAL_OK; -} - - -/** - * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO - * @param USBx : Selected device - * @param num : FIFO number - * This parameter can be a value from 1 to 15 - 15 means Flush all Tx FIFOs - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ) -{ - uint32_t count = 0; - - USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6)); - - do - { - if (++count > 200000) - { - return HAL_TIMEOUT; - } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); - - return HAL_OK; -} - - -/** - * @brief USB_FlushRxFifo : Flush Rx FIFO - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t count = 0; - - USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; - - do - { - if (++count > 200000) - { - return HAL_TIMEOUT; - } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); - - return HAL_OK; -} - -/** - * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register - * depending the PHY type and the enumeration speed of the device. - * @param USBx : Selected device - * @param speed : device speed - * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode - * @arg USB_OTG_SPEED_FULL: Full speed mode - * @arg USB_OTG_SPEED_LOW: Low speed mode - * @retval Hal status - */ -HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed) -{ - USBx_DEVICE->DCFG |= speed; - return HAL_OK; -} - -/** - * @brief USB_GetDevSpeed :Return the Dev Speed - * @param USBx : Selected device - * @retval speed : device speed - * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_FULL: Full speed mode - * @arg USB_OTG_SPEED_LOW: Low speed mode - */ -uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) -{ - uint8_t speed = 0; - - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) - { - speed = USB_OTG_SPEED_HIGH; - } - else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)|| - ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ)) - { - speed = USB_OTG_SPEED_FULL; - } - else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) - { - speed = USB_OTG_SPEED_LOW; - } - - return speed; -} - -/** - * @brief Activate and configure an endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) -{ - if (ep->is_in == 1) - { - USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))); - - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0) - { - USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); - } - - } - else - { - USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16); - - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0) - { - USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP)); - } - } - return HAL_OK; -} -/** - * @brief Activate and configure a dedicated endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) -{ - static __IO uint32_t debug = 0; - - /* Read DEPCTLn register */ - if (ep->is_in == 1) - { - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0) - { - USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); - } - - - debug |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); - - USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))); - } - else - { - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0) - { - USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); - - debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE); - debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL; - debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); - } - - USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16); - } - - return HAL_OK; -} -/** - * @brief De-activate and de-initialize an endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) -{ - /* Read DEPCTLn register */ - if (ep->is_in == 1) - { - USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); - USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; - } - else - { - USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); - USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; - } - return HAL_OK; -} - -/** - * @brief De-activate and de-initialize a dedicated endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) -{ - /* Read DEPCTLn register */ - if (ep->is_in == 1) - { - USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); - } - else - { - USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); - } - return HAL_OK; -} - -/** - * @brief USB_EPStartXfer : setup and starts a transfer over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma) -{ - uint16_t pktcnt = 0; - - /* IN endpoint */ - if (ep->is_in == 1) - { - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - } - else - { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - - if (ep->type == EP_TYPE_ISOC) - { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29)); - } - } - - if (dma == 1) - { - USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr); - } - else - { - if (ep->type != EP_TYPE_ISOC) - { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) - { - USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num; - } - } - } - - if (ep->type == EP_TYPE_ISOC) - { - if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0) - { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; - } - else - { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; - } - } - - /* EP enable, IN data in FIFO */ - USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - - if (ep->type == EP_TYPE_ISOC) - { - USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma); - } - } - else /* OUT endpoint */ - { - /* Program the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - - if (ep->xfer_len == 0) - { - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ; - } - else - { - pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket; - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19)); - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt)); - } - - if (dma == 1) - { - USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff; - } - - if (ep->type == EP_TYPE_ISOC) - { - if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0) - { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; - } - else - { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; - } - } - /* EP enable */ - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); - } - return HAL_OK; -} - -/** - * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0 - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL status - */ -HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma) -{ - /* IN endpoint */ - if (ep->is_in == 1) - { - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - } - else - { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - - if(ep->xfer_len > ep->maxpacket) - { - ep->xfer_len = ep->maxpacket; - } - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - - } - - if (dma == 1) - { - USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr); - } - else - { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) - { - USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num); - } - } - - /* EP enable, IN data in FIFO */ - USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - } - else /* OUT endpoint */ - { - /* Program the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - - if (ep->xfer_len > 0) - { - ep->xfer_len = ep->maxpacket; - } - - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)); - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); - - - if (dma == 1) - { - USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff); - } - - /* EP enable */ - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); - } - return HAL_OK; -} - -/** - * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated - * with the EP/channel - * @param USBx : Selected device - * @param src : pointer to source buffer - * @param ch_ep_num : endpoint or host channel number - * @param len : Number of bytes to write - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL status - */ -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) -{ - uint32_t count32b= 0 , i= 0; - - if (dma == 0) - { - count32b = (len + 3) / 4; - for (i = 0; i < count32b; i++, src += 4) - { - USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src); - } - } - return HAL_OK; -} - -/** - * @brief USB_ReadPacket : read a packet from the Tx FIFO associated - * with the EP/channel - * @param USBx : Selected device - * @param src : source pointer - * @param ch_ep_num : endpoint or host channel number - * @param len : Number of bytes to read - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval pointer to destination buffer - */ -void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) -{ - uint32_t i=0; - uint32_t count32b = (len + 3) / 4; - - for ( i = 0; i < count32b; i++, dest += 4 ) - { - *(__packed uint32_t *)dest = USBx_DFIFO(0); - - } - return ((void *)dest); -} - -/** - * @brief USB_EPSetStall : set a stall condition over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) -{ - if (ep->is_in == 1) - { - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0) - { - USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); - } - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; - } - else - { - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0) - { - USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); - } - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; - } - return HAL_OK; -} - - -/** - * @brief USB_EPClearStall : Clear a stall condition over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) -{ - if (ep->is_in == 1) - { - USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) - { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ - } - } - else - { - USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; - if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) - { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ - } - } - return HAL_OK; -} - -/** - * @brief USB_StopDevice : Stop the usb device mode - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t i; - - /* Clear Pending interrupt */ - for (i = 0; i < 15 ; i++) - { - USBx_INEP(i)->DIEPINT = 0xFF; - USBx_OUTEP(i)->DOEPINT = 0xFF; - } - USBx_DEVICE->DAINT = 0xFFFFFFFF; - - /* Clear interrupt masks */ - USBx_DEVICE->DIEPMSK = 0; - USBx_DEVICE->DOEPMSK = 0; - USBx_DEVICE->DAINTMSK = 0; - - /* Flush the FIFO */ - USB_FlushRxFifo(USBx); - USB_FlushTxFifo(USBx , 0x10 ); - - return HAL_OK; -} - -/** - * @brief USB_SetDevAddress : Stop the usb device mode - * @param USBx : Selected device - * @param address : new device address to be assigned - * This parameter can be a value from 0 to 255 - * @retval HAL status - */ -HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address) -{ - USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD); - USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ; - - return HAL_OK; -} - -/** - * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx) -{ - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ; - HAL_Delay(3); - - return HAL_OK; -} - -/** - * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) -{ - USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ; - HAL_Delay(3); - - return HAL_OK; -} - -/** - * @brief USB_ReadInterrupts: return the global USB interrupt status - * @param USBx : Selected device - * @retval HAL status - */ -uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t v = 0; - - v = USBx->GINTSTS; - v &= USBx->GINTMSK; - return v; -} - -/** - * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status - * @param USBx : Selected device - * @retval HAL status - */ -uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t v; - v = USBx_DEVICE->DAINT; - v &= USBx_DEVICE->DAINTMSK; - return ((v & 0xffff0000) >> 16); -} - -/** - * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status - * @param USBx : Selected device - * @retval HAL status - */ -uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t v; - v = USBx_DEVICE->DAINT; - v &= USBx_DEVICE->DAINTMSK; - return ((v & 0xFFFF)); -} - -/** - * @brief Returns Device OUT EP Interrupt register - * @param USBx : Selected device - * @param epnum : endpoint number - * This parameter can be a value from 0 to 15 - * @retval Device OUT EP Interrupt register - */ -uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) -{ - uint32_t v; - v = USBx_OUTEP(epnum)->DOEPINT; - v &= USBx_DEVICE->DOEPMSK; - return v; -} - -/** - * @brief Returns Device IN EP Interrupt register - * @param USBx : Selected device - * @param epnum : endpoint number - * This parameter can be a value from 0 to 15 - * @retval Device IN EP Interrupt register - */ -uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) -{ - uint32_t v, msk, emp; - - msk = USBx_DEVICE->DIEPMSK; - emp = USBx_DEVICE->DIEPEMPMSK; - msk |= ((emp >> epnum) & 0x1) << 7; - v = USBx_INEP(epnum)->DIEPINT & msk; - return v; -} - -/** - * @brief USB_ClearInterrupts: clear a USB interrupt - * @param USBx : Selected device - * @param interrupt : interrupt flag - * @retval None - */ -void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) -{ - USBx->GINTSTS |= interrupt; -} - -/** - * @brief Returns USB core mode - * @param USBx : Selected device - * @retval return core mode : Host or Device - * This parameter can be one of these values: - * 0 : Host - * 1 : Device - */ -uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) -{ - return ((USBx->GINTSTS ) & 0x1); -} - - -/** - * @brief Activate EP0 for Setup transactions - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) -{ - /* Set the MPS of the IN EP based on the enumeration speed */ - USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; - - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) - { - USBx_INEP(0)->DIEPCTL |= 3; - } - USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; - - return HAL_OK; -} - - -/** - * @brief Prepare the EP0 to start the first control setup - * @param USBx : Selected device - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @param psetup : pointer to setup packet - * @retval HAL status - */ -HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) -{ - USBx_OUTEP(0)->DOEPTSIZ = 0; - USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8); - USBx_OUTEP(0)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; - - if (dma == 1) - { - USBx_OUTEP(0)->DOEPDMA = (uint32_t)psetup; - /* EP enable */ - USBx_OUTEP(0)->DOEPCTL = 0x80008000; - } - - return HAL_OK; -} - - -/** - * @brief Reset the USB Core (needed after USB clock settings change) - * @param USBx : Selected device - * @retval HAL status - */ -static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t count = 0; - - /* Wait for AHB master IDLE state. */ - do - { - if (++count > 200000) - { - return HAL_TIMEOUT; - } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0); - - /* Core Soft Reset */ - count = 0; - USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; - - do - { - if (++count > 200000) - { - return HAL_TIMEOUT; - } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); - - return HAL_OK; -} - - -/** - * @brief USB_HostInit : Initializes the USB OTG controller registers - * for Host mode - * @param USBx : Selected device - * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) -{ - uint32_t i; - - /* Restart the Phy Clock */ - USBx_PCGCCTL = 0; - - /*Activate VBUS Sensing B */ - USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; - - /* Disable the FS/LS support mode only */ - if((cfg.speed == USB_OTG_SPEED_FULL)&& - (USBx != USB_OTG_FS)) - { - USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; - } - else - { - USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); - } - - /* Make sure the FIFOs are flushed. */ - USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */ - USB_FlushRxFifo(USBx); - - /* Clear all pending HC Interrupts */ - for (i = 0; i < cfg.Host_channels; i++) - { - USBx_HC(i)->HCINT = 0xFFFFFFFF; - USBx_HC(i)->HCINTMSK = 0; - } - - /* Enable VBUS driving */ - USB_DriveVbus(USBx, 1); - - HAL_Delay(200); - - /* Disable all interrupts. */ - USBx->GINTMSK = 0; - - /* Clear any pending interrupts */ - USBx->GINTSTS = 0xFFFFFFFF; - - if(USBx == USB_OTG_FS) - { - /* set Rx FIFO size */ - USBx->GRXFSIZ = (uint32_t )0x80; - USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80); - USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0); - } - else - { - /* set Rx FIFO size */ - USBx->GRXFSIZ = (uint32_t )0x200; - USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100 << 16)& USB_OTG_NPTXFD) | 0x200); - USBx->HPTXFSIZ = (uint32_t )(((0xE0 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0x300); - } - - /* Enable the common interrupts */ - if (cfg.dma_enable == DISABLE) - { - USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; - } - - /* Enable interrupts matching to the Host mode ONLY */ - USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\ - USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\ - USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); - - return HAL_OK; -} - -/** - * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the - * HCFG register on the PHY type and set the right frame interval - * @param USBx : Selected device - * @param freq : clock frequency - * This parameter can be one of these values: - * HCFG_48_MHZ : Full Speed 48 MHz Clock - * HCFG_6_MHZ : Low Speed 6 MHz Clock - * @retval HAL status - */ -HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq) -{ - USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); - USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS); - - if (freq == HCFG_48_MHZ) - { - USBx_HOST->HFIR = (uint32_t)48000; - } - else if (freq == HCFG_6_MHZ) - { - USBx_HOST->HFIR = (uint32_t)6000; - } - return HAL_OK; -} - -/** -* @brief USB_OTG_ResetPort : Reset Host Port - * @param USBx : Selected device - * @retval HAL status - * @note : (1)The application must wait at least 10 ms - * before clearing the reset bit. - */ -HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) -{ - __IO uint32_t hprt0; - - hprt0 = USBx_HPRT0; - - hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); - HAL_Delay (10); /* See Note #1 */ - USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); - return HAL_OK; -} - -/** - * @brief USB_DriveVbus : activate or de-activate vbus - * @param state : VBUS state - * This parameter can be one of these values: - * 0 : VBUS Active - * 1 : VBUS Inactive - * @retval HAL status -*/ -HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) -{ - __IO uint32_t hprt0; - - hprt0 = USBx_HPRT0; - hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 )) - { - USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); - } - if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 )) - { - USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); - } - return HAL_OK; -} - -/** - * @brief Return Host Core speed - * @param USBx : Selected device - * @retval speed : Host speed - * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_FULL: Full speed mode - * @arg USB_OTG_SPEED_LOW: Low speed mode - */ -uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx) -{ - __IO uint32_t hprt0; - - hprt0 = USBx_HPRT0; - return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); -} - -/** - * @brief Return Host Current Frame number - * @param USBx : Selected device - * @retval current frame number -*/ -uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx) -{ - return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); -} - -/** - * @brief Initialize a host channel - * @param USBx : Selected device - * @param ch_num : Channel number - * This parameter can be a value from 1 to 15 - * @param epnum : Endpoint number - * This parameter can be a value from 1 to 15 - * @param dev_address : Current device address - * This parameter can be a value from 0 to 255 - * @param speed : Current device speed - * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_FULL: Full speed mode - * @arg USB_OTG_SPEED_LOW: Low speed mode - * @param ep_type : Endpoint Type - * This parameter can be one of these values: - * @arg EP_TYPE_CTRL: Control type - * @arg EP_TYPE_ISOC: Isochronous type - * @arg EP_TYPE_BULK: Bulk type - * @arg EP_TYPE_INTR: Interrupt type - * @param mps : Max Packet Size - * This parameter can be a value from 0 to32K - * @retval HAL state - */ -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps) -{ - - /* Clear old interrupt conditions for this host channel. */ - USBx_HC(ch_num)->HCINT = 0xFFFFFFFF; - - /* Enable channel interrupts required for this transfer. */ - switch (ep_type) - { - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - - USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ - USB_OTG_HCINTMSK_STALLM |\ - USB_OTG_HCINTMSK_TXERRM |\ - USB_OTG_HCINTMSK_DTERRM |\ - USB_OTG_HCINTMSK_AHBERR |\ - USB_OTG_HCINTMSK_NAKM ; - - if (epnum & 0x80) - { - USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; - } - else - { - if(USBx != USB_OTG_FS) - { - USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); - } - } - break; - - case EP_TYPE_INTR: - - USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ - USB_OTG_HCINTMSK_STALLM |\ - USB_OTG_HCINTMSK_TXERRM |\ - USB_OTG_HCINTMSK_DTERRM |\ - USB_OTG_HCINTMSK_NAKM |\ - USB_OTG_HCINTMSK_AHBERR |\ - USB_OTG_HCINTMSK_FRMORM ; - - if (epnum & 0x80) - { - USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; - } - - break; - case EP_TYPE_ISOC: - - USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ - USB_OTG_HCINTMSK_ACKM |\ - USB_OTG_HCINTMSK_AHBERR |\ - USB_OTG_HCINTMSK_FRMORM ; - - if (epnum & 0x80) - { - USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); - } - break; - } - - /* Enable the top level host channel interrupt. */ - USBx_HOST->HAINTMSK |= (1 << ch_num); - - /* Make sure host channel interrupts are enabled. */ - USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; - - /* Program the HCCHAR register */ - USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD) |\ - (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\ - ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\ - (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\ - ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\ - (mps & USB_OTG_HCCHAR_MPSIZ)); - - if (ep_type == EP_TYPE_INTR) - { - USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; - } - - return HAL_OK; -} - -/** - * @brief Start a transfer over a host channel - * @param USBx : Selected device - * @param hc : pointer to host channel structure - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL state - */ -#if defined (__CC_ARM) /*!< ARM Compiler */ -#pragma O0 -#elif defined (__GNUC__) /*!< GNU Compiler */ -#pragma GCC optimize ("O0") -#endif /* __CC_ARM */ -HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) -{ - uint8_t is_oddframe = 0; - uint16_t len_words = 0; - uint16_t num_packets = 0; - uint16_t max_hc_pkt_count = 256; - uint32_t tmpreg = 0; - - if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH)) - { - if((dma == 0) && (hc->do_ping == 1)) - { - USB_DoPing(USBx, hc->ch_num); - return HAL_OK; - } - else if(dma == 1) - { - USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); - hc->do_ping = 0; - } - } - - /* Compute the expected number of packets associated to the transfer */ - if (hc->xfer_len > 0) - { - num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet; - - if (num_packets > max_hc_pkt_count) - { - num_packets = max_hc_pkt_count; - hc->xfer_len = num_packets * hc->max_packet; - } - } - else - { - num_packets = 1; - } - if (hc->ep_is_in) - { - hc->xfer_len = num_packets * hc->max_packet; - } - - /* Initialize the HCTSIZn register */ - USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\ - ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ - (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID); - - if (dma) - { - /* xfer_buff MUST be 32-bits aligned */ - USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff; - } - - is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1; - USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; - USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29); - - /* Set host channel enable */ - tmpreg = USBx_HC(hc->ch_num)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hc->ch_num)->HCCHAR = tmpreg; - - if (dma == 0) /* Slave mode */ - { - if((hc->ep_is_in == 0) && (hc->xfer_len > 0)) - { - switch(hc->ep_type) - { - /* Non periodic transfer */ - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - - len_words = (hc->xfer_len + 3) / 4; - - /* check if there is enough space in FIFO space */ - if(len_words > (USBx->HNPTXSTS & 0xFFFF)) - { - /* need to process data in nptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; - } - break; - /* Periodic transfer */ - case EP_TYPE_INTR: - case EP_TYPE_ISOC: - len_words = (hc->xfer_len + 3) / 4; - /* check if there is enough space in FIFO space */ - if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */ - { - /* need to process data in ptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; - } - break; - - default: - break; - } - - /* Write packet into the Tx FIFO. */ - USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0); - } - } - - return HAL_OK; -} - -/** - * @brief Read all host channel interrupts status - * @param USBx : Selected device - * @retval HAL state - */ -uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx) -{ - return ((USBx_HOST->HAINT) & 0xFFFF); -} - -/** - * @brief Halt a host channel - * @param USBx : Selected device - * @param hc_num : Host Channel number - * This parameter can be a value from 1 to 15 - * @retval HAL state - */ -HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) -{ - uint32_t count = 0; - - /* Check for space in the request queue to issue the halt. */ - if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18))) - { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - - if ((USBx->HNPTXSTS & 0xFFFF) == 0) - { - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; - do - { - if (++count > 1000) - { - break; - } - } - while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); - } - else - { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - } - } - else - { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - - if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0) - { - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; - do - { - if (++count > 1000) - { - break; - } - } - while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); - } - else - { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - } - } - - return HAL_OK; -} - -/** - * @brief Initiate Do Ping protocol - * @param USBx : Selected device - * @param hc_num : Host Channel number - * This parameter can be a value from 1 to 15 - * @retval HAL state - */ -HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num) -{ - uint8_t num_packets = 1; - uint32_t tmpreg = 0; - - USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ - USB_OTG_HCTSIZ_DOPING; - - /* Set host channel enable */ - tmpreg = USBx_HC(ch_num)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; - - return HAL_OK; -} - -/** - * @brief Stop Host Core - * @param USBx : Selected device - * @retval HAL state - */ -HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) -{ - uint8_t i; - uint32_t count = 0; - uint32_t value; - - USB_DisableGlobalInt(USBx); - - /* Flush FIFO */ - USB_FlushTxFifo(USBx, 0x10); - USB_FlushRxFifo(USBx); - - /* Flush out any leftover queued requests. */ - for (i = 0; i <= 15; i++) - { - - value = USBx_HC(i)->HCCHAR ; - value |= USB_OTG_HCCHAR_CHDIS; - value &= ~USB_OTG_HCCHAR_CHENA; - value &= ~USB_OTG_HCCHAR_EPDIR; - USBx_HC(i)->HCCHAR = value; - } - - /* Halt all channels to put them into a known state. */ - for (i = 0; i <= 15; i++) - { - value = USBx_HC(i)->HCCHAR ; - - value |= USB_OTG_HCCHAR_CHDIS; - value |= USB_OTG_HCCHAR_CHENA; - value &= ~USB_OTG_HCCHAR_EPDIR; - - USBx_HC(i)->HCCHAR = value; - do - { - if (++count > 1000) - { - break; - } - } - while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); - } - - /* Clear any pending Host interrupts */ - USBx_HOST->HAINT = 0xFFFFFFFF; - USBx->GINTSTS = 0xFFFFFFFF; - USB_EnableGlobalInt(USBx); - return HAL_OK; -} -/** - * @} - */ - -#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/com/lib/lib.mk b/int/com/lib/lib.mk deleted file mode 100644 index dd76f55..0000000 --- a/int/com/lib/lib.mk +++ /dev/null @@ -1,93 +0,0 @@ -# common make include for libraries - -reverse = $(if $(wordlist 2,2,$(1)),$(call reverse,$(wordlist 2,$(words $(1)),$(1))) $(firstword $(1)),$(1)) - -LIB_OUT := ../$(PJDIR)/$(ARDIR)/$(LIBNAME) -OBJ_OUT := ../$(PJDIR)/$(OBJDIR)/$(LIBNAME:.a=) - -CFLAGS := $(patsubst -I%,-I../$(PJDIR)/%,$(CFLAGS)) -ASFLAGS := $(patsubst -I%,-I../$(PJDIR)/%,$(ASFLAGS)) - -SRCS_CC := $(filter-out %template.c,$(SRCS_C)) -SRCS_CC := $(filter-out $(LIB_EXCL),$(SRCS_CC)) - -OBJSC := $(patsubst %.c,%.o,$(SRCS_CC)) -OBJSC := $(patsubst %,$(OBJ_OUT)/%,$(OBJSC)) - -OBJSS := $(patsubst %.s,%.o,$(SRCS_S)) -OBJSS := $(patsubst %,$(OBJ_OUT)/%,$(OBJSS)) - -DEP := ../$(PJDIR)/$(ARDIR)/$(LIBNAME:.a=.d) -DEP1 := ../$(PJDIR)/$(ARDIR)/$(LIBNAME:.a=.d.d) -#DEP2 := ../$(PJDIR)/$(ARDIR)/$(LIBNAME:.a=.d.d.d) -SRCS = $(SRCS_C) $(SRCS_S) -#OBJS = $(call reverse, $(sort $(OBJSC) $(OBJSS))) -#OBJS = $(sort $(OBJSC) $(OBJSS)) -OBJS = $(OBJSC) $(OBJSS) - -#test1: -# @echo $(LIB_OBJS) -# @echo $(SRCS_C) -# @echo $(SRCS_S) - -.PHONY: all - -all: $(LIB_OUT) - @touch $(LIB_OUT) - -zz: - @echo $(OBJ_OUT) - @echo $(LIB_OUT) - @echo $(SRCS) - @echo $(OBJS) - -$(LIB_OUT): $(OBJS) - @echo ar $@ - @$(AR) $(ARFLAGS) $@ $^ -# @echo $(LIB_OUT) - @cat $(OBJS:.o=.d) \ - | sed -e 's/.*://' -e 's/\\$$//' \ - | fmt -1 | sort | uniq \ - | sed -e 's,^ \([^.]\), '../$(PJDIR)/$(LIBDIR)/'\1,' \ - | sed -n 's,'../$(PJDIR)/',,p' \ - | sed -e 's/$$/ \\/' -e '$$ s/\\$$//' -e '1 i '$(ARDIR)/$(LIBNAME)': \\' \ - > $(DEP) - -.PHONY: clean -clean: - @-rm -f $(OBJS) $(OBJS:.o=.d) $(LIB_OUT) $(DEP) $(DEP1) $(DEP2) - -#depend dep: $(DEP) - -#$(DEP): Src/*.c -# $(CCDEP) $(CFLAGS) -MM $^ | sed -e 's@.*.o:@Src/&@' > $(DEP) - -#$(DEP): $(LIB_SRCS_C) -# $(CCDEP) $(CFLAGS) -MM $^ > $(DEP) - -#$(DEP): $(SRCS) -# @rm -f $(DEP) -# @$(foreach SRC,$(SRCS_S),echo dep $(SRC); $(CCDEP) $(CFLAGS) -MM -MT $(OBJ_OUT)/$(SRC:.s=.o) $(SRC) >> $(DEP) || { rm $(DEP); exit 1; };) -# @$(foreach SRC,$(SRCS_C),echo dep $(SRC); $(CCDEP) $(CFLAGS) -MM -MT $(OBJ_OUT)/$(SRC:.c=.o) $(SRC) >> $(DEP) || { rm $(DEP); exit 1; };) - -#.c.o: -$(OBJSC): $(OBJ_OUT)/%.o: %.c - @mkdir -p $(dir $@) -# @echo cc \[$(PJNAME): $(LIBNAME)\] $< -ifeq ($(SHOWPJ),1) - @echo cc \[$(PJNAME)\] $< -else - @echo cc $< -endif -# @echo $(CFLAGS) - @$(CC) $(CFLAGS) -MMD -c -o $@ $< - -#.s.o: -$(OBJSS): $(OBJ_OUT)/%.o: %.s - @mkdir -p $(dir $@) - @echo as $< - @$(AS) $(ASFLAGS) -MMD -c -o $@ $< - --include $(OBJS:.o=.d) -#-include $(DEP) - diff --git a/int/com/lib/libstm32f7xxhal.mk b/int/com/lib/libstm32f7xxhal.mk deleted file mode 100644 index a8824f8..0000000 --- a/int/com/lib/libstm32f7xxhal.mk +++ /dev/null @@ -1,39 +0,0 @@ -# Compile the STM32F7xx HAL Driver Library - -LIBN := libstm32f7xxhal.a -LIBD := STM32F7xx_HAL_Driver -LIBP := fw - -# this part is to be included at the top of the project Makefile -ifeq '$(INCLIBS)' 'inc' - -$(info including $(LIBN)) - -LIBS += $(ARDIR)/$(LIBN) -LIBDIRS += $(LIBDIR)/$(LIBD) -PORTDIRS += $(PORTDIR)/$(LIBP) -LIBS_OPT += -DUSE_HAL_DRIVER -SRCS_ADD += $(LIBDIR)/CMSIS-hal/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c - -INC += $(LIBDIR)/$(LIBD)/Inc -INC += $(PORTDIR)/$(LIBP) - -endif - -#this part is to be called to build the lib -ifeq '$(INCLIBS)' 'mk' -export -#$(info making $(LIBN)) - -LIBNAME := $(LIBN) - -SRCS_C := $(wildcard $(LIBD)/Src/*.c) -SRCS_S := $(wildcard $(LIBD)/Src/*.s) - -include lib.mk - -endif - -LIBN := -LIBD := -LIBP := diff --git a/int/com/pj/cube-hal-dma.awk b/int/com/pj/cube-hal-dma.awk deleted file mode 100644 index 27960c9..0000000 --- a/int/com/pj/cube-hal-dma.awk +++ /dev/null @@ -1,33 +0,0 @@ -/hdma.*Instance/ { - b=$3; - a=$1; - sub("hdma_","",a); - sub(".Instance","",a); - a=toupper(a); - sub("UART","USART",a); - sub(";","",b); - sub(" ","",b); - printf("#define DMA_IRQ_%s %s_IRQHandler\n",a,b); - split(b,c,"_"); - d1 = substr(c[1], 1, length(c[1])-1); - n1 = substr(c[1], length(c[1]), 1); - d2 = substr(c[2], 1, length(c[2])-1); - n2 = substr(c[2], length(c[2]), 1); - if (d2 = "Stream") { - printf("#ifdef DMAv2\n"); - if (n2 <= 3) { - printf("#define TCIF_%s ((DMA%s->LISR & DMA_LISR_TCIF%d)!=0)\n",a,n1,n2); - printf("#define CTCIF_%s (DMA%s->LIFCR |= DMA_LIFCR_CTCIF%d)\n",a,n1,n2); - } else { - printf("#define TCIF_%s ((DMA%s->HISR & DMA_HISR_TCIF%d)!=0)\n",a,n1,n2); - printf("#define CTCIF_%s (DMA%s->HIFCR |= DMA_HIFCR_CTCIF%d)\n",a,n1,n2); - } - printf("#endif\n"); - printf("#ifdef DMAv1\n"); - printf("#define TCIF_%s ((DMA%s->ISR & DMA_ISR_TCIF%d)!=0)\n",a,n1,n2); - printf("#define CTCIF_%s (DMA%s->IFCR |= DMA_IFCR_CTCIF%d)\n",a,n1,n2); - printf("#endif\n"); - - }; - printf("\n"); -} diff --git a/int/com/pj/cube-hal.mk b/int/com/pj/cube-hal.mk deleted file mode 100644 index 53c4d02..0000000 --- a/int/com/pj/cube-hal.mk +++ /dev/null @@ -1,76 +0,0 @@ -INC += $(CUBEDIR)/$(PJNAME)/Inc -#CSRCDIRS += $(CUBEDIR)/$(PJNAME)/Src - -C_ISR_NAME := $(notdir $(wildcard $(CUBEDIR)/$(PJNAME)/Src/stm*it.c)) -C_ISR_FILE := $(CUBEDIR)/$(PJNAME)/Src/cube_$(C_ISR_NAME) -C_MAIN_FILE := $(CUBEDIR)/$(PJNAME)/Src/cube_main.c -C_DMA_FILE := $(CUBEDIR)/$(PJNAME)/Inc/cube_dma.h -ifeq ($(CHIBIOS_PORT),) -C_IRQH_FILE := -else -C_IRQH_FILE := $(CUBEDIR)/$(PJNAME)/Inc/$(CHIBIOS_PORT)-irqs.h -endif -C_AWK_DMA := $(COMDIR)/pj/cube-hal-dma.awk -C_AWK_IRQ := $(COMDIR)/pj/cube-hal-irqs.awk - -CLEAN_ADD += $(C_ISR_FILE) $(C_MAIN_FILE) $(C_DMA_FILE) $(C_IRQH_FILE) -GEN_ADD += $(C_ISR_FILE) $(C_MAIN_FILE) $(C_DMA_FILE) $(C_IRQH_FILE) -SRCS_ADD += $(patsubst %_it.c,, $(patsubst %main.c,, $(wildcard $(CUBEDIR)/$(PJNAME)/Src/*.c))) -SRCS_ADD += $(C_MAIN_FILE) $(C_ISR_FILE) -C_DEPS += $(C_DMA_FILE) -FILES_ADD += $(C_AWK_DMA) - -$(C_MAIN_FILE): $(CUBEDIR)/$(PJNAME)/Src/main.c - @echo gen $@ -# @echo generate $(C_MAIN_FILE) calling main1\(\) -ifeq ($(CHIBIOS_PORT),) - @cat $< \ - | sed -e '/USER CODE END PFP/ i void main1\(void\);' \ - | sed -e '/USER CODE BEGIN WHILE/ i main1();' \ - | sed -e '/int main(void)/ i __weak' \ - > $@ -else - @cat $< \ - | sed -e '/USER CODE END PFP/ i void main1\(void\);' \ - | sed -e '/USER CODE BEGIN WHILE/ i main1();' \ - | sed -e '/int main(void)/ i __weak' \ - | sed -e 's/SCB_EnableICache()/\/\/removed by cube-hal.mk/' \ - | sed -e 's/SCB_EnableDCache()/\/\/removed by cube-hal.mk/' \ - > $@ -endif - -ifeq ($(CHIBIOS_PORT),) -else -FILES_ADD += $(C_AWK_IRQ) -$(C_ISR_FILE): $(C_IRQH_FILE) - -$(C_IRQH_FILE): $(C_AWK_IRQ) $(CHIBIOS_IRQ_S_FILE) -ifeq ($(CHIBIOS_IRQ_S_FILE),) - @echo missing startup_stm32xx.s file && false - -endif - @echo gen $@ - @test -f $(CHIBIOS_IRQ_S_FILE) && cat $(CHIBIOS_IRQ_S_FILE) \ - |sed -e 's/\r$///' | gawk -f $(C_AWK_IRQ) \ - > $@ -endif - -$(C_ISR_FILE): $(CUBEDIR)/$(PJNAME)/Src/$(C_ISR_NAME) - @echo gen $@ -# @echo generate $(C_ISR_FILE) declaring ISRs as weak symbols -ifeq ($(CHIBIOS_PORT),) - @cat $< \ - | sed -e '/IRQHandler(void)/ i __weak' \ - > $@ -else - @cat $< \ - | sed -e '/USER CODE END 0/ i #include "$(CHIBIOS_PORT)-irqs.h"' \ - | sed -e '/Handler(void)/ i __weak' \ - > $@ -endif - -$(C_DMA_FILE): $(CUBEDIR)/$(PJNAME)/Src/main.c $(C_AWK_DMA) - @echo gen $@ -# @echo generate $(C_DMA_FILE) - @cat $(CUBEDIR)/$(PJNAME)/Src/*.c \ - | gawk -f $(C_AWK_DMA) \ - > $(C_DMA_FILE) diff --git a/int/com/pj/f767-nucleo-hal.mk b/int/com/pj/f767-nucleo-hal.mk deleted file mode 100644 index 57a6c16..0000000 --- a/int/com/pj/f767-nucleo-hal.mk +++ /dev/null @@ -1,22 +0,0 @@ -DEVICE_FAMILY := STM32F7xx -DEVICE_TYPE := STM32F767xx -STARTUP_FILE := stm32f767xx -SYSTEM_FILE := stm32f7xx -LDSCRIPT := stm32f767xi.ld - -CMSIS = $(LIBDIR)/CMSIS-hal -CMSIS_DEVSUP = $(CMSIS)/Device/ST/$(DEVICE_FAMILY) -CMSIS_CORESUP = $(CMSIS)/Include -CMSIS_OPT = -D$(DEVICE_TYPE) -GCC_OPT = -Wall -fno-common -fno-strict-aliasing -Wfatal-errors -CPU_OPT = -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 - -INC := $(INCDIR) -INC += $(CMSIS_DEVSUP)/Include $(CMSIS_CORESUP) - -STARTUP_SRC = $(CMSIS_DEVSUP)/Source/Templates/gcc/startup_$(STARTUP_FILE).s -STARTUP_OBJ = $(OBJ_OUT)/startup_$(STARTUP_FILE).o -#SYSTEM_SRC = $(CMSIS_DEVSUP)/Source/Templates/system_$(SYSTEM_FILE).c -#SYSTEM_OBJ = $(OBJ_OUT)/system_$(SYSTEM_FILE).o - -include $(CSRCDIR)/stm-common.mk diff --git a/int/com/pj/oocd-stm32f7xx.mk b/int/com/pj/oocd-stm32f7xx.mk deleted file mode 100644 index 62f9837..0000000 --- a/int/com/pj/oocd-stm32f7xx.mk +++ /dev/null @@ -1,27 +0,0 @@ -OCD = @echo "set OCD in project makefile" - -OCD-jlink := openocd -f interface/jlink.cfg -f target/stm32f7x.cfg -OCD-vsllink := openocd -f interface/vsllink.cfg -c "transport select jtag" -f target/stm32f7x.cfg -OCD-arm-usb-ocd := openocd -f interface/ftdi/olimex-arm-usb-ocd.cfg -f target/stm32f7x.cfg -OCD-stlink := openocd -f interface/stlink-v2.cfg -c "transport select hla_swd" -f target/stm32f7x.cfg -OCD-discovery := openocd -f board/stm32f7discovery.cfg -OCD-nucleo := openocd -f interface/stlink-v2-1.cfg -c "transport select hla_swd" -f target/stm32f7x.cfg - -OCD_RESET = $(OCD) -c init -c "reset run" -c shutdown -OCD_FLASH = $(OCD) -c init -c "reset halt" \ - -c "flash write_image erase "$(BIN)" 0x08000000" \ - -c "reset run" \ - -c shutdown - -OCD_ZFLASH = $(OCD) -c init -c "reset halt" \ - -c "flash write_image erase "$(BINZ)" $(ZSTRT)" \ - -c "reset run" \ - -c shutdown - -OCD_FFLASH = $(OCD) -c init -c "reset halt" \ - -c "flash write_image erase "$(BIN)" $(FSTRT)" \ - -c "reset run" \ - -c shutdown - -#OCD_GDB = $(OCD) -c "{stm32f7x}.cpu configure -rtos auto;" -OCD_GDB = $(OCD) diff --git a/int/com/pj/pj.mk b/int/com/pj/pj.mk deleted file mode 100644 index 1f21a67..0000000 --- a/int/com/pj/pj.mk +++ /dev/null @@ -1,243 +0,0 @@ -#Common makefile include for all projectes - -ifeq ($(SPECS),none) - SPECS := -else -ifeq ($(SPECS),) - SPECS := -specs=nano.specs -endif -endif - -ifeq ($(SYSTEM),) -S_GCC := -ifeq ($(S_GCC),) -SYSTEM := $(shell ls -rd /usr/local/gcc-arm-none-eabi-* 2>/dev/null |head -n 1)/bin/arm-none-eabi -S_GCC := $(shell which $(SYSTEM)-gcc 2>/dev/null) -endif -ifeq ($(S_GCC),) -SYSTEM := arm-none-eabi -S_GCC := $(shell which $(SYSTEM)-gcc 2>/dev/null) -endif -ifeq ($(S_GCC),) -SYSTEM := echo "arm-none-eabi toolchain not found "; false - -S_GCC := -endif -$(info using gcc: $(S_GCC) ) -endif - -SRCS_C += $(SRCS_ADD) -SRCS_C += $(wildcard $(patsubst %,%/*.c,$(PORTDIRS))) -SRCS_C += $(wildcard $(patsubst %,%/*.c,$(CSRCDIRS))) -SRCS_C += $(LIBSRCS) -VPATH := $(COMDIR) - -GLBL_GCC = -ffunction-sections -fdata-sections -fmessage-length=0 -CFLAGS1 = $(CPU_OPT) $(CMSIS_OPT) $(OTHER_OPT) $(LIBS_OPT) $(GCC_OPT) $(OPTIMIZE) $(GLBL_GCC) -CFLAGS = $(CFLAGS1) $(patsubst %,-I%,$(INC)) -ASFLAGS = $(CFLAGS) -x assembler-with-cpp -LDFLAGS = $(CFLAGS1) $(SPECS) -Wl,--gc-sections,-Map=$(MAP),-cref$(LDOPT) -T $(LDDIR)/$(LDSCRIPT) $(patsubst %,-L%,$(LDINC)) -ARFLAGS = cr -OBJCOPYBIN = -Obinary -OBJCOPYHEX = -Oihex -OBJCOPYS19 = -Osrec -OBJDUMPFLAGS = -S - -CC = $(SYSTEM)-gcc -CCDEP = $(SYSTEM)-gcc -LD = $(SYSTEM)-gcc -AR = $(SYSTEM)-ar -AS = $(SYSTEM)-gcc -OBJCOPY = $(SYSTEM)-objcopy -OBJDUMP = $(SYSTEM)-objdump -SIZE = $(SYSTEM)-size -GDB = $(SYSTEM)-gdb - -OBJ_OUT = $(OBJDIR) - -OUT = $(PJNAME).out -BIN = $(PJNAME).bin -BINZ = $(PJNAME).bin.gz -LST = $(PJNAME).list -HEX = $(PJNAME).hex -S19 = $(PJNAME).s19 -MAP = $(PJNAME).map -DEP = $(PJNAME).d - -OBJSC := $(patsubst %.c,%.o,$(SRCS_C)) -OBJSC := $(patsubst $(COMDIR)/%,%,$(OBJSC)) -OBJSC := $(patsubst %,$(OBJ_OUT)/%,$(OBJSC)) -#OBJSC := $(abspath $(OBJSC)) - -OBJSS := $(patsubst %.s,%.o,$(SRCS_S)) -OBJSS := $(patsubst $(COMDIR)/%,%,$(OBJSS)) -OBJSS := $(patsubst %,$(OBJ_OUT)/%,$(OBJSS)) -#OBJSS := $(abspath $(OBJSS)) - -SRCS = $(SRCS_C) $(SRCS_S) -OBJS = $(OBJSC) $(OBJSS) $(STARTUP_OBJ) $(SYSTEM_OBJ) - -info: - $(info using cc toolchain : $(SYSTEM)) - $(info project export to : $(EXPDIR)/$(PJNAME)) - $(info using cc options : $(CFLAGS)) -# $(info using as options : $(ASFLAGS)) - $(info using ld options : $(LDFLAGS)) - $(info objects to build : $(OBJS)) - $(info archives to build : $(LIBS)) - $(info sources : $(SRCS)) -# $(info c sources : $(SRCS_C)) -# @$(CC) --version - -all: $(BIN) - -ifeq '$(BL)' '-bl1' -#all: $(BINZ) -endif - -ifeq '$(BL)' '-bl' -#all: $(S19) -endif - -filelist: $(OUT) - make --debug=v |grep -E "(Prerequisite )|(makefile )" |sed -e s/\`/\'/ |cut -d "'" -f 2 |sort |uniq |grep -v -E "([.][ado])|([.]out)\$$" >filelist - -test -d cube && find cube/ -iname "*.ioc" >>filelist - @echo $(FILES_ADD) >>filelist - -pjexport: filelist - -mkdir -p $(EXPDIR)/$(PJNAME) - -mkdir -p $(EXPDIR)/$(PJNAME)/a - -mkdir -p $(EXPDIR)/$(PJNAME)/o - cp -v --parents `cat filelist` ../Makefile $(EXPDIR)/$(PJNAME) - -reset: - $(OCD_RESET) - -ifeq '$(BL)' '-bl1' -flashz: $(BINZ) - $(OCD_ZFLASH) - -flash: $(BIN) - $(OCD_FFLASH) - -else -ifeq '$(BL)' '-bl' -flash: $(BIN) $(HEX) - $(BLTCS) -i $(BIN) -o $(BIN).out - $(OCD_BFLASH) - -else -flash: $(BIN) $(HEX) - $(OCD_FLASH) -endif -endif - -gdb: - $(OCD_GDB) - -ifeq '$(BL)' '-bl' -boot: $(S19) $(BLTCMD) - $(BLT) $(S19) -endif - -$(HEX): $(OUT) - @echo objcopy $(HEX) - @$(OBJCOPY) $(OBJCOPYHEX) $(OUT) $(HEX) - -$(S19): $(BIN) $(BLTCS) - $(BLTCS) -i $(BIN) -o $(BIN).out - $(SREC) $(BIN).out -binary -offset $(VTOR_INIT) -o $(S19) - $(SREC_INFO) $(S19) - -rm -f $(BIN).out - -$(BIN): $(OUT) - @echo objcopy $(BIN) - @$(OBJCOPY) $(OBJCOPYBIN) $(OUT) $(BIN) - @echo objdump $(LST) - @$(OBJDUMP) $(OBJDUMPFLAGS) $(OUT) > $(LST) - @echo size $(OUT) - @$(SIZE) $(OUT) -ifeq '$(BL)' '-bl1' - @echo gzip $(BIN) - @gzip -c $(BIN) >$(BINZ) -endif - @echo Make finished - -#$(BINZ): $(BIN) -# @echo gzip $(BIN) -# @gzip -c $(BIN) >$(BINZ) - -$(OUT): $(GEN_ADD) $(LIBS) $(OBJS) $(LDDIR)/$(LDSCRIPT) - @echo ld $@ -# @echo $(LD) $(LDFLAGS) -o $@ - @$(LD) $(LDFLAGS) -o $@ $(OBJS) -Wl,--start-group,--whole-archive $(LIBS) -Wl,--end-group,--no-whole-archive $(STDLIBS) - -#$(LIBS): -# ${MAKE} -C $@ -# @$(foreach LIB,$(LIBDIRS),${MAKE} -C $(LIB) || exit 1;) - --include $(LIBS:.a=.d) - -gen: clean-gen $(GEN_ADD) - -clean: - @-rm -f $(OBJS) $(OBJS:.o=.d) $(OBJS:.o=.sl) $(OUT) $(BIN) $(BINZ) $(HEX) $(S19) $(LST) $(MAP) $(DEP) $(CLEAN_ADD) - @$(foreach LIB,$(LIBS),${MAKE} -s -C $(LIBDIR) -f $(patsubst $(ARDIR)/%.a,%.mk,$(LIB)) clean || exit 1;) - @-rm -f jlink.reset jlink.flash filelist - -clean-nl: - @-rm -f $(OBJS) $(OBJS:.o=.d) $(OBJS:.o=.sl) $(OUT) $(BIN) $(BINZ) $(HEX) $(S19) $(LST) $(MAP) $(DEP) -# @$(foreach LIB,$(LIBS),${MAKE} -s -C $(LIBDIR) -f $(patsubst $(ARDIR)/%.a,%.mk,$(LIB)) clean || exit 1;) - @-rm -f jlink.reset jlink.flash filelist - -clean-add: - @-rm -f $(CLEAN_ADD) - -clean-gen: - @-rm -f $(GEN_ADD) - -depend dep: $(DEP) - -#$(DEP): Src/*.c -# $(CCDEP) $(CFLAGS) -MM $^ | sed -e 's@.*.o:@Src/&@' > $(DEP) - -#$(DEP): $(LIB_SRCS_C) -# $(CCDEP) $(CFLAGS) -MM $^ > $(DEP) - -#$(DEP): $(SRCS) -# @rm -f $(DEP) -# @$(foreach SRC,$(SRCS_S),echo dep $(SRC); $(CCDEP) $(CFLAGS) -MM -MT $(OBJ_OUT)/$(SRC:.s=.o) $(SRC) >> $(DEP);) -# @$(foreach SRC,$(SRCS_C),echo dep $(SRC); $(CCDEP) $(CFLAGS) -MM -MT $(OBJ_OUT)/$(SRC:.c=.o) $(SRC) >> $(DEP);) - -$(LIBS): %.a: - @-mkdir -p a - ${MAKE} -C $(LIBDIR) -f $(patsubst $(ARDIR)/%,%,$*).mk - -$(SYSTEM_OBJ): $(SYSTEM_SRC) - @echo cc $< - @$(CC) $(CFLAGS) -MMD -c -o $@ $< - -$(STARTUP_OBJ): $(STARTUP_SRC) - @echo as $< - @$(AS) $(CFLAGS) -MMD -c -o $@ $< - -$(OBJSC): $(OBJ_OUT)/%.o: %.c - @mkdir -p $(dir $@) -ifeq ($(SHOWPJ),1) - @echo cc \[$(PJNAME)\] $< -else - @echo cc $< -endif -# @echo $(CFLAGS) - @$(CC) $(CFLAGS) -MMD -c -o $@ -Wa,-adhln=$(@:.o=.sl) $< -# @$(CC) $(CFLAGS) --save-temps -MMD -c -o $@ $< -# @$(CC) $(CFLAGS) -MMD -c -o $@ $< - -$(OBJSS): $(OBJ_OUT)/%.o: %.s - @mkdir -p $(dir $@) - @echo as $< - @$(AS) $(ASFLAGS) -MMD -c -o $@ $< - --include $(OBJS:.o=.d) -#-include $(DEP) - -$(OBJS) $(LIBS): Makefile $(COMDIR)/pj/pjhdr.mk $(COMDIR)/pj/pj.mk $(COMDIR)/lib/lib.mk diff --git a/int/com/pj/pjhdr.mk b/int/com/pj/pjhdr.mk deleted file mode 100644 index 8473b25..0000000 --- a/int/com/pj/pjhdr.mk +++ /dev/null @@ -1,41 +0,0 @@ -ZZZ := $(shell rm -fv cln) - -ifeq ($(AUTOJ),1) -CORES := $(shell expr `grep -c ^processor /proc/cpuinfo` + 1) -NUMJOBS := -j $(CORES) -MAKEFLAGS += $(NUMJOBS) -endif - -#$(info $(CORES)) - -PJNAME := $(notdir $(CURDIR)) -PJDIR := ../$(notdir $(CURDIR)) - -ifeq ($(EXPDIR),) -EXPDIR := ../../export -endif - -OBJDIR := o -ARDIR := a -SRCDIR := src -INCDIR := inc -LDDIR := $(COMDIR)/ld -LDINC := -LDOPT := -LIBDIR := $(COMDIR)/lib -CSRCDIR := $(COMDIR)/src -PORTDIR := port -CUBEDIR := cube - -LIBS := -LIBDIRS := -LIBSRCS := -PORTDIRS := -CSRCDIRS := -LIBS_OPT := -SRCS_ADD := -CLEAN_ADD := - -current_mk = $(patsubst %.mk,%, $(notdir $(lastword $(MAKEFILE_LIST)))) - -.phony all: diff --git a/int/com/src/stm-common.mk b/int/com/src/stm-common.mk deleted file mode 100644 index 288183f..0000000 --- a/int/com/src/stm-common.mk +++ /dev/null @@ -1,5 +0,0 @@ -CSRCD := $(call current_mk) - -#$(info including $(CSRCD)) - -INC += $(CSRCDIR)/$(CSRCD) diff --git a/int/com/src/syscalls.mk b/int/com/src/syscalls.mk deleted file mode 100755 index 9fe845f..0000000 --- a/int/com/src/syscalls.mk +++ /dev/null @@ -1,11 +0,0 @@ -CSRCD := $(call current_mk) -#CSRCD := syscalls - -ifeq '$(INCLIBS)' 'src' - -$(info including $(CSRCD)) - -INC += $(CSRCDIR)/$(CSRCD) -CSRCDIRS += $(CSRCDIR)/$(CSRCD) - -endif diff --git a/int/com/src/syscalls/syscalls.c b/int/com/src/syscalls/syscalls.c deleted file mode 100755 index b553401..0000000 --- a/int/com/src/syscalls/syscalls.c +++ /dev/null @@ -1,180 +0,0 @@ -/***********************************************************************/ -/* */ -/* SYSCALLS.C: System Calls for the newlib */ -/* most of this is from newlib-lpc and a Keil-demo */ -/* */ -/* These are "reentrant functions" as needed by */ -/* the WinARM-newlib-config, see newlib-manual. */ -/* Collected and modified by Martin Thomas */ -/* */ -/***********************************************************************/ - - -#include -#include -#include -#include - -_ssize_t _read_r( - struct _reent *r, - int file, - void *ptr, - size_t len) -{ - /* - unsigned char *p; - while ( AT91F_US_RxReady((AT91PS_USART)AT91C_BASE_DBGU) == 0 ) { - ; - } - - p = ptr; - - *p= AT91F_US_GetChar((AT91PS_USART)AT91C_BASE_DBGU); - */ - return (_ssize_t)1; -} - - -_ssize_t _write_r ( - struct _reent *r, - int file, - const void *ptr, - size_t len) -{ - /* - size_t todo; - const unsigned char *p; - - todo = len; - p = ptr; - - for( ; todo != 0; todo--) { - if ( *p == '\n' ) { - while (!AT91F_US_TxReady((AT91PS_USART)AT91C_BASE_DBGU)) { - ; - } - AT91F_US_PutChar((AT91PS_USART)AT91C_BASE_DBGU, '\r'); - } - while (!AT91F_US_TxReady((AT91PS_USART)AT91C_BASE_DBGU)) { - ; - } - AT91F_US_PutChar((AT91PS_USART)AT91C_BASE_DBGU, *p++); - } - */ - return (_ssize_t)len; // Number of bytes written. -} - - -int _close_r( - struct _reent *r, - int file) -{ - return 0; -} - - -_off_t _lseek_r( - struct _reent *r, - int file, - _off_t ptr, - int dir) -{ - return (_off_t)0; /* Always indicate we are at file beginning. */ -} - - -int _fstat_r( - struct _reent *r, - int file, - struct stat *st) -{ - /* Always set as character device. */ - st->st_mode = S_IFCHR; - /* assigned to strong type with implicit */ - /* signed/unsigned conversion. Required by */ - /* newlib. */ - - return 0; -} - - -int _isatty(int file); /* avoid warning */ - -int _isatty(int file) -{ - return 1; -} - -void abort(void) -{ - while(1); -} - -#if 0 -static void _exit (int n) { -label: goto label; /* endless loop */ -} -#endif - - -#ifdef USE_CHIBIOS - -void * _sbrk_r(struct _reent *r, int incr) -{ -#if CH_USE_MEMCORE - void *p; - - chDbgCheck(incr > 0, "_sbrk_r"); - - (void)r; - p = chCoreAlloc((size_t)incr); - if (p == NULL) { - __errno_r(r) = ENOMEM; - return (caddr_t)-1; - } - return (caddr_t)p; -#else - __errno_r(r) = ENOMEM; - return (caddr_t)-1; -#endif -} - - -#else -/**** Locally used variables. ****/ -// mt: "cleaner": extern char* end; -extern char end[]; /* end is set in the linker command */ - /* file and is the end of statically */ - /* allocated data (thus start of heap). */ - -static char *heap_ptr; /* Points to current end of the heap. */ - -/************************** _sbrk_r ************************************* - * Support function. Adjusts end of heap to provide more memory to - * memory allocator. Simple and dumb with no sanity checks. - - * struct _reent *r -- re-entrancy structure, used by newlib to - * support multiple threads of operation. - * ptrdiff_t nbytes -- number of bytes to add. - * Returns pointer to start of new heap area. - * - * Note: This implementation is not thread safe (despite taking a - * _reent structure as a parameter). - * Since _s_r is not used in the current implementation, - * the following messages must be suppressed. - */ -void * _sbrk_r( - struct _reent *_s_r, - ptrdiff_t nbytes) -{ - char *base; /* errno should be set to ENOMEM on error */ - - if (!heap_ptr) { /* Initialize if first time through. */ - heap_ptr = end; - } - base = heap_ptr; /* Point to end of heap. */ - heap_ptr += nbytes; /* Increase heap. */ - - return base; /* Return pointer to start of new heap area. */ -} -#endif diff --git a/int/flash b/int/flash new file mode 100755 index 0000000..d8f717c --- /dev/null +++ b/int/flash @@ -0,0 +1,10 @@ +#!/bin/sh +openocd \ + -f interface/stlink-v2-1.cfg\ + -c "transport select hla_swd"\ + -f target/stm32f7x.cfg \ + -c init\ + -c "reset halt"\ + -c "flash write_image erase "build/mTask.bin" 0x08000000"\ + -c "reset run"\ + -c shutdown diff --git a/int/halconf.h b/int/halconf.h new file mode 100644 index 0000000..82602b4 --- /dev/null +++ b/int/halconf.h @@ -0,0 +1,388 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the QSPI subsystem. + */ +#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__) +#define HAL_USE_QSPI FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/int/interface.c b/int/interface.c new file mode 100644 index 0000000..5c9b500 --- /dev/null +++ b/int/interface.c @@ -0,0 +1,70 @@ +#include +#include +#include +#include + +#include "interface.h" +#include "ch.h" +#include "hal.h" + +//char buf[1024]; + +//Globals +bool input_available(void) +{ + return qSizeX(&(&SD3)->iqueue) > 0; +} + +uint8_t read_byte(void) +{ + return sdGet(&SD3); +} + +void write_byte(uint8_t b) +{ + sdPut(&SD3, b); +} + +void write_dpin(uint8_t i, bool b) +{ + (void) i; + (void) b; +} + +bool read_dpin(uint8_t i) +{ + return 0; + (void) i; +} + +void write_apin(uint8_t i, uint8_t a) +{ + (void)i; + (void)a; +} + +uint8_t read_apin(uint8_t i) +{ + return 0; + (void) i; +} + +long millis(void){ + return ST2MS(chVTGetSystemTime()); +} + +void delay(long ms) +{ + chThdSleepMilliseconds(ms); +} + +void setup(void) +{ + halInit(); + chSysInit(); + sdStart(&SD3, NULL); +} + +void test(void) +{ +} diff --git a/int/interface.h b/int/interface.h new file mode 100644 index 0000000..1547501 --- /dev/null +++ b/int/interface.h @@ -0,0 +1,39 @@ +#ifndef INTERFACE_H +#define INTERFACE_H + +#include +#include + +#ifndef STM +extern int gargc; +extern char **gargv; +#endif + +#define read16() 256*read_byte() + read_byte() +uint8_t read_byte(void); +void write_byte(uint8_t b); + +void write_dpin(uint8_t i, bool b); +bool read_dpin(uint8_t i); + +void write_apin(uint8_t i, uint8_t a); +uint8_t read_apin(uint8_t i); + +long millis(void); +bool input_available(void); +void delay(long ms); + +void setup(void); +void test(void); + +#ifdef STM +#define debug(s, ...) {}; +#define pdie(s) {}; +#define die(s, ...) {}; +#else +#define debug(s, ...) printf(s "\n", ##__VA_ARGS__); +#define pdie(s) {perror(s); exit(1);} +#define die(s, ...) {fprintf(stderr, s "\n", ##__VA_ARGS__); exit(1);} +#endif + +#endif diff --git a/int/nucleo-f767-blinky/src/interface_linux.c b/int/interface_linux.c similarity index 95% rename from int/nucleo-f767-blinky/src/interface_linux.c rename to int/interface_linux.c index 548730c..33fd003 100644 --- a/int/nucleo-f767-blinky/src/interface_linux.c +++ b/int/interface_linux.c @@ -32,13 +32,13 @@ void usage(FILE *o, char *arg0){ "-p PORT Custom port number, default: 8123\n" , arg0); } -long millis() { +long millis(void) { if (gettimeofday(&tv1, NULL) == -1) pdie("gettimeofday"); return tv1.tv_sec*1000 + tv1.tv_usec/1000; } -bool input_available(){ +bool input_available(void){ struct timeval tv; fd_set fds; tv.tv_sec = 0; @@ -53,7 +53,7 @@ bool input_available(){ return true; } -uint8_t read_byte() +uint8_t read_byte(void) { read(fd, &bt, 1); return bt; @@ -97,7 +97,7 @@ void delay(long ms) usleep(ms*1000); } -void setup() +void setup(void) { int port = 8123, opti = 1; //Register signal handler @@ -143,3 +143,8 @@ void setup() if((fd = accept(sock_fd, (struct sockaddr*)NULL, NULL)) == -1) pdie("accept"); } + +void test(void) +{ + +} diff --git a/int/nucleo-f767-blinky/src/interpret.c b/int/interpret.c similarity index 100% rename from int/nucleo-f767-blinky/src/interpret.c rename to int/interpret.c diff --git a/int/nucleo-f767-blinky/src/interpret.h b/int/interpret.h similarity index 100% rename from int/nucleo-f767-blinky/src/interpret.h rename to int/interpret.h diff --git a/int/nucleo-f767-blinky/src/main.c b/int/main.c similarity index 72% rename from int/nucleo-f767-blinky/src/main.c rename to int/main.c index 42c483e..026fd5d 100644 --- a/int/nucleo-f767-blinky/src/main.c +++ b/int/main.c @@ -3,19 +3,8 @@ #include #include -#ifdef STM32F767xx -#include "stm32f7xx_hal.h" -#include "gpio.h" -#include "usart.h" -#else +#ifndef STM #include -#include -#include -#include -#include -#include -#include -#include #endif #include "interpret.h" @@ -29,7 +18,7 @@ #define MSG_SDS_SPEC 's' #define MSG_SDS_UPD 'u' -void read_message() +void read_message(void) { //Find next task if(input_available()){ @@ -63,7 +52,7 @@ void read_message() } } -void loop() +void loop(void) { int ct; long cyclestart; @@ -91,8 +80,8 @@ void loop() } } -#ifdef STM32F767xx -int main1(void){ +#ifdef STM +int main(void){ #else int main(int argc, char *argv[]){ gargc = argc; @@ -104,28 +93,14 @@ int main(int argc, char *argv[]){ sds_init(); task_init(); - //debug("booting up"); + debug("booting up"); - int i = 0; while(true){ - //Check for new tasks -// debug("loop\r\n"); + //Check for newetasks + debug("loop"); loop(); + input_available(); delay(100); - i = (i + 1) % 3; - if(i == 0){ - SET_LED_RED; - RESET_LED_BLUE; - RESET_LED_GREEN; - } else if(i == 1){ - RESET_LED_RED; - SET_LED_BLUE; - RESET_LED_GREEN; - } else if(i == 2){ - RESET_LED_RED; - RESET_LED_BLUE; - SET_LED_GREEN; - } } return 0; } diff --git a/int/mcuconf.h b/int/mcuconf.h new file mode 100644 index 0000000..2886487 --- /dev/null +++ b/int/mcuconf.h @@ -0,0 +1,386 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F7xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 432 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 25 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_I2SSRC STM32_I2SSRC_PLLI2S +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SP_VALUE 4 +#define STM32_PLLI2SQ_VALUE 4 +#define STM32_PLLI2SR_VALUE 4 +#define STM32_PLLSAIN_VALUE 192 +#define STM32_PLLSAIP_VALUE 4 +#define STM32_PLLSAIQ_VALUE 4 +#define STM32_PLLSAIR_VALUE 4 +#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#define STM32_USART1SEL STM32_USART1SEL_PCLK2 +#define STM32_USART2SEL STM32_USART2SEL_PCLK1 +#define STM32_USART3SEL STM32_USART3SEL_PCLK1 +#define STM32_UART4SEL STM32_UART4SEL_PCLK1 +#define STM32_UART5SEL STM32_UART5SEL_PCLK1 +#define STM32_USART6SEL STM32_USART6SEL_PCLK2 +#define STM32_UART7SEL STM32_UART7SEL_PCLK1 +#define STM32_UART8SEL STM32_UART8SEL_PCLK1 +#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 +#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 +#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 +#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1 +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_CECSEL STM32_CECSEL_LSE +#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK +#define STM32_SRAM2_NOCACHE FALSE + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_USE_I2C4 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C4_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C4_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 +#define STM32_SDC_SDMMC_READ_TIMEOUT 1000 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 TRUE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_UART7_PRIORITY 12 +#define STM32_SERIAL_UART8_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +#endif /* MCUCONF_H */ diff --git a/int/nucleo-f767-blinky/.gitignore b/int/nucleo-f767-blinky/.gitignore deleted file mode 100644 index f60a380..0000000 --- a/int/nucleo-f767-blinky/.gitignore +++ /dev/null @@ -1,7 +0,0 @@ -*.bin -*.list -*.map -*.out -*.hex -o/* -a/* diff --git a/int/nucleo-f767-blinky/Makefile b/int/nucleo-f767-blinky/Makefile deleted file mode 100644 index 8b4f425..0000000 --- a/int/nucleo-f767-blinky/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -export - -#always set COMDIR (common sources, makefiles, libraries) first -COMDIR := ../com - -#set optimize/debug symbols options -OPTIMIZE := -O3 -g - -#set std libs to be linked -STDLIBS := -lm - -#include common project header -include $(COMDIR)/pj/pjhdr.mk - -#include target/os/lib specific header -include $(COMDIR)/pj/f767-nucleo-hal.mk -#SYSTEM := /usr/local/gcc-arm-none-eabi-4_8-2014q3/bin/arm-none-eabi -#SYSTEM := /usr/local/gcc-arm-none-eabi-4_9-2015q2/bin/arm-none-eabi -#SYSTEM := /usr/local/gcc-arm-none-eabi-4_9-2015q3/bin/arm-none-eabi -#SYSTEM := /usr/local/gcc-arm-none-eabi-5_2-2015q4/bin/arm-none-eabi - - -#include stm32cube header -include $(COMDIR)/pj/cube-hal.mk - -#include libraries -INCLIBS := inc - -include $(LIBDIR)/libstm32f7xxhal.mk - -#include common sources -INCLIBS := src - -include $(CSRCDIR)/syscalls.mk - -#start making -INCLIBS := mk - -#set ocd command (interface/target) -include $(COMDIR)/pj/oocd-stm32f7xx.mk -OCD = $(OCD-nucleo) - -#add sources -SRCS_C := $(filter-out src/interface_linux.c,$(wildcard $(SRCDIR)/*.c)) -SRCS_S := $(wildcard $(SRCDIR)/*.s) - -#include common project makefile -include $(COMDIR)/pj/pj.mk diff --git a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/cube_dma.h b/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/cube_dma.h deleted file mode 100644 index abccab0..0000000 --- a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/cube_dma.h +++ /dev/null @@ -1,10 +0,0 @@ -#define DMA_IRQ_USART3_TX DMA1_Stream3_IRQHandler -#ifdef DMAv2 -#define TCIF_USART3_TX ((DMA1->LISR & DMA_LISR_TCIF3)!=0) -#define CTCIF_USART3_TX (DMA1->LIFCR |= DMA_LIFCR_CTCIF3) -#endif -#ifdef DMAv1 -#define TCIF_USART3_TX ((DMA1->ISR & DMA_ISR_TCIF3)!=0) -#define CTCIF_USART3_TX (DMA1->IFCR |= DMA_IFCR_CTCIF3) -#endif - diff --git a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/dma.h b/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/dma.h deleted file mode 100644 index 9327666..0000000 --- a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/dma.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - ****************************************************************************** - * File Name : dma.h - * Description : This file contains all the function prototypes for - * the dma.c file - ****************************************************************************** - * - * COPYRIGHT(c) 2016 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __dma_H -#define __dma_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/* DMA memory to memory transfer handles -------------------------------------*/ -extern void Error_Handler(void); - -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* USER CODE BEGIN Private defines */ - -/* USER CODE END Private defines */ - -void MX_DMA_Init(void); - -/* USER CODE BEGIN Prototypes */ - -/* USER CODE END Prototypes */ - -#ifdef __cplusplus -} -#endif - -#endif /* __dma_H */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/gpio.h b/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/gpio.h deleted file mode 100644 index f2b3e70..0000000 --- a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/gpio.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - ****************************************************************************** - * File Name : gpio.h - * Description : This file contains all the functions prototypes for - * the gpio - ****************************************************************************** - * - * COPYRIGHT(c) 2016 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __gpio_H -#define __gpio_H -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* USER CODE BEGIN Private defines */ - -/* USER CODE END Private defines */ - -void MX_GPIO_Init(void); - -/* USER CODE BEGIN Prototypes */ - -/* USER CODE END Prototypes */ - -#ifdef __cplusplus -} -#endif -#endif /*__ pinoutConfig_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/mxconstants.h b/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/mxconstants.h deleted file mode 100644 index f3a29fe..0000000 --- a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/mxconstants.h +++ /dev/null @@ -1,109 +0,0 @@ -/** - ****************************************************************************** - * File Name : mxconstants.h - * Description : This file contains the common defines of the application - ****************************************************************************** - * - * COPYRIGHT(c) 2016 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MXCONSTANT_H -#define __MXCONSTANT_H - /* Includes ------------------------------------------------------------------*/ - -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Private define ------------------------------------------------------------*/ - -#define User_Blue_Button_Pin GPIO_PIN_13 -#define User_Blue_Button_GPIO_Port GPIOC -#define MCO_Pin GPIO_PIN_0 -#define MCO_GPIO_Port GPIOH -#define RMII_MDC_Pin GPIO_PIN_1 -#define RMII_MDC_GPIO_Port GPIOC -#define RMII_REF_CLK_Pin GPIO_PIN_1 -#define RMII_REF_CLK_GPIO_Port GPIOA -#define RMII_MDIO_Pin GPIO_PIN_2 -#define RMII_MDIO_GPIO_Port GPIOA -#define RMII_CRS_DV_Pin GPIO_PIN_7 -#define RMII_CRS_DV_GPIO_Port GPIOA -#define RMII_RXD0_Pin GPIO_PIN_4 -#define RMII_RXD0_GPIO_Port GPIOC -#define RMII_RXD1_Pin GPIO_PIN_5 -#define RMII_RXD1_GPIO_Port GPIOC -#define LD1_Pin GPIO_PIN_0 -#define LD1_GPIO_Port GPIOB -#define RMII_TXD1_Pin GPIO_PIN_13 -#define RMII_TXD1_GPIO_Port GPIOB -#define LD3_Pin GPIO_PIN_14 -#define LD3_GPIO_Port GPIOB -#define STLK_RX_Pin GPIO_PIN_8 -#define STLK_RX_GPIO_Port GPIOD -#define STLK_TX_Pin GPIO_PIN_9 -#define STLK_TX_GPIO_Port GPIOD -#define USB_PowerSwitchOn_Pin GPIO_PIN_6 -#define USB_PowerSwitchOn_GPIO_Port GPIOG -#define USB_OverCurrent_Pin GPIO_PIN_7 -#define USB_OverCurrent_GPIO_Port GPIOG -#define USB_SOF_Pin GPIO_PIN_8 -#define USB_SOF_GPIO_Port GPIOA -#define USB_VBUS_Pin GPIO_PIN_9 -#define USB_VBUS_GPIO_Port GPIOA -#define USB_ID_Pin GPIO_PIN_10 -#define USB_ID_GPIO_Port GPIOA -#define USB_DM_Pin GPIO_PIN_11 -#define USB_DM_GPIO_Port GPIOA -#define USB_DP_Pin GPIO_PIN_12 -#define USB_DP_GPIO_Port GPIOA -#define TMS_Pin GPIO_PIN_13 -#define TMS_GPIO_Port GPIOA -#define TCK_Pin GPIO_PIN_14 -#define TCK_GPIO_Port GPIOA -#define RMII_TX_EN_Pin GPIO_PIN_11 -#define RMII_TX_EN_GPIO_Port GPIOG -#define RMII_TXD0_Pin GPIO_PIN_13 -#define RMII_TXD0_GPIO_Port GPIOG -#define SW0_Pin GPIO_PIN_3 -#define SW0_GPIO_Port GPIOB -#define LD2_Pin GPIO_PIN_7 -#define LD2_GPIO_Port GPIOB -/* USER CODE BEGIN Private defines */ - -/* USER CODE END Private defines */ - -/** - * @} - */ - -/** - * @} -*/ - -#endif /* __MXCONSTANT_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/stm32f7xx_hal_conf.h b/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/stm32f7xx_hal_conf.h deleted file mode 100644 index 37d57e8..0000000 --- a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/stm32f7xx_hal_conf.h +++ /dev/null @@ -1,449 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_conf.h - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_CONF_H -#define __STM32F7xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "mxconstants.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED - -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -/* #define HAL_JPEG_MODULE_ENABLED */ -/* #define HAL_MDIOS_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_I2C_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)40000U) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define ART_ACCLERATOR_ENABLE 1U /* To enable instruction cache and prefetch */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1 */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848_PHY_ADDRESS Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) - -#define PHY_READ_TO ((uint32_t)0x0000FFFFU) -#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x11U) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x12U) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001U) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002U) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001U) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 0U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f7xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f7xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f7xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f7xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f7xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f7xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f7xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f7xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f7xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f7xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f7xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f7xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f7xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f7xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f7xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f7xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f7xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f7xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f7xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f7xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f7xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f7xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f7xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f7xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f7xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f7xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f7xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f7xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f7xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f7xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f7xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f7xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f7xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f7xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f7xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f7xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f7xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f7xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f7xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f7xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f7xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f7xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_JPEG_MODULE_ENABLED - #include "stm32f7xx_hal_jpeg.h" -#endif /* HAL_JPEG_MODULE_ENABLED */ - -#ifdef HAL_MDIOS_MODULE_ENABLED - #include "stm32f7xx_hal_mdios.h" -#endif /* HAL_MDIOS_MODULE_ENABLED */ -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/stm32f7xx_it.h b/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/stm32f7xx_it.h deleted file mode 100644 index 2d9e693..0000000 --- a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/stm32f7xx_it.h +++ /dev/null @@ -1,58 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_it.h - * @brief This file contains the headers of the interrupt handlers. - ****************************************************************************** - * - * COPYRIGHT(c) 2016 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_IT_H -#define __STM32F7xx_IT_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void SysTick_Handler(void); -void DMA1_Stream3_IRQHandler(void); -void USART3_IRQHandler(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_IT_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/usart.h b/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/usart.h deleted file mode 100644 index 8198628..0000000 --- a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Inc/usart.h +++ /dev/null @@ -1,75 +0,0 @@ -/** - ****************************************************************************** - * File Name : USART.h - * Description : This file provides code for the configuration - * of the USART instances. - ****************************************************************************** - * - * COPYRIGHT(c) 2016 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __usart_H -#define __usart_H -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -extern UART_HandleTypeDef huart3; - -/* USER CODE BEGIN Private defines */ - -/* USER CODE END Private defines */ - -extern void Error_Handler(void); - -void MX_USART3_UART_Init(void); - -/* USER CODE BEGIN Prototypes */ - -/* USER CODE END Prototypes */ - -#ifdef __cplusplus -} -#endif -#endif /*__ usart_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/cube_main.c b/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/cube_main.c deleted file mode 100644 index e231130..0000000 --- a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/cube_main.c +++ /dev/null @@ -1,207 +0,0 @@ -/** - ****************************************************************************** - * File Name : main.c - * Description : Main program body - ****************************************************************************** - * - * COPYRIGHT(c) 2016 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" -#include "dma.h" -#include "usart.h" -#include "gpio.h" - -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Private variables ---------------------------------------------------------*/ - -/* USER CODE BEGIN PV */ -/* Private variables ---------------------------------------------------------*/ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -void SystemClock_Config(void); -void Error_Handler(void); - -/* USER CODE BEGIN PFP */ -/* Private function prototypes -----------------------------------------------*/ - -void main1(void); -/* USER CODE END PFP */ - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -__weak -int main(void) -{ - - /* USER CODE BEGIN 1 */ - - /* USER CODE END 1 */ - - /* MCU Configuration----------------------------------------------------------*/ - - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); - - /* Configure the system clock */ - SystemClock_Config(); - - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_DMA_Init(); - MX_USART3_UART_Init(); - - /* USER CODE BEGIN 2 */ - - /* USER CODE END 2 */ - - /* Infinite loop */ -main1(); - /* USER CODE BEGIN WHILE */ - while (1) - { - /* USER CODE END WHILE */ - - /* USER CODE BEGIN 3 */ - - } - /* USER CODE END 3 */ - -} - -/** System Clock Configuration -*/ -void SystemClock_Config(void) -{ - - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; - - __HAL_RCC_PWR_CLK_ENABLE(); - - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 4; - RCC_OscInitStruct.PLL.PLLN = 200; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 2; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } - - if (HAL_PWREx_EnableOverDrive() != HAL_OK) - { - Error_Handler(); - } - - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK) - { - Error_Handler(); - } - - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3; - PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { - Error_Handler(); - } - - HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); - - HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); - - /* SysTick_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); -} - -/* USER CODE BEGIN 4 */ - -/* USER CODE END 4 */ - -/** - * @brief This function is executed in case of error occurrence. - * @param None - * @retval None - */ -void Error_Handler(void) -{ - /* USER CODE BEGIN Error_Handler */ - /* User can add his own implementation to report the HAL error return state */ - while(1) - { - } - /* USER CODE END Error_Handler */ -} - -#ifdef USE_FULL_ASSERT - -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ -void assert_failed(uint8_t* file, uint32_t line) -{ - /* USER CODE BEGIN 6 */ - /* User can add his own implementation to report the file name and line number, - ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - /* USER CODE END 6 */ - -} - -#endif - -/** - * @} - */ - -/** - * @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/cube_stm32f7xx_it.c b/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/cube_stm32f7xx_it.c deleted file mode 100644 index 96b81cb..0000000 --- a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/cube_stm32f7xx_it.c +++ /dev/null @@ -1,105 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_it.c - * @brief Interrupt Service Routines. - ****************************************************************************** - * - * COPYRIGHT(c) 2016 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" -#include "stm32f7xx.h" -#include "stm32f7xx_it.h" - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/* External variables --------------------------------------------------------*/ -extern DMA_HandleTypeDef hdma_usart3_tx; -extern UART_HandleTypeDef huart3; - -/******************************************************************************/ -/* Cortex-M7 Processor Interruption and Exception Handlers */ -/******************************************************************************/ - -/** -* @brief This function handles System tick timer. -*/ -void SysTick_Handler(void) -{ - /* USER CODE BEGIN SysTick_IRQn 0 */ - - /* USER CODE END SysTick_IRQn 0 */ - HAL_IncTick(); - HAL_SYSTICK_IRQHandler(); - /* USER CODE BEGIN SysTick_IRQn 1 */ - - /* USER CODE END SysTick_IRQn 1 */ -} - -/******************************************************************************/ -/* STM32F7xx Peripheral Interrupt Handlers */ -/* Add here the Interrupt Handlers for the used peripherals. */ -/* For the available peripheral interrupt handler names, */ -/* please refer to the startup file (startup_stm32f7xx.s). */ -/******************************************************************************/ - -/** -* @brief This function handles DMA1 stream3 global interrupt. -*/ -__weak -void DMA1_Stream3_IRQHandler(void) -{ - /* USER CODE BEGIN DMA1_Stream3_IRQn 0 */ - - /* USER CODE END DMA1_Stream3_IRQn 0 */ - HAL_DMA_IRQHandler(&hdma_usart3_tx); - /* USER CODE BEGIN DMA1_Stream3_IRQn 1 */ - - /* USER CODE END DMA1_Stream3_IRQn 1 */ -} - -/** -* @brief This function handles USART3 global interrupt. -*/ -__weak -void USART3_IRQHandler(void) -{ - /* USER CODE BEGIN USART3_IRQn 0 */ - - /* USER CODE END USART3_IRQn 0 */ - HAL_UART_IRQHandler(&huart3); - /* USER CODE BEGIN USART3_IRQn 1 */ - - /* USER CODE END USART3_IRQn 1 */ -} - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/dma.c b/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/dma.c deleted file mode 100644 index 99963af..0000000 --- a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/dma.c +++ /dev/null @@ -1,76 +0,0 @@ -/** - ****************************************************************************** - * File Name : dma.c - * Description : This file provides code for the configuration - * of all the requested memory to memory DMA transfers. - ****************************************************************************** - * - * COPYRIGHT(c) 2016 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "dma.h" - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/*----------------------------------------------------------------------------*/ -/* Configure DMA */ -/*----------------------------------------------------------------------------*/ - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ - -/** - * Enable DMA controller clock - */ -void MX_DMA_Init(void) -{ - /* DMA controller clock enable */ - __HAL_RCC_DMA1_CLK_ENABLE(); - - /* DMA interrupt init */ - /* DMA1_Stream3_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 2, 0); - HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn); - -} - -/* USER CODE BEGIN 2 */ - -/* USER CODE END 2 */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/gpio.c b/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/gpio.c deleted file mode 100644 index fe38206..0000000 --- a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/gpio.c +++ /dev/null @@ -1,252 +0,0 @@ -/** - ****************************************************************************** - * File Name : gpio.c - * Description : This file provides code for the configuration - * of all used GPIO pins. - ****************************************************************************** - * - * COPYRIGHT(c) 2016 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "gpio.h" -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/*----------------------------------------------------------------------------*/ -/* Configure GPIO */ -/*----------------------------------------------------------------------------*/ -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ - -/** Configure pins as - * Analog - * Input - * Output - * EVENT_OUT - * EXTI - * Free pins are configured automatically as Analog (this feature is enabled through - * the Code Generation settings) - PC1 ------> ETH_MDC - PA1 ------> ETH_REF_CLK - PA2 ------> ETH_MDIO - PA7 ------> ETH_CRS_DV - PC4 ------> ETH_RXD0 - PC5 ------> ETH_RXD1 - PB13 ------> ETH_TXD1 - PA8 ------> USB_OTG_FS_SOF - PA9 ------> USB_OTG_FS_VBUS - PA10 ------> USB_OTG_FS_ID - PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP - PG11 ------> ETH_TX_EN - PG13 ------> ETH_TXD0 -*/ -void MX_GPIO_Init(void) -{ - - GPIO_InitTypeDef GPIO_InitStruct; - - /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOE_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOF_CLK_ENABLE(); - __HAL_RCC_GPIOH_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOG_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); - - /*Configure GPIO pins : PE2 PE3 PE4 PE5 - PE6 PE7 PE8 PE9 - PE10 PE11 PE12 PE13 - PE14 PE15 PE0 PE1 */ - GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5 - |GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9 - |GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13 - |GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = User_Blue_Button_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(User_Blue_Button_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pins : PF0 PF1 PF2 PF3 - PF4 PF5 PF6 PF7 - PF8 PF9 PF10 PF11 - PF12 PF13 PF14 PF15 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7 - |GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 - |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - - /*Configure GPIO pins : PC0 PC2 PC3 PC6 - PC7 PC8 PC9 PC10 - PC11 PC12 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_6 - |GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_12; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /*Configure GPIO pins : PCPin PCPin PCPin */ - GPIO_InitStruct.Pin = RMII_MDC_Pin|RMII_RXD0_Pin|RMII_RXD1_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF11_ETH; - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /*Configure GPIO pins : PA0 PA3 PA4 PA5 - PA6 PA15 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5 - |GPIO_PIN_6|GPIO_PIN_15; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /*Configure GPIO pins : PAPin PAPin PAPin */ - GPIO_InitStruct.Pin = RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF11_ETH; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /*Configure GPIO pins : PBPin PBPin PBPin */ - GPIO_InitStruct.Pin = LD1_Pin|LD3_Pin|LD2_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /*Configure GPIO pins : PB1 PB2 PB10 PB11 - PB12 PB15 PB4 PB5 - PB6 PB8 PB9 */ - GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10|GPIO_PIN_11 - |GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_4|GPIO_PIN_5 - |GPIO_PIN_6|GPIO_PIN_8|GPIO_PIN_9; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /*Configure GPIO pins : PG0 PG1 PG2 PG3 - PG4 PG5 PG8 PG9 - PG10 PG12 PG14 PG15 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_8|GPIO_PIN_9 - |GPIO_PIN_10|GPIO_PIN_12|GPIO_PIN_14|GPIO_PIN_15; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = RMII_TXD1_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF11_ETH; - HAL_GPIO_Init(RMII_TXD1_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pins : PD10 PD11 PD12 PD13 - PD14 PD15 PD0 PD1 - PD2 PD3 PD4 PD5 - PD6 PD7 */ - GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13 - |GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1 - |GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5 - |GPIO_PIN_6|GPIO_PIN_7; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = USB_PowerSwitchOn_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(USB_PowerSwitchOn_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = USB_OverCurrent_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(USB_OverCurrent_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pins : PAPin PAPin PAPin PAPin */ - GPIO_InitStruct.Pin = USB_SOF_Pin|USB_ID_Pin|USB_DM_Pin|USB_DP_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = USB_VBUS_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(USB_VBUS_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pins : PGPin PGPin */ - GPIO_InitStruct.Pin = RMII_TX_EN_Pin|RMII_TXD0_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF11_ETH; - HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOB, LD1_Pin|LD3_Pin|LD2_Pin, GPIO_PIN_RESET); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(USB_PowerSwitchOn_GPIO_Port, USB_PowerSwitchOn_Pin, GPIO_PIN_RESET); - -} - -/* USER CODE BEGIN 2 */ - -/* USER CODE END 2 */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/main.c b/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/main.c deleted file mode 100644 index 2efc678..0000000 --- a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/main.c +++ /dev/null @@ -1,204 +0,0 @@ -/** - ****************************************************************************** - * File Name : main.c - * Description : Main program body - ****************************************************************************** - * - * COPYRIGHT(c) 2016 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" -#include "dma.h" -#include "usart.h" -#include "gpio.h" - -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Private variables ---------------------------------------------------------*/ - -/* USER CODE BEGIN PV */ -/* Private variables ---------------------------------------------------------*/ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -void SystemClock_Config(void); -void Error_Handler(void); - -/* USER CODE BEGIN PFP */ -/* Private function prototypes -----------------------------------------------*/ - -/* USER CODE END PFP */ - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -int main(void) -{ - - /* USER CODE BEGIN 1 */ - - /* USER CODE END 1 */ - - /* MCU Configuration----------------------------------------------------------*/ - - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); - - /* Configure the system clock */ - SystemClock_Config(); - - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_DMA_Init(); - MX_USART3_UART_Init(); - - /* USER CODE BEGIN 2 */ - - /* USER CODE END 2 */ - - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ - while (1) - { - /* USER CODE END WHILE */ - - /* USER CODE BEGIN 3 */ - - } - /* USER CODE END 3 */ - -} - -/** System Clock Configuration -*/ -void SystemClock_Config(void) -{ - - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; - - __HAL_RCC_PWR_CLK_ENABLE(); - - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 4; - RCC_OscInitStruct.PLL.PLLN = 200; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 2; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } - - if (HAL_PWREx_EnableOverDrive() != HAL_OK) - { - Error_Handler(); - } - - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK) - { - Error_Handler(); - } - - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3; - PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { - Error_Handler(); - } - - HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); - - HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); - - /* SysTick_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); -} - -/* USER CODE BEGIN 4 */ - -/* USER CODE END 4 */ - -/** - * @brief This function is executed in case of error occurrence. - * @param None - * @retval None - */ -void Error_Handler(void) -{ - /* USER CODE BEGIN Error_Handler */ - /* User can add his own implementation to report the HAL error return state */ - while(1) - { - } - /* USER CODE END Error_Handler */ -} - -#ifdef USE_FULL_ASSERT - -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ -void assert_failed(uint8_t* file, uint32_t line) -{ - /* USER CODE BEGIN 6 */ - /* User can add his own implementation to report the file name and line number, - ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - /* USER CODE END 6 */ - -} - -#endif - -/** - * @} - */ - -/** - * @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/stm32f7xx_hal_msp.c b/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/stm32f7xx_hal_msp.c deleted file mode 100644 index 0cf8ff6..0000000 --- a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/stm32f7xx_hal_msp.c +++ /dev/null @@ -1,86 +0,0 @@ -/** - ****************************************************************************** - * File Name : stm32f7xx_hal_msp.c - * Description : This file provides code for the MSP Initialization - * and de-Initialization codes. - ****************************************************************************** - * - * COPYRIGHT(c) 2016 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -extern void Error_Handler(void); -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/** - * Initializes the Global MSP. - */ -void HAL_MspInit(void) -{ - /* USER CODE BEGIN MspInit 0 */ - - /* USER CODE END MspInit 0 */ - - HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - - /* System interrupt init*/ - /* MemoryManagement_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0); - /* BusFault_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0); - /* UsageFault_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0); - /* SVCall_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0); - /* DebugMonitor_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0); - /* PendSV_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(PendSV_IRQn, 0, 0); - /* SysTick_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); - - /* USER CODE BEGIN MspInit 1 */ - - /* USER CODE END MspInit 1 */ -} - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/stm32f7xx_it.c b/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/stm32f7xx_it.c deleted file mode 100644 index 81b9e55..0000000 --- a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/stm32f7xx_it.c +++ /dev/null @@ -1,103 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_it.c - * @brief Interrupt Service Routines. - ****************************************************************************** - * - * COPYRIGHT(c) 2016 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" -#include "stm32f7xx.h" -#include "stm32f7xx_it.h" - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/* External variables --------------------------------------------------------*/ -extern DMA_HandleTypeDef hdma_usart3_tx; -extern UART_HandleTypeDef huart3; - -/******************************************************************************/ -/* Cortex-M7 Processor Interruption and Exception Handlers */ -/******************************************************************************/ - -/** -* @brief This function handles System tick timer. -*/ -void SysTick_Handler(void) -{ - /* USER CODE BEGIN SysTick_IRQn 0 */ - - /* USER CODE END SysTick_IRQn 0 */ - HAL_IncTick(); - HAL_SYSTICK_IRQHandler(); - /* USER CODE BEGIN SysTick_IRQn 1 */ - - /* USER CODE END SysTick_IRQn 1 */ -} - -/******************************************************************************/ -/* STM32F7xx Peripheral Interrupt Handlers */ -/* Add here the Interrupt Handlers for the used peripherals. */ -/* For the available peripheral interrupt handler names, */ -/* please refer to the startup file (startup_stm32f7xx.s). */ -/******************************************************************************/ - -/** -* @brief This function handles DMA1 stream3 global interrupt. -*/ -void DMA1_Stream3_IRQHandler(void) -{ - /* USER CODE BEGIN DMA1_Stream3_IRQn 0 */ - - /* USER CODE END DMA1_Stream3_IRQn 0 */ - HAL_DMA_IRQHandler(&hdma_usart3_tx); - /* USER CODE BEGIN DMA1_Stream3_IRQn 1 */ - - /* USER CODE END DMA1_Stream3_IRQn 1 */ -} - -/** -* @brief This function handles USART3 global interrupt. -*/ -void USART3_IRQHandler(void) -{ - /* USER CODE BEGIN USART3_IRQn 0 */ - - /* USER CODE END USART3_IRQn 0 */ - HAL_UART_IRQHandler(&huart3); - /* USER CODE BEGIN USART3_IRQn 1 */ - - /* USER CODE END USART3_IRQn 1 */ -} - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/usart.c b/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/usart.c deleted file mode 100644 index 2dfca4b..0000000 --- a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/Src/usart.c +++ /dev/null @@ -1,162 +0,0 @@ -/** - ****************************************************************************** - * File Name : USART.c - * Description : This file provides code for the configuration - * of the USART instances. - ****************************************************************************** - * - * COPYRIGHT(c) 2016 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usart.h" - -#include "gpio.h" -#include "dma.h" - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -UART_HandleTypeDef huart3; -DMA_HandleTypeDef hdma_usart3_tx; - -/* USART3 init function */ - -void MX_USART3_UART_Init(void) -{ - - huart3.Instance = USART3; - huart3.Init.BaudRate = 9600; - huart3.Init.WordLength = UART_WORDLENGTH_8B; - huart3.Init.StopBits = UART_STOPBITS_1; - huart3.Init.Parity = UART_PARITY_NONE; - huart3.Init.Mode = UART_MODE_TX_RX; - huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; - huart3.Init.OverSampling = UART_OVERSAMPLING_16; - huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&huart3) != HAL_OK) - { - Error_Handler(); - } - -} - -void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) -{ - - GPIO_InitTypeDef GPIO_InitStruct; - if(uartHandle->Instance==USART3) - { - /* USER CODE BEGIN USART3_MspInit 0 */ - - /* USER CODE END USART3_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_USART3_CLK_ENABLE(); - - /**USART3 GPIO Configuration - PD8 ------> USART3_TX - PD9 ------> USART3_RX - */ - GPIO_InitStruct.Pin = STLK_RX_Pin|STLK_TX_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF7_USART3; - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - - /* Peripheral DMA init*/ - - hdma_usart3_tx.Instance = DMA1_Stream3; - hdma_usart3_tx.Init.Channel = DMA_CHANNEL_4; - hdma_usart3_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; - hdma_usart3_tx.Init.PeriphInc = DMA_PINC_DISABLE; - hdma_usart3_tx.Init.MemInc = DMA_MINC_ENABLE; - hdma_usart3_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - hdma_usart3_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - hdma_usart3_tx.Init.Mode = DMA_NORMAL; - hdma_usart3_tx.Init.Priority = DMA_PRIORITY_LOW; - hdma_usart3_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; - if (HAL_DMA_Init(&hdma_usart3_tx) != HAL_OK) - { - Error_Handler(); - } - - __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart3_tx); - - /* Peripheral interrupt init */ - HAL_NVIC_SetPriority(USART3_IRQn, 2, 0); - HAL_NVIC_EnableIRQ(USART3_IRQn); - /* USER CODE BEGIN USART3_MspInit 1 */ - - /* USER CODE END USART3_MspInit 1 */ - } -} - -void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) -{ - - if(uartHandle->Instance==USART3) - { - /* USER CODE BEGIN USART3_MspDeInit 0 */ - - /* USER CODE END USART3_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_USART3_CLK_DISABLE(); - - /**USART3 GPIO Configuration - PD8 ------> USART3_TX - PD9 ------> USART3_RX - */ - HAL_GPIO_DeInit(GPIOD, STLK_RX_Pin|STLK_TX_Pin); - - /* Peripheral DMA DeInit*/ - HAL_DMA_DeInit(uartHandle->hdmatx); - - /* Peripheral interrupt Deinit*/ - HAL_NVIC_DisableIRQ(USART3_IRQn); - - } - /* USER CODE BEGIN USART3_MspDeInit 1 */ - - /* USER CODE END USART3_MspDeInit 1 */ -} - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/nucleo-f767-blinky.ioc b/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/nucleo-f767-blinky.ioc deleted file mode 100644 index 75c1c4f..0000000 --- a/int/nucleo-f767-blinky/cube/nucleo-f767-blinky/nucleo-f767-blinky.ioc +++ /dev/null @@ -1,318 +0,0 @@ -#MicroXplorer Configuration settings - do not modify -CORTEX_M7.CPU_DCache=Disabled -CORTEX_M7.CPU_ICache=Disabled -CORTEX_M7.FlashInterface=TCM_Enabled -CORTEX_M7.IPParameters=FlashInterface,CPU_ICache,CPU_DCache -Dma.Request0=USART3_TX -Dma.RequestsNb=1 -Dma.USART3_TX.0.Direction=DMA_MEMORY_TO_PERIPH -Dma.USART3_TX.0.FIFOMode=DMA_FIFOMODE_DISABLE -Dma.USART3_TX.0.Instance=DMA1_Stream3 -Dma.USART3_TX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE -Dma.USART3_TX.0.MemInc=DMA_MINC_ENABLE -Dma.USART3_TX.0.Mode=DMA_NORMAL -Dma.USART3_TX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE -Dma.USART3_TX.0.PeriphInc=DMA_PINC_DISABLE -Dma.USART3_TX.0.Priority=DMA_PRIORITY_LOW -Dma.USART3_TX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode -File.Version=6 -KeepUserPlacement=true -Mcu.Family=STM32F7 -Mcu.IP0=CORTEX_M7 -Mcu.IP1=DMA -Mcu.IP2=NVIC -Mcu.IP3=RCC -Mcu.IP4=SYS -Mcu.IP5=USART3 -Mcu.IPNb=6 -Mcu.Name=STM32F767Z(G-I)Tx -Mcu.Package=LQFP144 -Mcu.Pin0=PC13 -Mcu.Pin1=PC14/OSC32_IN -Mcu.Pin10=PC5 -Mcu.Pin11=PB0 -Mcu.Pin12=PB13 -Mcu.Pin13=PB14 -Mcu.Pin14=PD8 -Mcu.Pin15=PD9 -Mcu.Pin16=PG6 -Mcu.Pin17=PG7 -Mcu.Pin18=PA8 -Mcu.Pin19=PA9 -Mcu.Pin2=PC15/OSC32_OUT -Mcu.Pin20=PA10 -Mcu.Pin21=PA11 -Mcu.Pin22=PA12 -Mcu.Pin23=PA13 -Mcu.Pin24=PA14 -Mcu.Pin25=PG11 -Mcu.Pin26=PG13 -Mcu.Pin27=PB3 -Mcu.Pin28=PB7 -Mcu.Pin29=VP_SYS_VS_Systick -Mcu.Pin3=PH0/OSC_IN -Mcu.Pin4=PH1/OSC_OUT -Mcu.Pin5=PC1 -Mcu.Pin6=PA1 -Mcu.Pin7=PA2 -Mcu.Pin8=PA7 -Mcu.Pin9=PC4 -Mcu.PinsNb=30 -Mcu.UserConstants= -Mcu.UserName=STM32F767ZITx -MxCube.Version=4.15.1 -MxDb.Version=DB.4.0.151 -NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false -NVIC.DMA1_Stream3_IRQn=true\:2\:0\:true\:false\:true -NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false -NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:false -NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 -NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false -NVIC.SysTick_IRQn=true\:0\:0\:true\:false\:true -NVIC.USART3_IRQn=true\:2\:0\:true\:false\:true -NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false -PA1.GPIOParameters=GPIO_Label -PA1.GPIO_Label=RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0] -PA1.Locked=true -PA1.Signal=ETH_REF_CLK -PA10.GPIOParameters=GPIO_Label -PA10.GPIO_Label=USB_ID -PA10.Locked=true -PA10.Signal=USB_OTG_FS_ID -PA11.GPIOParameters=GPIO_Label -PA11.GPIO_Label=USB_DM -PA11.Locked=true -PA11.Signal=USB_OTG_FS_DM -PA12.GPIOParameters=GPIO_Label -PA12.GPIO_Label=USB_DP -PA12.Locked=true -PA12.Signal=USB_OTG_FS_DP -PA13.GPIOParameters=GPIO_Label -PA13.GPIO_Label=TMS -PA13.Locked=true -PA13.Mode=Serial_Wire -PA13.Signal=SYS_JTMS-SWDIO -PA14.GPIOParameters=GPIO_Label -PA14.GPIO_Label=TCK -PA14.Locked=true -PA14.Mode=Serial_Wire -PA14.Signal=SYS_JTCK-SWCLK -PA2.GPIOParameters=GPIO_Label -PA2.GPIO_Label=RMII_MDIO [LAN8742A-CZ-TR_MDIO] -PA2.Locked=true -PA2.Signal=ETH_MDIO -PA7.GPIOParameters=GPIO_Label -PA7.GPIO_Label=RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV] -PA7.Locked=true -PA7.Signal=ETH_CRS_DV -PA8.GPIOParameters=GPIO_Label -PA8.GPIO_Label=USB_SOF [TP1] -PA8.Locked=true -PA8.Signal=USB_OTG_FS_SOF -PA9.GPIOParameters=GPIO_Label -PA9.GPIO_Label=USB_VBUS -PA9.Locked=true -PA9.Signal=USB_OTG_FS_VBUS -PB0.GPIOParameters=GPIO_Label -PB0.GPIO_Label=LD1 [Green] -PB0.Locked=true -PB0.Signal=GPIO_Output -PB13.GPIOParameters=GPIO_Label -PB13.GPIO_Label=RMII_TXD1 [LAN8742A-CZ-TR_TXD1] -PB13.Locked=true -PB13.Signal=ETH_TXD1 -PB14.GPIOParameters=GPIO_Label -PB14.GPIO_Label=LD3 [Red] -PB14.Locked=true -PB14.Signal=GPIO_Output -PB3.GPIOParameters=GPIO_Label -PB3.GPIO_Label=SW0 -PB3.Locked=true -PB3.Signal=SYS_JTDO-SWO -PB7.GPIOParameters=GPIO_Label -PB7.GPIO_Label=LD2 [Blue] -PB7.Locked=true -PB7.Signal=GPIO_Output -PC1.GPIOParameters=GPIO_Label -PC1.GPIO_Label=RMII_MDC [LAN8742A-CZ-TR_MDC] -PC1.Locked=true -PC1.Signal=ETH_MDC -PC13.GPIOParameters=GPIO_Label -PC13.GPIO_Label=User Blue Button [B1] -PC13.Locked=true -PC13.Signal=GPIO_Input -PC14/OSC32_IN.Locked=true -PC14/OSC32_IN.Signal=RCC_OSC32_IN -PC15/OSC32_OUT.Locked=true -PC15/OSC32_OUT.Signal=RCC_OSC32_OUT -PC4.GPIOParameters=GPIO_Label -PC4.GPIO_Label=RMII_RXD0 [LAN8742A-CZ-TR_RXD0] -PC4.Locked=true -PC4.Signal=ETH_RXD0 -PC5.GPIOParameters=GPIO_Label -PC5.GPIO_Label=RMII_RXD1 [LAN8742A-CZ-TR_RXD1] -PC5.Locked=true -PC5.Signal=ETH_RXD1 -PCC.Checker=false -PCC.Line=STM32F7x7 -PCC.MCU=STM32F767Z(G-I)Tx -PCC.MXVersion=4.15.1 -PCC.PartNumber=STM32F767ZITx -PCC.Seq0=0 -PCC.Series=STM32F7 -PCC.Temperature=25 -PCC.Vdd=3.6 -PD8.GPIOParameters=GPIO_Label -PD8.GPIO_Label=STLK_RX [STM32F103CBT6_PA3] -PD8.Locked=true -PD8.Mode=Asynchronous -PD8.Signal=USART3_TX -PD9.GPIOParameters=GPIO_Label -PD9.GPIO_Label=STLK_TX [STM32F103CBT6_PA2] -PD9.Locked=true -PD9.Mode=Asynchronous -PD9.Signal=USART3_RX -PG11.GPIOParameters=GPIO_Label -PG11.GPIO_Label=RMII_TX_EN [LAN8742A-CZ-TR_TXEN] -PG11.Locked=true -PG11.Signal=ETH_TX_EN -PG13.GPIOParameters=GPIO_Label -PG13.GPIO_Label=RMII_TXD0 [LAN8742A-CZ-TR_TXD0] -PG13.Locked=true -PG13.Signal=ETH_TXD0 -PG6.GPIOParameters=GPIO_Label -PG6.GPIO_Label=USB_PowerSwitchOn [STMPS2151STR_EN] -PG6.Locked=true -PG6.Signal=GPIO_Output -PG7.GPIOParameters=GPIO_Label -PG7.GPIO_Label=USB_OverCurrent [STMPS2151STR_FAULT] -PG7.Locked=true -PG7.Signal=GPIO_Input -PH0/OSC_IN.GPIOParameters=GPIO_Label -PH0/OSC_IN.GPIO_Label=MCO [STM32F103CBT6_PA8] -PH0/OSC_IN.Locked=true -PH0/OSC_IN.Mode=HSE-External-Oscillator -PH0/OSC_IN.Signal=RCC_OSC_IN -PH1/OSC_OUT.Locked=true -PH1/OSC_OUT.Mode=HSE-External-Oscillator -PH1/OSC_OUT.Signal=RCC_OSC_OUT -ProjectManager.AskForMigrate=true -ProjectManager.BackupPrevious=false -ProjectManager.CompilerOptimize=2 -ProjectManager.ComputerToolchain=false -ProjectManager.CoupleFile=true -ProjectManager.DeletePrevious=true -ProjectManager.DeviceId=STM32F767ZITx -ProjectManager.FirmwarePackage=STM32Cube FW_F7 V1.4.0 -ProjectManager.FreePins=true -ProjectManager.HalAssertFull=false -ProjectManager.HeapSize=0x200 -ProjectManager.KeepUserCode=false -ProjectManager.LastFirmware=true -ProjectManager.LibraryCopy=2 -ProjectManager.PreviousToolchain=SW4STM32 -ProjectManager.ProjectBuild=false -ProjectManager.ProjectFileName=nucleo-f767-blinky.ioc -ProjectManager.ProjectName=nucleo-f767-blinky -ProjectManager.StackSize=0x400 -ProjectManager.TargetToolchain=SW4STM32 -ProjectManager.ToolChainLocation=/home/mg/ws1/stm32-templ1/nucleo-f767-blinky/cube/nucleo-f767-blinky -ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false,2-MX_DMA_Init-DMA-false,3-MX_USART3_UART_Init-USART3-false -RCC.48MHZClocksFreq_Value=24000000 -RCC.ADC12outputFreq_Value=72000000 -RCC.ADC34outputFreq_Value=72000000 -RCC.AHBFreq_Value=200000000 -RCC.APB1CLKDivider=RCC_HCLK_DIV4 -RCC.APB1Freq_Value=50000000 -RCC.APB1TimFreq_Value=100000000 -RCC.APB2CLKDivider=RCC_HCLK_DIV2 -RCC.APB2Freq_Value=100000000 -RCC.APB2TimFreq_Value=200000000 -RCC.CECFreq_Value=32786.88524590164 -RCC.CortexFreq_Value=200000000 -RCC.DFSDMAudioFreq_Value=192000000 -RCC.DFSDMFreq_Value=100000000 -RCC.EthernetFreq_Value=200000000 -RCC.FCLKCortexFreq_Value=200000000 -RCC.FamilyName=M -RCC.HCLKFreq_Value=200000000 -RCC.HSE_VALUE=8000000 -RCC.HSI_VALUE=16000000 -RCC.I2C1Freq_Value=50000000 -RCC.I2C2Freq_Value=50000000 -RCC.I2C3Freq_Value=50000000 -RCC.I2C4Freq_Value=50000000 -RCC.I2SClocksFreq_Value=48000000 -RCC.I2SFreq_Value=192000000 -RCC.IPParameters=48MHZClocksFreq_Value,ADC12outputFreq_Value,ADC34outputFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,DFSDMAudioFreq_Value,DFSDMFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SClocksFreq_Value,I2SFreq_Value,LCDTFTFreq_Value,LCDTFToutputFreq_Value,LPTIM1Freq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,MCO2PinFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SRoutputFreq_Value,PLLM,PLLMCOFreq_Value,PLLMUL,PLLN,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLRFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,PLLSAIoutputFreq_Value,PLLSourceVirtual,PRESCALERUSB,RNGFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC2Freq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,SYSCLKSourceVirtual,TIM15Freq_Value,TIM16Freq_Value,TIM17Freq_Value,TIM1Freq_Value,TIM20Freq_Value,TIM2Freq_Value,TIM3Freq_Value,TIM8Freq_Value,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutput2Freq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VcooutputI2S,WatchDogFreq_Value -RCC.LCDTFTFreq_Value=96000000 -RCC.LCDTFToutputFreq_Value=24000000 -RCC.LPTIM1Freq_Value=50000000 -RCC.LSE_VALUE=32768 -RCC.LSI_VALUE=40000 -RCC.MCO1PinFreq_Value=16000000 -RCC.MCO2PinFreq_Value=200000000 -RCC.MCOFreq_Value=72000000 -RCC.PLLCLKFreq_Value=200000000 -RCC.PLLI2SPCLKFreq_Value=192000000 -RCC.PLLI2SQCLKFreq_Value=192000000 -RCC.PLLI2SRCLKFreq_Value=192000000 -RCC.PLLI2SRoutputFreq_Value=192000000 -RCC.PLLM=4 -RCC.PLLMCOFreq_Value=72000000 -RCC.PLLMUL=RCC_PLL_MUL9 -RCC.PLLN=200 -RCC.PLLQCLKFreq_Value=200000000 -RCC.PLLQoutputFreq_Value=200000000 -RCC.PLLRFreq_Value=200000000 -RCC.PLLSAIPCLKFreq_Value=192000000 -RCC.PLLSAIQCLKFreq_Value=192000000 -RCC.PLLSAIRCLKFreq_Value=192000000 -RCC.PLLSAIoutputFreq_Value=192000000 -RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE -RCC.PRESCALERUSB=RCC_USBCLKSOURCE_PLL_DIV1_5 -RCC.RNGFreq_Value=200000000 -RCC.RTCFreq_Value=40000 -RCC.RTCHSEDivFreq_Value=4000000 -RCC.SAI1Freq_Value=192000000 -RCC.SAI2Freq_Value=192000000 -RCC.SDMMC2Freq_Value=200000000 -RCC.SDMMCFreq_Value=200000000 -RCC.SPDIFRXFreq_Value=192000000 -RCC.SYSCLKFreq_VALUE=200000000 -RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK -RCC.SYSCLKSourceVirtual=RCC_SYSCLKSOURCE_PLLCLK -RCC.TIM15Freq_Value=72000000 -RCC.TIM16Freq_Value=72000000 -RCC.TIM17Freq_Value=72000000 -RCC.TIM1Freq_Value=72000000 -RCC.TIM20Freq_Value=72000000 -RCC.TIM2Freq_Value=72000000 -RCC.TIM3Freq_Value=72000000 -RCC.TIM8Freq_Value=72000000 -RCC.UART4Freq_Value=50000000 -RCC.UART5Freq_Value=50000000 -RCC.UART7Freq_Value=50000000 -RCC.UART8Freq_Value=50000000 -RCC.USART1Freq_Value=100000000 -RCC.USART2Freq_Value=50000000 -RCC.USART3Freq_Value=50000000 -RCC.USART6Freq_Value=100000000 -RCC.USBFreq_Value=200000000 -RCC.VCOI2SOutputFreq_Value=384000000 -RCC.VCOInputFreq_Value=2000000 -RCC.VCOOutput2Freq_Value=8000000 -RCC.VCOOutputFreq_Value=400000000 -RCC.VCOSAIOutputFreq_Value=384000000 -RCC.VcooutputI2S=48000000 -RCC.WatchDogFreq_Value=40000 -USART3.IPParameters=WordLength -USART3.WordLength=UART_WORDLENGTH_8B -VP_SYS_VS_Systick.Mode=SysTick -VP_SYS_VS_Systick.Signal=SYS_VS_Systick -board=NUCLEO-F767ZI -boardIOC=true diff --git a/int/nucleo-f767-blinky/src/interface.c b/int/nucleo-f767-blinky/src/interface.c deleted file mode 100644 index 260919c..0000000 --- a/int/nucleo-f767-blinky/src/interface.c +++ /dev/null @@ -1,125 +0,0 @@ -#include -#include -#include -#include - -#include "stm32f7xx_hal.h" -#include "usart.h" -#include "gpio.h" -#include "interface.h" - -#define SET_LED_RED GPIOB->BSRR = GPIO_PIN_14 -#define RESET_LED_RED GPIOB->BSRR = GPIO_PIN_14 << 16 - -#define SET_LED_BLUE GPIOB->BSRR = GPIO_PIN_7 -#define RESET_LED_BLUE GPIOB->BSRR = GPIO_PIN_7 << 16 - -#define SET_LED_GREEN GPIOB->BSRR = GPIO_PIN_0 -#define RESET_LED_GREEN GPIOB->BSRR = GPIO_PIN_0 << 16 - - -#define BUFSIZE 1024 - -//Globals -char buf[128]; -volatile bool sending = false; -uint8_t circbuf[BUFSIZE]; -uint16_t readpos, writepos; -uint8_t readb; - -void _exit(int i){ - while(1); - (void)i; -} - -void HAL_UART_TxCpltCallback(UART_HandleTypeDef *UartHandle) -{ - sending = false; -} - -int i = 0; -void HAL_UART_RxCpltCallback(UART_HandleTypeDef *UartHandle) -{ - if(writepos == BUFSIZE){ - writepos = 0; - } - circbuf[writepos++] = readb; - HAL_UART_Receive_DMA(&huart3, &readb, 1); -} - -bool input_available() -{ - return readpos != writepos; -} - -uint8_t read_byte() -{ - while(sending){ - HAL_Delay(5); - } - if(readpos == BUFSIZE){ - readpos = 0; - } - return circbuf[readpos++]; -} - -void write_byte(uint8_t b) -{ - while(sending){ - HAL_Delay(5); - } - sending = true; - HAL_UART_Transmit_IT(&huart3, &b, 1); -} - -void write_dpin(uint8_t i, bool b) -{ - (void) i; - (void) b; -} - -bool read_dpin(uint8_t i) -{ - return 0; - (void) i; -} - -void write_apin(uint8_t i, uint8_t a) -{ - if(i == 1){ - SET_LED_RED; - RESET_LED_BLUE; - RESET_LED_GREEN; - } else if(i == 2){ - RESET_LED_RED; - SET_LED_BLUE; - RESET_LED_GREEN; - } else if(i == 3){ - RESET_LED_RED; - RESET_LED_BLUE; - SET_LED_GREEN; - } -} - -uint8_t read_apin(uint8_t i) -{ - return 0; - (void) i; -} - -long millis(){ - return HAL_GetTick(); -} - -void delay(long ms) -{ - HAL_Delay(ms); -} - -void setup() -{ - readpos = 0; - writepos = 0; - HAL_UART_Receive_DMA(&huart3, &readb, 1); - write_byte('b'); -} diff --git a/int/nucleo-f767-blinky/src/interface.h b/int/nucleo-f767-blinky/src/interface.h deleted file mode 100644 index a01905e..0000000 --- a/int/nucleo-f767-blinky/src/interface.h +++ /dev/null @@ -1,71 +0,0 @@ -#ifndef MAIN_H -#define MAIN_H - -#include -#include -#include -#include - -#ifdef STM32F767xx -#include "stm32f7xx_hal.h" -#include "gpio.h" -#include "usart.h" -#include "serial.h" - -#define SET_LED_RED GPIOB->BSRR = GPIO_PIN_14 -#define RESET_LED_RED GPIOB->BSRR = GPIO_PIN_14 << 16 - -#define SET_LED_BLUE GPIOB->BSRR = GPIO_PIN_7 -#define RESET_LED_BLUE GPIOB->BSRR = GPIO_PIN_7 << 16 - -#define SET_LED_GREEN GPIOB->BSRR = GPIO_PIN_0 -#define RESET_LED_GREEN GPIOB->BSRR = GPIO_PIN_0 << 16 - -#endif - -#ifdef STM32F767xx -extern char buf[128]; -#else -extern int gargc; -extern char **gargv; -#endif - -uint8_t read_byte(); -void write_byte(uint8_t b); - -void write_dpin(uint8_t i, bool b); -bool read_dpin(uint8_t i); - -void write_apin(uint8_t i, uint8_t a); -uint8_t read_apin(uint8_t i); - -long millis(); -bool input_available(); -void delay(long ms); - -void setup(); - -#define read16() 256*read_byte() + read_byte() -#ifdef STM32F767xx -#define debug(s, ...) ; -//#define debug(s, ...) {\ -// sprintf(buf, "m" s "\n", ##__VA_ARGS__);\ -// for(int _i = 0; _i - -extern volatile char uartf; - -void init(); -bool input_av(); -uint8_t read_byte(); -void write_byte(uint8_t b); -#endif diff --git a/int/nucleo-f767-blinky/src/sds.c b/int/sds.c similarity index 96% rename from int/nucleo-f767-blinky/src/sds.c rename to int/sds.c index cd6452b..b424ff7 100644 --- a/int/nucleo-f767-blinky/src/sds.c +++ b/int/sds.c @@ -13,12 +13,12 @@ struct sds sdss[MAXSDSS]; uint8_t c; -void sds_init() +void sds_init(void) { memset(&sdss, 0, sizeof(struct sds)*MAXSDSS); } -void sds_register() +void sds_register(void) { uint8_t cs; for(cs = 0; cs